TimeQuest Timing Analyzer report for atari800core
Fri Jun 14 21:19:08 2024
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 14. Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 15. Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 16. Slow 1200mV 85C Model Setup: 'SPI_SCK'
 17. Slow 1200mV 85C Model Setup: 'clk_27'
 18. Slow 1200mV 85C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 19. Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 20. Slow 1200mV 85C Model Hold: 'SPI_SCK'
 21. Slow 1200mV 85C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 22. Slow 1200mV 85C Model Hold: 'clk_27'
 23. Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 24. Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 25. Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 26. Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 27. Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 28. Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 29. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 30. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 31. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 32. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
 33. Slow 1200mV 85C Model Minimum Pulse Width: 'clk_27'
 34. Slow 1200mV 85C Model Minimum Pulse Width: 'SPI_SCK'
 35. Slow 1200mV 85C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 36. Setup Times
 37. Hold Times
 38. Clock to Output Times
 39. Minimum Clock to Output Times
 40. Propagation Delay
 41. Minimum Propagation Delay
 42. Output Enable Times
 43. Minimum Output Enable Times
 44. Output Disable Times
 45. Minimum Output Disable Times
 46. Slow 1200mV 85C Model Metastability Report
 47. Slow 1200mV 0C Model Fmax Summary
 48. Slow 1200mV 0C Model Setup Summary
 49. Slow 1200mV 0C Model Hold Summary
 50. Slow 1200mV 0C Model Recovery Summary
 51. Slow 1200mV 0C Model Removal Summary
 52. Slow 1200mV 0C Model Minimum Pulse Width Summary
 53. Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 54. Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 55. Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 56. Slow 1200mV 0C Model Setup: 'SPI_SCK'
 57. Slow 1200mV 0C Model Setup: 'clk_27'
 58. Slow 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 59. Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 60. Slow 1200mV 0C Model Hold: 'SPI_SCK'
 61. Slow 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 62. Slow 1200mV 0C Model Hold: 'clk_27'
 63. Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 64. Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 65. Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 66. Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 67. Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 68. Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 69. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 70. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 71. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 72. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
 73. Slow 1200mV 0C Model Minimum Pulse Width: 'clk_27'
 74. Slow 1200mV 0C Model Minimum Pulse Width: 'SPI_SCK'
 75. Slow 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 76. Setup Times
 77. Hold Times
 78. Clock to Output Times
 79. Minimum Clock to Output Times
 80. Propagation Delay
 81. Minimum Propagation Delay
 82. Output Enable Times
 83. Minimum Output Enable Times
 84. Output Disable Times
 85. Minimum Output Disable Times
 86. Slow 1200mV 0C Model Metastability Report
 87. Fast 1200mV 0C Model Setup Summary
 88. Fast 1200mV 0C Model Hold Summary
 89. Fast 1200mV 0C Model Recovery Summary
 90. Fast 1200mV 0C Model Removal Summary
 91. Fast 1200mV 0C Model Minimum Pulse Width Summary
 92. Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 93. Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 94. Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 95. Fast 1200mV 0C Model Setup: 'SPI_SCK'
 96. Fast 1200mV 0C Model Setup: 'clk_27'
 97. Fast 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 98. Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 99. Fast 1200mV 0C Model Hold: 'SPI_SCK'
100. Fast 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
101. Fast 1200mV 0C Model Hold: 'clk_27'
102. Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
103. Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
104. Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
105. Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
106. Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
107. Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
108. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
109. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
110. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
111. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
112. Fast 1200mV 0C Model Minimum Pulse Width: 'clk_27'
113. Fast 1200mV 0C Model Minimum Pulse Width: 'SPI_SCK'
114. Fast 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
115. Setup Times
116. Hold Times
117. Clock to Output Times
118. Minimum Clock to Output Times
119. Propagation Delay
120. Minimum Propagation Delay
121. Output Enable Times
122. Minimum Output Enable Times
123. Output Disable Times
124. Minimum Output Disable Times
125. Fast 1200mV 0C Model Metastability Report
126. Multicorner Timing Analysis Summary
127. Setup Times
128. Hold Times
129. Clock to Output Times
130. Minimum Clock to Output Times
131. Progagation Delay
132. Minimum Progagation Delay
133. Board Trace Model Assignments
134. Input Transition Times
135. Slow Corner Signal Integrity Metrics
136. Fast Corner Signal Integrity Metrics
137. Setup Transfers
138. Hold Transfers
139. Recovery Transfers
140. Removal Transfers
141. Report TCCS
142. Report RSKM
143. Unconstrained Paths
144. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
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to the terms and conditions of the Altera Program License 
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Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; atari800core                                                      ;
; Device Family      ; Cyclone III                                                       ;
; Device Name        ; EP3C25E144C8                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Combined                                                          ;
; Rise/Fall Delays   ; Enabled                                                           ;
+--------------------+-------------------------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 8           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.50        ;
; Maximum used               ; 4           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-4         ;  16.7%      ;
;     Processors 5-8         ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------+
; SDC File List                                        ;
+------------------+--------+--------------------------+
; SDC File Path    ; Status ; Read at                  ;
+------------------+--------+--------------------------+
; atari800core.sdc ; OK     ; Fri Jun 14 21:19:03 2024 ;
+------------------+--------+--------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+-----------------------------------------------------------------------+-----------+--------+------------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------------------------------------------------------------------+-------------------------------------------------------------------------+---------------------------------------------------------------------------+
; Clock Name                                                            ; Type      ; Period ; Frequency  ; Rise   ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase  ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                                               ; Source                                                                  ; Targets                                                                   ;
+-----------------------------------------------------------------------+-----------+--------+------------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------------------------------------------------------------------+-------------------------------------------------------------------------+---------------------------------------------------------------------------+
; clk_27                                                                ; Base      ; 37.037 ; 27.0 MHz   ; 0.000  ; 18.518 ;            ;           ;             ;        ;        ;           ;            ;          ;                                                                      ;                                                                         ; { CLOCK_27[0] }                                                           ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 8.810  ; 113.51 MHz ; 0.000  ; 4.405  ; 50.00      ; 27        ; 100         ;        ;        ;           ;            ; false    ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] } ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 17.621 ; 56.75 MHz  ; 0.000  ; 8.810  ; 50.00      ; 27        ; 50          ;        ;        ;           ;            ; false    ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] } ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 8.810  ; 113.51 MHz ; -2.447 ; 1.958  ; 50.00      ; 27        ; 100         ; -100.0 ;        ;           ;            ; false    ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] } ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; Generated ; 32.631 ; 30.65 MHz  ; 0.000  ; 16.315 ; 50.00      ; 200       ; 227         ;        ;        ;           ;            ; false    ; clk_27                                                               ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]  ; { pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] }  ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; Generated ; 83.333 ; 12.0 MHz   ; 0.000  ; 41.666 ; 50.00      ; 9         ; 4           ;        ;        ;           ;            ; false    ; clk_27                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]              ; { reconfig_pll|altpll_component|auto_generated|pll1|clk[0] }              ;
; SPI_SCK                                                               ; Base      ; 41.666 ; 24.0 MHz   ; 20.800 ; 41.666 ;            ;           ;             ;        ;        ;           ;            ;          ;                                                                      ;                                                                         ; { SPI_SCK }                                                               ;
+-----------------------------------------------------------------------+-----------+--------+------------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------------------------------------------------------------------+-------------------------------------------------------------------------+---------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                                                                   ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                            ; Note                                                          ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
; 54.28 MHz  ; 54.28 MHz       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                               ;
; 70.75 MHz  ; 70.75 MHz       ; SPI_SCK                                                               ;                                                               ;
; 99.26 MHz  ; 99.26 MHz       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ;                                                               ;
; 129.48 MHz ; 129.48 MHz      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                               ;
; 327.44 MHz ; 250.0 MHz       ; clk_27                                                                ; limit due to minimum period restriction (max I/O toggle rate) ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                            ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.595 ; -1.595        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -0.801 ; -1.506        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.942  ; 0.000         ;
; SPI_SCK                                                               ; 13.788 ; 0.000         ;
; clk_27                                                                ; 33.983 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 36.629 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                            ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.353 ; 0.000         ;
; SPI_SCK                                                               ; 0.427 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 0.454 ; 0.000         ;
; clk_27                                                                ; 0.455 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.455 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 2.208 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+-----------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                        ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.219 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.628 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+-----------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                         ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.590 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.901 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                              ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.093  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 4.193  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.378  ; 0.000         ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 16.275 ; 0.000         ;
; clk_27                                                                ; 18.278 ; 0.000         ;
; SPI_SCK                                                               ; 20.416 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 40.596 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                  ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -1.595 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.958        ; -2.033     ; 1.288      ;
; 2.572  ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                ; SDRAM_A[5]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.931      ; 4.112      ;
; 2.579  ; sdram_statemachine:sdram_adaptor|addr_reg[11]                               ; SDRAM_A[11]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.938      ; 4.112      ;
; 2.581  ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                             ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.940      ; 4.112      ;
; 2.583  ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                ; SDRAM_A[7]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.932      ; 4.102      ;
; 2.583  ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                ; SDRAM_A[8]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.932      ; 4.102      ;
; 2.586  ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                ; SDRAM_A[9]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.935      ; 4.102      ;
; 2.588  ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                ; SDRAM_A[6]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.937      ; 4.102      ;
; 2.589  ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                             ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.938      ; 4.102      ;
; 2.589  ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                             ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.938      ; 4.102      ;
; 2.590  ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                             ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.939      ; 4.102      ;
; 2.591  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5                 ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.899      ; 4.061      ;
; 2.600  ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.949      ; 4.102      ;
; 2.601  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4                 ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.899      ; 4.051      ;
; 2.601  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6                 ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.899      ; 4.051      ;
; 2.602  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7                 ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.900      ; 4.051      ;
; 2.604  ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                              ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.953      ; 4.102      ;
; 2.606  ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                              ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.945      ; 4.092      ;
; 2.606  ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                              ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.945      ; 4.092      ;
; 2.607  ; sdram_statemachine:sdram_adaptor|udqm_reg                                   ; SDRAM_DQMH                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.946      ; 4.092      ;
; 2.620  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.956      ; 4.089      ;
; 2.620  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.956      ; 4.089      ;
; 2.624  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2                 ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.960      ; 4.089      ;
; 2.624  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3                 ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.960      ; 4.089      ;
; 2.628  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.954      ; 4.079      ;
; 2.628  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.954      ; 4.079      ;
; 2.629  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.955      ; 4.079      ;
; 2.629  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.955      ; 4.079      ;
; 2.639  ; sdram_statemachine:sdram_adaptor|dq_output_reg                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.965      ; 4.079      ;
; 2.643  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1                 ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.969      ; 4.079      ;
; 2.645  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8                 ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.961      ; 4.069      ;
; 2.645  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9                 ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.961      ; 4.069      ;
; 2.708  ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                              ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.883      ; 3.928      ;
; 2.718  ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                ; SDRAM_A[3]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.883      ; 3.918      ;
; 2.718  ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                              ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.883      ; 3.918      ;
; 2.718  ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                              ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.883      ; 3.918      ;
; 2.719  ; sdram_statemachine:sdram_adaptor|we_n_reg                                   ; SDRAM_nWE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.884      ; 3.918      ;
; 2.719  ; sdram_statemachine:sdram_adaptor|ldqm_reg                                   ; SDRAM_DQML                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.884      ; 3.918      ;
; 2.719  ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                              ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.884      ; 3.918      ;
; 2.728  ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                ; SDRAM_A[4]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.928      ; 3.953      ;
; 2.729  ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                ; SDRAM_A[1]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.884      ; 3.908      ;
; 2.729  ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                ; SDRAM_A[2]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.884      ; 3.908      ;
; 2.731  ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                ; SDRAM_A[0]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.886      ; 3.908      ;
; 2.731  ; sdram_statemachine:sdram_adaptor|addr_reg[10]                               ; SDRAM_A[10]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.886      ; 3.908      ;
; 2.731  ; sdram_statemachine:sdram_adaptor|ba_reg[0]                                  ; SDRAM_BA[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.886      ; 3.908      ;
; 2.731  ; sdram_statemachine:sdram_adaptor|cas_n_reg                                  ; SDRAM_nCAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.886      ; 3.908      ;
; 2.732  ; sdram_statemachine:sdram_adaptor|ras_n_reg                                  ; SDRAM_nRAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.887      ; 3.908      ;
; 2.740  ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                             ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.940      ; 3.953      ;
; 2.741  ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                  ; SDRAM_BA[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.886      ; 3.898      ;
; 2.744  ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                              ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.944      ; 3.953      ;
; 2.744  ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                              ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.944      ; 3.953      ;
; 2.749  ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                             ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.939      ; 3.943      ;
; 3.618  ; sdram_statemachine:sdram_adaptor|cke_reg                                    ; SDRAM_CKE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.877      ; 3.012      ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                              ;
+--------+------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                              ; To Node                                                                                                                ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -0.801 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 18.344     ;
; -0.574 ; reset_load                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.104     ; 18.092     ;
; -0.554 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 18.097     ;
; -0.397 ; cart_type_byte[3]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 17.946     ;
; -0.385 ; ioctl_state.IOCTL_IDLE                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 17.900     ;
; -0.339 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 17.886     ;
; -0.275 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 17.790     ;
; -0.263 ; cart_type_byte[2]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 17.814     ;
; -0.231 ; DMA_16BIT_WRITE_ENABLE_IOCTL                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 17.746     ;
; -0.180 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 17.723     ;
; -0.172 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 17.687     ;
; -0.153 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 17.668     ;
; -0.141 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.390      ; 18.153     ;
; -0.141 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.390      ; 18.153     ;
; -0.141 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.390      ; 18.153     ;
; -0.141 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.390      ; 18.153     ;
; -0.141 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.390      ; 18.153     ;
; -0.140 ; cart_type_byte[0]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 17.689     ;
; -0.123 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 17.556     ;
; -0.118 ; user_io:my_user_io|status[1]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 17.665     ;
; -0.109 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 17.656     ;
; -0.071 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.544     ; 17.149     ;
; -0.046 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[0]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.548     ; 17.120     ;
; -0.031 ; cart_type_byte[4]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 17.580     ;
; 0.041  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.545     ; 17.036     ;
; 0.086  ; reset_load                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.365      ; 17.901     ;
; 0.086  ; reset_load                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.365      ; 17.901     ;
; 0.086  ; reset_load                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.365      ; 17.901     ;
; 0.086  ; reset_load                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.365      ; 17.901     ;
; 0.086  ; reset_load                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.365      ; 17.901     ;
; 0.090  ; cart_type_byte[6]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 17.459     ;
; 0.106  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.390      ; 17.906     ;
; 0.106  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.390      ; 17.906     ;
; 0.106  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.390      ; 17.906     ;
; 0.106  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.390      ; 17.906     ;
; 0.106  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.390      ; 17.906     ;
; 0.163  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.568     ; 16.891     ;
; 0.169  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.548     ; 16.905     ;
; 0.171  ; cart_type_byte[5]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 17.378     ;
; 0.177  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[3]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.060     ; 17.385     ;
; 0.208  ; DMA_ADDR_FETCH_IOCTL[18]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.076     ; 17.338     ;
; 0.215  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 17.323     ;
; 0.215  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 17.323     ;
; 0.215  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 17.323     ;
; 0.217  ; cart_type_byte[1]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 17.332     ;
; 0.223  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 17.320     ;
; 0.246  ; user_io:my_user_io|but_sw[1]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 17.273     ;
; 0.252  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.056     ; 17.314     ;
; 0.262  ; cart_type_byte[7]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 17.287     ;
; 0.263  ; cart_type_byte[3]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.396      ; 17.755     ;
; 0.263  ; cart_type_byte[3]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.396      ; 17.755     ;
; 0.263  ; cart_type_byte[3]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.396      ; 17.755     ;
; 0.263  ; cart_type_byte[3]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.396      ; 17.755     ;
; 0.263  ; cart_type_byte[3]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.396      ; 17.755     ;
; 0.274  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 17.250     ;
; 0.274  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 17.250     ;
; 0.275  ; ioctl_state.IOCTL_IDLE                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.362      ; 17.709     ;
; 0.275  ; ioctl_state.IOCTL_IDLE                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.362      ; 17.709     ;
; 0.275  ; ioctl_state.IOCTL_IDLE                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.362      ; 17.709     ;
; 0.275  ; ioctl_state.IOCTL_IDLE                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.362      ; 17.709     ;
; 0.275  ; ioctl_state.IOCTL_IDLE                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.362      ; 17.709     ;
; 0.295  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.351      ; 17.678     ;
; 0.295  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.351      ; 17.678     ;
; 0.295  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.351      ; 17.678     ;
; 0.295  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.351      ; 17.678     ;
; 0.295  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.351      ; 17.678     ;
; 0.295  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.351      ; 17.678     ;
; 0.309  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[5]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.060     ; 17.253     ;
; 0.319  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.083     ; 17.220     ;
; 0.321  ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.394      ; 17.695     ;
; 0.321  ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.394      ; 17.695     ;
; 0.321  ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.394      ; 17.695     ;
; 0.321  ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.394      ; 17.695     ;
; 0.321  ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.394      ; 17.695     ;
; 0.326  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.568     ; 16.728     ;
; 0.338  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.338      ; 17.622     ;
; 0.361  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 17.187     ;
; 0.361  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 17.180     ;
; 0.363  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.592     ; 16.667     ;
; 0.368  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 17.153     ;
; 0.368  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 17.153     ;
; 0.370  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.528     ; 16.724     ;
; 0.385  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.362      ; 17.599     ;
; 0.385  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.362      ; 17.599     ;
; 0.385  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.362      ; 17.599     ;
; 0.385  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.362      ; 17.599     ;
; 0.385  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.362      ; 17.599     ;
; 0.386  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[8]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.057     ; 17.179     ;
; 0.397  ; cart_type_byte[2]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.398      ; 17.623     ;
; 0.397  ; cart_type_byte[2]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.398      ; 17.623     ;
; 0.397  ; cart_type_byte[2]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.398      ; 17.623     ;
; 0.397  ; cart_type_byte[2]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.398      ; 17.623     ;
; 0.397  ; cart_type_byte[2]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.398      ; 17.623     ;
; 0.418  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 17.114     ;
; 0.418  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 17.130     ;
; 0.429  ; DMA_16BIT_WRITE_ENABLE_IOCTL                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.362      ; 17.555     ;
; 0.429  ; DMA_16BIT_WRITE_ENABLE_IOCTL                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.362      ; 17.555     ;
; 0.429  ; DMA_16BIT_WRITE_ENABLE_IOCTL                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.362      ; 17.555     ;
; 0.429  ; DMA_16BIT_WRITE_ENABLE_IOCTL                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.362      ; 17.555     ;
; 0.429  ; DMA_16BIT_WRITE_ENABLE_IOCTL                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.362      ; 17.555     ;
+--------+------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                 ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.942 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.405        ; -2.032     ; 1.289      ;
; 0.957 ; SDRAM_DQ[3]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.428     ; 1.241      ;
; 0.957 ; SDRAM_DQ[2]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.428     ; 1.241      ;
; 0.959 ; SDRAM_DQ[1]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.436     ; 1.231      ;
; 0.961 ; SDRAM_DQ[14]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.424     ; 1.241      ;
; 0.961 ; SDRAM_DQ[15]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.424     ; 1.241      ;
; 0.963 ; SDRAM_DQ[0]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.432     ; 1.231      ;
; 0.973 ; SDRAM_DQ[13]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.422     ; 1.231      ;
; 0.973 ; SDRAM_DQ[12]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.422     ; 1.231      ;
; 0.974 ; SDRAM_DQ[11]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.421     ; 1.231      ;
; 0.974 ; SDRAM_DQ[10]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.421     ; 1.231      ;
; 0.976 ; SDRAM_DQ[8]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.429     ; 1.221      ;
; 0.976 ; SDRAM_DQ[9]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.429     ; 1.221      ;
; 1.006 ; SDRAM_DQ[5]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.369     ; 1.251      ;
; 1.015 ; SDRAM_DQ[7]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.370     ; 1.241      ;
; 1.016 ; SDRAM_DQ[4]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.369     ; 1.241      ;
; 1.016 ; SDRAM_DQ[6]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.369     ; 1.241      ;
; 1.087 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.138     ; 7.456      ;
; 1.100 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.138     ; 7.443      ;
; 1.258 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.139     ; 7.284      ;
; 1.325 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.138     ; 7.218      ;
; 1.388 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.136     ; 7.157      ;
; 1.482 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.138     ; 7.061      ;
; 1.510 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.092     ; 7.079      ;
; 1.510 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 7.029      ;
; 1.523 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.092     ; 7.066      ;
; 1.570 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 6.969      ;
; 1.636 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.139     ; 6.906      ;
; 1.681 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 6.907      ;
; 1.681 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.143     ; 6.857      ;
; 1.682 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.138     ; 6.861      ;
; 1.748 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.092     ; 6.841      ;
; 1.758 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.135     ; 6.788      ;
; 1.773 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 6.766      ;
; 1.778 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.136     ; 6.767      ;
; 1.825 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.092     ; 6.764      ;
; 1.838 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 6.699      ;
; 1.873 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.092     ; 6.716      ;
; 1.880 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 6.657      ;
; 1.881 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 6.656      ;
; 1.896 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 6.643      ;
; 1.898 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.135     ; 6.648      ;
; 1.905 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.092     ; 6.684      ;
; 1.907 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.145     ; 6.629      ;
; 1.920 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.145     ; 6.616      ;
; 1.939 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|udqm_reg                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.133     ; 6.609      ;
; 1.952 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|udqm_reg                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.134     ; 6.595      ;
; 1.969 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.139     ; 6.573      ;
; 1.988 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 6.547      ;
; 1.996 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 6.592      ;
; 2.030 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 6.505      ;
; 2.031 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 6.504      ;
; 2.049 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.143     ; 6.489      ;
; 2.052 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 6.492      ;
; 2.057 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.147     ; 6.477      ;
; 2.059 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 6.529      ;
; 2.063 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.092     ; 6.526      ;
; 2.068 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 6.469      ;
; 2.070 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.147     ; 6.464      ;
; 2.072 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.138     ; 6.471      ;
; 2.077 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.145     ; 6.459      ;
; 2.105 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]                           ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 6.373      ;
; 2.125 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|udqm_reg                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.133     ; 6.423      ;
; 2.162 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.138     ; 6.381      ;
; 2.192 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 6.352      ;
; 2.198 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.135     ; 6.348      ;
; 2.218 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 6.317      ;
; 2.220 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.092     ; 6.369      ;
; 2.227 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.147     ; 6.307      ;
; 2.241 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.095     ; 6.345      ;
; 2.245 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.073     ; 6.363      ;
; 2.258 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.135     ; 6.288      ;
; 2.269 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 6.268      ;
; 2.279 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.143     ; 6.259      ;
; 2.312 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 6.225      ;
; 2.317 ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[6]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.257     ; 6.107      ;
; 2.321 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.143     ; 6.217      ;
; 2.322 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.143     ; 6.216      ;
; 2.323 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 6.217      ;
; 2.348 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 6.192      ;
; 2.348 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 6.189      ;
; 2.361 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 6.176      ;
; 2.374 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 6.214      ;
; 2.379 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.143     ; 6.159      ;
; 2.383 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.091     ; 6.207      ;
; 2.392 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 6.196      ;
; 2.440 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.145     ; 6.096      ;
; 2.458 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 6.079      ;
; 2.492 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 6.052      ;
; 2.494 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 6.045      ;
; 2.494 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 6.046      ;
; 2.505 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|udqm_reg                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.134     ; 6.042      ;
; 2.507 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 6.030      ;
; 2.509 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.143     ; 6.029      ;
; 2.517 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|udqm_reg                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.133     ; 6.031      ;
; 2.518 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 6.019      ;
; 2.550 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]                           ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.255     ; 5.876      ;
; 2.552 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 5.992      ;
; 2.561 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 5.979      ;
; 2.574 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 5.965      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'SPI_SCK'                                                                                                                ;
+--------+--------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                      ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 13.788 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 7.086      ;
; 13.788 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 7.086      ;
; 13.788 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 7.086      ;
; 13.788 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 7.086      ;
; 13.788 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 7.086      ;
; 14.219 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 6.655      ;
; 14.219 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 6.655      ;
; 14.219 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 6.655      ;
; 14.219 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 6.655      ;
; 14.219 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 6.655      ;
; 14.275 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 6.599      ;
; 14.482 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 6.392      ;
; 14.482 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 6.392      ;
; 14.482 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 6.392      ;
; 14.482 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 6.392      ;
; 14.482 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 6.392      ;
; 14.582 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 6.292      ;
; 14.582 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 6.292      ;
; 14.582 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 6.292      ;
; 14.582 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 6.292      ;
; 14.582 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 6.292      ;
; 14.706 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 6.168      ;
; 14.969 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 5.905      ;
; 15.069 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 5.805      ;
; 16.158 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.716      ;
; 16.158 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.716      ;
; 16.158 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.716      ;
; 16.158 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.716      ;
; 16.158 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.716      ;
; 16.301 ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.561      ;
; 16.301 ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.561      ;
; 16.301 ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.561      ;
; 16.301 ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.561      ;
; 16.301 ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.561      ;
; 16.321 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.553      ;
; 16.321 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.553      ;
; 16.321 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.553      ;
; 16.321 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.553      ;
; 16.321 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.553      ;
; 16.350 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.524      ;
; 16.350 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.524      ;
; 16.350 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.524      ;
; 16.350 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.524      ;
; 16.350 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.524      ;
; 16.431 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.431      ;
; 16.431 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.431      ;
; 16.431 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.431      ;
; 16.431 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.431      ;
; 16.431 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.431      ;
; 16.478 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.384      ;
; 16.478 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.384      ;
; 16.478 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.384      ;
; 16.478 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.384      ;
; 16.478 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.384      ;
; 16.522 ; user_io:my_user_io|cmd[1]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.340      ;
; 16.522 ; user_io:my_user_io|cmd[1]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.340      ;
; 16.522 ; user_io:my_user_io|cmd[1]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.340      ;
; 16.522 ; user_io:my_user_io|cmd[1]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.340      ;
; 16.522 ; user_io:my_user_io|cmd[1]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.340      ;
; 16.526 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.348      ;
; 16.526 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.348      ;
; 16.526 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.348      ;
; 16.526 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.348      ;
; 16.526 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.348      ;
; 16.536 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.326      ;
; 16.536 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.326      ;
; 16.536 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.326      ;
; 16.536 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.326      ;
; 16.536 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.326      ;
; 16.585 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.289      ;
; 16.585 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.289      ;
; 16.585 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.289      ;
; 16.585 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.289      ;
; 16.585 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.289      ;
; 16.596 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.266      ;
; 16.596 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.266      ;
; 16.596 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.266      ;
; 16.596 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.266      ;
; 16.596 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.266      ;
; 16.645 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.229      ;
; 16.732 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.142      ;
; 16.732 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.142      ;
; 16.732 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.142      ;
; 16.732 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.142      ;
; 16.732 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.142      ;
; 16.757 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.105      ;
; 16.757 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.105      ;
; 16.757 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.105      ;
; 16.757 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.105      ;
; 16.757 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.105      ;
; 16.821 ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 4.041      ;
; 16.837 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.037      ;
; 16.841 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 4.033      ;
; 16.951 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 3.911      ;
; 16.998 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 3.864      ;
; 17.013 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 3.861      ;
; 17.042 ; user_io:my_user_io|cmd[1]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 3.820      ;
; 17.056 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 3.806      ;
; 17.072 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.007      ; 3.802      ;
; 17.116 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.005     ; 3.746      ;
+--------+--------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'clk_27'                                                                                                                                                                ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 33.983 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.976      ;
; 34.077 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.882      ;
; 34.099 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.860      ;
; 34.121 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.838      ;
; 34.125 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.834      ;
; 34.151 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.808      ;
; 34.166 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.793      ;
; 34.213 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.746      ;
; 34.247 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.712      ;
; 34.262 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.697      ;
; 34.269 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.690      ;
; 34.275 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.684      ;
; 34.293 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.666      ;
; 34.308 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.651      ;
; 34.356 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.603      ;
; 34.367 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.592      ;
; 34.389 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.570      ;
; 34.411 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.548      ;
; 34.458 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.501      ;
; 34.557 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.402      ;
; 34.840 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.119      ;
; 34.852 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.107      ;
; 34.861 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.098      ;
; 34.880 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.079      ;
; 34.886 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.073      ;
; 34.898 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.061      ;
; 34.942 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.017      ;
; 34.952 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.007      ;
; 34.955 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.004      ;
; 34.978 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.981      ;
; 34.985 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.974      ;
; 35.003 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.956      ;
; 35.027 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.932      ;
; 35.037 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.922      ;
; 35.040 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.919      ;
; 35.041 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.918      ;
; 35.048 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.911      ;
; 35.060 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.899      ;
; 35.073 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.886      ;
; 35.091 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.868      ;
; 35.105 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.854      ;
; 35.124 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.835      ;
; 35.126 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.833      ;
; 35.210 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.749      ;
; 35.221 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.738      ;
; 35.234 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.725      ;
; 35.235 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.724      ;
; 35.241 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.718      ;
; 35.256 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.703      ;
; 35.407 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.552      ;
; 35.410 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.549      ;
; 35.418 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.541      ;
; 35.427 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.532      ;
; 35.427 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.532      ;
; 35.590 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.369      ;
; 35.610 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.349      ;
; 35.681 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.278      ;
; 35.685 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.274      ;
; 35.721 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.238      ;
; 36.101 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 0.858      ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 36.629 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_we_reg ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.806     ; 6.623      ;
; 36.645 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.095      ; 9.118      ;
; 38.746 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.400     ; 4.912      ;
; 38.917 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.391     ; 4.750      ;
; 38.925 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.391     ; 4.742      ;
; 39.021 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.400     ; 4.637      ;
; 39.093 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.111      ; 6.686      ;
; 39.125 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.391     ; 4.542      ;
; 39.205 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.400     ; 4.453      ;
; 39.213 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.111      ; 6.566      ;
; 39.261 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.391     ; 4.406      ;
; 39.353 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.400     ; 4.305      ;
; 39.400 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.111      ; 6.379      ;
; 39.533 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.391     ; 4.134      ;
; 39.899 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.400     ; 3.759      ;
; 40.453 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate3_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.122     ; 1.092      ;
; 40.575 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.407     ; 3.076      ;
; 40.971 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                             ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.408     ; 2.679      ;
; 75.111 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.096     ; 8.127      ;
; 75.137 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.098     ; 8.099      ;
; 77.425 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 5.829      ;
; 77.493 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 5.759      ;
; 77.565 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 5.689      ;
; 77.633 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 5.619      ;
; 77.750 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 5.504      ;
; 77.813 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.334      ; 5.902      ;
; 77.818 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 5.434      ;
; 78.042 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.334      ; 5.673      ;
; 78.145 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                                                 ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.334      ; 5.570      ;
; 78.145 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                                                 ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.334      ; 5.570      ;
; 78.469 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 4.095      ; 8.960      ;
; 78.566 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 4.686      ;
; 78.588 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                                                ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.317      ; 5.110      ;
; 78.588 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                                                ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.317      ; 5.110      ;
; 78.808 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.064     ; 4.462      ;
; 78.919 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 4.337      ;
; 78.919 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 4.337      ;
; 78.919 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 4.337      ;
; 78.919 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 4.337      ;
; 78.919 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 4.337      ;
; 78.919 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 4.337      ;
; 78.919 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 4.337      ;
; 78.919 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 4.337      ;
; 78.934 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.331      ; 4.778      ;
; 78.934 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.331      ; 4.778      ;
; 78.944 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.064     ; 4.326      ;
; 78.944 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.064     ; 4.326      ;
; 78.944 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.064     ; 4.326      ;
; 78.944 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.064     ; 4.326      ;
; 78.944 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.064     ; 4.326      ;
; 78.944 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.064     ; 4.326      ;
; 78.944 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.064     ; 4.326      ;
; 78.944 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.064     ; 4.326      ;
; 78.950 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 4.299      ;
; 78.950 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 4.299      ;
; 78.950 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 4.299      ;
; 78.950 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 4.299      ;
; 78.950 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 4.299      ;
; 78.975 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.288      ;
; 78.975 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.288      ;
; 78.975 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.288      ;
; 78.975 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.288      ;
; 78.975 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.288      ;
; 79.049 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_last_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.320      ; 4.652      ;
; 79.088 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.064     ; 4.182      ;
; 79.089 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.098     ; 4.147      ;
; 79.089 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.098     ; 4.147      ;
; 79.089 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.098     ; 4.147      ;
; 79.089 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.098     ; 4.147      ;
; 79.089 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.098     ; 4.147      ;
; 79.089 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.098     ; 4.147      ;
; 79.089 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.098     ; 4.147      ;
; 79.089 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.098     ; 4.147      ;
; 79.094 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.064     ; 4.176      ;
; 79.104 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.064     ; 4.166      ;
; 79.124 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.097     ; 4.113      ;
; 79.136 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.064     ; 4.134      ;
; 79.152 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.097     ; 4.085      ;
; 79.188 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.064     ; 4.082      ;
; 79.198 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.320      ; 4.503      ;
; 79.198 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.320      ; 4.503      ;
; 79.253 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.064     ; 4.017      ;
; 79.266 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.064     ; 4.004      ;
; 79.266 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.064     ; 4.004      ;
; 79.276 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_datain_reg0  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.341      ; 4.446      ;
; 79.285 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.337      ; 4.433      ;
; 79.287 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 3.969      ;
; 79.293 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.337      ; 4.425      ;
; 79.297 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 3.966      ;
; 79.297 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 3.966      ;
; 79.297 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 3.966      ;
; 79.297 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 3.966      ;
; 79.297 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 3.966      ;
; 79.319 ; rom_loaded                                                                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 3.937      ;
; 79.327 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.063     ; 3.944      ;
; 79.365 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 3.889      ;
; 79.365 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 3.889      ;
; 79.365 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 3.889      ;
; 79.365 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 3.889      ;
; 79.365 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 3.889      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                ; To Node                                                                                                                                                                                                                                 ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.353 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[7]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.085      ;
; 0.353 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[1]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.085      ;
; 0.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[5]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.134      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[6]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.145      ;
; 0.413 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[0]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.149      ;
; 0.414 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[3]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.147      ;
; 0.415 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[3]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.151      ;
; 0.416 ; user_io:my_user_io|sd_dout[2]                                                                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.149      ;
; 0.416 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[0]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.149      ;
; 0.423 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1]                                                                                         ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.155      ;
; 0.425 ; zpu_secbuf_d[2]                                                                                                                                                                          ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.483      ; 1.162      ;
; 0.426 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[7]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.159      ;
; 0.427 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[1]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.160      ;
; 0.428 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[2]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.483      ; 1.165      ;
; 0.429 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[5]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.483      ; 1.166      ;
; 0.431 ; user_io:my_user_io|sd_buff_addr[1]                                                                                                                                                       ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.474      ; 1.159      ;
; 0.434 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_freezer_reg                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_freezer_reg                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[3]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[3]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 0.746      ;
; 0.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[2]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[2]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 0.746      ;
; 0.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[1]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[1]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 0.746      ;
; 0.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[0]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[0]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 0.746      ;
; 0.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[6]                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[6]                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 0.746      ;
; 0.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 0.746      ;
; 0.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 0.746      ;
; 0.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 0.746      ;
; 0.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 0.746      ;
; 0.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 0.746      ;
; 0.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 0.746      ;
; 0.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqa_reg[1]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqa_reg[1]                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 0.746      ;
; 0.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[4]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[4]                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 0.746      ;
; 0.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[3]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[3]                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 0.746      ;
; 0.438 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 0.746      ;
; 0.440 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[5]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.176      ;
; 0.440 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[2]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.176      ;
; 0.441 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe3a[0]    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~portb_address_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.477      ; 1.172      ;
; 0.442 ; user_io:my_user_io|sd_dout[3]                                                                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.175      ;
; 0.443 ; user_io:my_user_io|sd_buff_addr[0]                                                                                                                                                       ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.474      ; 1.171      ;
; 0.443 ; user_io:my_user_io|sd_buff_addr[2]                                                                                                                                                       ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.474      ; 1.171      ;
; 0.443 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[4]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.483      ; 1.180      ;
; 0.447 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2]                                                                                         ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.179      ;
; 0.449 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[7]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.489      ; 1.192      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[0]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[0]                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[0]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[0]                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[0]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[0]                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[0]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[0]                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[0]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[0]                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[0]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[0]                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[0]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[0]                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[0]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[0]                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[3]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[3]                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[3]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[3]                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_kbd_wptr[0]                                                                                                                                                       ; user_io:my_user_io|ps2_kbd_wptr[0]                                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_kbd_wptr[1]                                                                                                                                                       ; user_io:my_user_io|ps2_kbd_wptr[1]                                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_kbd_wptr[2]                                                                                                                                                       ; user_io:my_user_io|ps2_kbd_wptr[2]                                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[9]                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[9]                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[1]                                                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[1]                                                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[1]                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[1]                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ZPU_IN1[30]                                                                                                                                                                              ; ZPU_IN1[30]                                                                                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[6]                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[6]                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[7] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[7]                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[6] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[6]                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[5] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[5]                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[4] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[4]                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[3] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[3]                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[2] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[2]                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[1] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[1]                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[0]                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[89]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[89]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[11]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[11]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[10]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[10]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|low_addressa[2]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|low_addressa[2]                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[363]                                                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[363]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ZPU_IN1[31]                                                                                                                                                                              ; ZPU_IN1[31]                                                                                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|scl_ena                                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|scl_ena                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|ack_error                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|ack_error                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[7]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[7]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_valid_reg[7]                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_valid_reg[7]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[6]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[6]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[5]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[5]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; scandoubler:scandoubler1|buffer_select_reg                                                                                                                                               ; scandoubler:scandoubler1|buffer_select_reg                                                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[4]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[4]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_valid_reg[3]                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_valid_reg[3]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'SPI_SCK'                                                                                                                                                                                              ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                  ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.427 ; osd:osd_inst|sbuf[2]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.483      ; 1.164      ;
; 0.431 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.482      ; 1.167      ;
; 0.432 ; osd:osd_inst|sbuf[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.483      ; 1.169      ;
; 0.437 ; osd:osd_inst|sbuf[0]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.483      ; 1.174      ;
; 0.443 ; osd:osd_inst|bcnt[0]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.476      ; 1.173      ;
; 0.449 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.482      ; 1.185      ;
; 0.451 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.482      ; 1.187      ;
; 0.454 ; osd:osd_inst|osd_enable                    ; osd:osd_inst|osd_enable                                                                                 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|bit_cnt[1]              ; user_io:my_user_io|bit_cnt[1]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|bit_cnt[2]              ; user_io:my_user_io|bit_cnt[2]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|byte_cnt[0]             ; user_io:my_user_io|byte_cnt[0]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|cmd[3]                  ; user_io:my_user_io|cmd[3]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|cmd[0]                  ; user_io:my_user_io|cmd[0]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|cmd[1]                  ; user_io:my_user_io|cmd[1]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|cmd[2]                  ; user_io:my_user_io|cmd[2]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|serial_out_rptr[0]      ; user_io:my_user_io|serial_out_rptr[0]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.455 ; data_io:mist_data_io|bit_cnt[1]            ; data_io:mist_data_io|bit_cnt[1]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; data_io:mist_data_io|bit_cnt[2]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; user_io:my_user_io|cmd[6]                  ; user_io:my_user_io|cmd[6]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; user_io:my_user_io|cmd[7]                  ; user_io:my_user_io|cmd[7]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.746      ;
; 0.458 ; osd:osd_inst|sbuf[6]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.482      ; 1.194      ;
; 0.459 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.476      ; 1.189      ;
; 0.466 ; user_io:my_user_io|bit_cnt[0]              ; user_io:my_user_io|bit_cnt[0]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.758      ;
; 0.466 ; user_io:my_user_io|spi_receiver_strobe_r   ; user_io:my_user_io|spi_receiver_strobe_r                                                                ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.758      ;
; 0.467 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[0]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.758      ;
; 0.467 ; data_io:mist_data_io|spi_receiver_strobe_r ; data_io:mist_data_io|spi_receiver_strobe_r                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.758      ;
; 0.471 ; osd:osd_inst|bcnt[3]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.477      ; 1.202      ;
; 0.486 ; osd:osd_inst|bcnt[5]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.477      ; 1.217      ;
; 0.486 ; osd:osd_inst|bcnt[10]                      ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.476      ; 1.216      ;
; 0.494 ; osd:osd_inst|bcnt[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.476      ; 1.224      ;
; 0.494 ; user_io:my_user_io|serial_out_rptr[5]      ; user_io:my_user_io|serial_out_rptr[5]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.786      ;
; 0.497 ; osd:osd_inst|bcnt[8]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.477      ; 1.228      ;
; 0.501 ; osd:osd_inst|cnt[4]                        ; osd:osd_inst|cnt[4]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.793      ;
; 0.503 ; data_io:mist_data_io|sbuf[6]               ; data_io:mist_data_io|spi_byte_in[7]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.794      ;
; 0.510 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[1]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.801      ;
; 0.511 ; data_io:mist_data_io|sbuf[1]               ; data_io:mist_data_io|spi_byte_in[2]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.802      ;
; 0.512 ; data_io:mist_data_io|sbuf[0]               ; data_io:mist_data_io|sbuf[1]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.803      ;
; 0.512 ; data_io:mist_data_io|sbuf[2]               ; data_io:mist_data_io|sbuf[3]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.803      ;
; 0.512 ; data_io:mist_data_io|sbuf[4]               ; data_io:mist_data_io|sbuf[5]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.803      ;
; 0.512 ; data_io:mist_data_io|sbuf[4]               ; data_io:mist_data_io|spi_byte_in[5]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.803      ;
; 0.512 ; data_io:mist_data_io|sbuf[0]               ; data_io:mist_data_io|spi_byte_in[1]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.803      ;
; 0.513 ; data_io:mist_data_io|sbuf[1]               ; data_io:mist_data_io|sbuf[2]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.804      ;
; 0.513 ; data_io:mist_data_io|sbuf[3]               ; data_io:mist_data_io|sbuf[4]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.804      ;
; 0.513 ; data_io:mist_data_io|sbuf[3]               ; data_io:mist_data_io|spi_byte_in[4]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.804      ;
; 0.514 ; data_io:mist_data_io|sbuf[2]               ; data_io:mist_data_io|spi_byte_in[3]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.805      ;
; 0.514 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.805      ;
; 0.520 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|sbuf[6]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.811      ;
; 0.520 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|spi_byte_in[6]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.811      ;
; 0.520 ; user_io:my_user_io|sbuf[4]                 ; user_io:my_user_io|spi_byte_in[5]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.811      ;
; 0.521 ; user_io:my_user_io|sbuf[4]                 ; user_io:my_user_io|sbuf[5]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.812      ;
; 0.535 ; user_io:my_user_io|bit_cnt[1]              ; user_io:my_user_io|bit_cnt[2]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.827      ;
; 0.543 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|sbuf[4]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.835      ;
; 0.545 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|cmd[4]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.837      ;
; 0.660 ; osd:osd_inst|bcnt[3]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.476      ; 1.390      ;
; 0.708 ; data_io:mist_data_io|sbuf[5]               ; data_io:mist_data_io|spi_byte_in[6]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.999      ;
; 0.709 ; data_io:mist_data_io|sbuf[5]               ; data_io:mist_data_io|sbuf[6]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.000      ;
; 0.717 ; user_io:my_user_io|sbuf[3]                 ; user_io:my_user_io|spi_byte_in[4]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.008      ;
; 0.718 ; user_io:my_user_io|sbuf[3]                 ; user_io:my_user_io|sbuf[4]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.009      ;
; 0.724 ; user_io:my_user_io|sbuf[0]                 ; user_io:my_user_io|spi_byte_in[1]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.016      ;
; 0.726 ; user_io:my_user_io|sbuf[0]                 ; user_io:my_user_io|sbuf[1]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.018      ;
; 0.739 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|cmd[5]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.031      ;
; 0.740 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|sbuf[5]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.032      ;
; 0.740 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|sbuf[6]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.032      ;
; 0.740 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|cmd[6]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.032      ;
; 0.747 ; osd:osd_inst|bcnt[2]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.477      ; 1.478      ;
; 0.747 ; user_io:my_user_io|serial_out_rptr[2]      ; user_io:my_user_io|serial_out_rptr[2]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.039      ;
; 0.749 ; user_io:my_user_io|serial_out_rptr[3]      ; user_io:my_user_io|serial_out_rptr[3]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.041      ;
; 0.749 ; user_io:my_user_io|serial_out_rptr[4]      ; user_io:my_user_io|serial_out_rptr[4]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.041      ;
; 0.758 ; osd:osd_inst|cnt[1]                        ; osd:osd_inst|cnt[1]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.050      ;
; 0.758 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|cmd[6]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.049      ;
; 0.760 ; osd:osd_inst|cnt[2]                        ; osd:osd_inst|cnt[2]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.052      ;
; 0.762 ; data_io:mist_data_io|bit_cnt[1]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.053      ;
; 0.762 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|bcnt[1]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.054      ;
; 0.763 ; osd:osd_inst|bcnt[2]                       ; osd:osd_inst|bcnt[2]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.055      ;
; 0.763 ; osd:osd_inst|bcnt[3]                       ; osd:osd_inst|bcnt[3]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.055      ;
; 0.763 ; osd:osd_inst|bcnt[5]                       ; osd:osd_inst|bcnt[5]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.055      ;
; 0.763 ; user_io:my_user_io|byte_cnt[2]             ; user_io:my_user_io|byte_cnt[2]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.055      ;
; 0.763 ; user_io:my_user_io|sbuf[0]                 ; user_io:my_user_io|cmd[1]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.055      ;
; 0.763 ; user_io:my_user_io|sbuf[1]                 ; user_io:my_user_io|cmd[2]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.055      ;
; 0.764 ; osd:osd_inst|bcnt[4]                       ; osd:osd_inst|bcnt[4]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.056      ;
; 0.764 ; osd:osd_inst|bcnt[9]                       ; osd:osd_inst|bcnt[9]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.056      ;
; 0.764 ; osd:osd_inst|bcnt[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.477      ; 1.495      ;
; 0.764 ; user_io:my_user_io|sbuf[6]                 ; user_io:my_user_io|cmd[7]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.055      ;
; 0.765 ; osd:osd_inst|bcnt[7]                       ; osd:osd_inst|bcnt[7]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.057      ;
; 0.766 ; osd:osd_inst|bcnt[10]                      ; osd:osd_inst|bcnt[10]                                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.058      ;
; 0.767 ; osd:osd_inst|bcnt[6]                       ; osd:osd_inst|bcnt[6]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.059      ;
; 0.767 ; osd:osd_inst|bcnt[8]                       ; osd:osd_inst|bcnt[8]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.059      ;
; 0.767 ; osd:osd_inst|bcnt[6]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.476      ; 1.497      ;
; 0.768 ; user_io:my_user_io|serial_out_rptr[1]      ; user_io:my_user_io|serial_out_rptr[1]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.060      ;
; 0.770 ; user_io:my_user_io|serial_out_rptr[0]      ; user_io:my_user_io|serial_out_rptr[1]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.062      ;
; 0.771 ; user_io:my_user_io|byte_cnt[4]             ; user_io:my_user_io|byte_cnt[4]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.063      ;
; 0.773 ; user_io:my_user_io|byte_cnt[3]             ; user_io:my_user_io|byte_cnt[3]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.065      ;
; 0.773 ; user_io:my_user_io|byte_cnt[6]             ; user_io:my_user_io|byte_cnt[6]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.065      ;
; 0.773 ; user_io:my_user_io|byte_cnt[8]             ; user_io:my_user_io|byte_cnt[8]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.065      ;
; 0.774 ; osd:osd_inst|cnt[3]                        ; osd:osd_inst|cnt[3]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.066      ;
; 0.774 ; user_io:my_user_io|sbuf[2]                 ; user_io:my_user_io|cmd[3]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.066      ;
; 0.775 ; osd:osd_inst|cnt[0]                        ; osd:osd_inst|cnt[0]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.067      ;
; 0.775 ; user_io:my_user_io|byte_cnt[5]             ; user_io:my_user_io|byte_cnt[5]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.067      ;
; 0.782 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.477      ; 1.513      ;
; 0.787 ; osd:osd_inst|bcnt[0]                       ; osd:osd_inst|bcnt[0]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.079      ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                     ; To Node                                                                                                                                                                                                       ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.455 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; rom_loaded                                                                                                                                                                                                    ; rom_loaded                                                                                                                                                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.466 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.758      ;
; 0.492 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.784      ;
; 0.493 ; rom_loaded                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.784      ;
; 0.495 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.786      ;
; 0.510 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.802      ;
; 0.511 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.802      ;
; 0.512 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.803      ;
; 0.519 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.810      ;
; 0.548 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.839      ;
; 0.554 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.845      ;
; 0.559 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.850      ;
; 0.562 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.853      ;
; 0.562 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.853      ;
; 0.620 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                              ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.475      ; 1.349      ;
; 0.654 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.945      ;
; 0.654 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.945      ;
; 0.656 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|tmp_seq_ena_state                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.947      ;
; 0.668 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.959      ;
; 0.668 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_counter_state                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.959      ;
; 0.698 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[2]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[2]                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.990      ;
; 0.699 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[1]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[1]                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.991      ;
; 0.700 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[7]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[7]                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.992      ;
; 0.700 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[6]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[6]                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.992      ;
; 0.700 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[3]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[3]                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.992      ;
; 0.700 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[0]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[0]                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.992      ;
; 0.701 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                          ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.992      ;
; 0.723 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.015      ;
; 0.736 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.028      ;
; 0.736 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.028      ;
; 0.736 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.028      ;
; 0.738 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.029      ;
; 0.739 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.739 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.030      ;
; 0.739 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.030      ;
; 0.740 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.741 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.033      ;
; 0.741 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.741 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.742 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.033      ;
; 0.742 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.033      ;
; 0.746 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.747 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.039      ;
; 0.747 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.039      ;
; 0.748 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.039      ;
; 0.748 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.040      ;
; 0.748 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.040      ;
; 0.748 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.040      ;
; 0.749 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.749 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.041      ;
; 0.749 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.041      ;
; 0.749 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.041      ;
; 0.749 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.750 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.041      ;
; 0.751 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.043      ;
; 0.751 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.042      ;
; 0.752 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.043      ;
; 0.762 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.054      ;
; 0.762 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.054      ;
; 0.762 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.054      ;
; 0.763 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.055      ;
; 0.763 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.054      ;
; 0.763 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.054      ;
; 0.764 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.056      ;
; 0.764 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.055      ;
; 0.764 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.055      ;
; 0.765 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.057      ;
; 0.765 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.056      ;
; 0.766 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.057      ;
; 0.766 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.058      ;
; 0.766 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.058      ;
; 0.766 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.057      ;
; 0.767 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.058      ;
; 0.768 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.060      ;
; 0.771 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.062      ;
; 0.772 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.063      ;
; 0.772 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.064      ;
; 0.774 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.065      ;
; 0.775 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.066      ;
; 0.775 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.066      ;
; 0.777 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.068      ;
; 0.781 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.072      ;
; 0.784 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.075      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'clk_27'                                                                                                                                                                ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 0.746      ;
; 0.749 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.040      ;
; 0.749 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.040      ;
; 0.751 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.042      ;
; 0.939 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.230      ;
; 0.950 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.241      ;
; 0.950 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.241      ;
; 0.957 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.248      ;
; 0.957 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.248      ;
; 0.958 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.249      ;
; 1.082 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.373      ;
; 1.091 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.382      ;
; 1.093 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.384      ;
; 1.093 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.384      ;
; 1.098 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.389      ;
; 1.098 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.389      ;
; 1.100 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.391      ;
; 1.100 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.391      ;
; 1.101 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.392      ;
; 1.103 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.394      ;
; 1.110 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.401      ;
; 1.111 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.402      ;
; 1.119 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.410      ;
; 1.233 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.524      ;
; 1.235 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.526      ;
; 1.239 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.530      ;
; 1.242 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.533      ;
; 1.242 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.533      ;
; 1.242 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.533      ;
; 1.244 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.535      ;
; 1.245 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.536      ;
; 1.251 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.542      ;
; 1.259 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.550      ;
; 1.260 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.551      ;
; 1.262 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.553      ;
; 1.270 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.561      ;
; 1.270 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.561      ;
; 1.273 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.564      ;
; 1.273 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.564      ;
; 1.277 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.568      ;
; 1.277 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.568      ;
; 1.278 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.569      ;
; 1.280 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.571      ;
; 1.280 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.571      ;
; 1.281 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.572      ;
; 1.287 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.578      ;
; 1.383 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.674      ;
; 1.388 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.679      ;
; 1.389 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.680      ;
; 1.412 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.703      ;
; 1.415 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.706      ;
; 1.419 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.710      ;
; 1.419 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.710      ;
; 1.422 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.713      ;
; 1.422 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.713      ;
; 1.560 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.851      ;
; 1.563 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.854      ;
; 1.565 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.856      ;
; 1.566 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.857      ;
; 1.568 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.859      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                            ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                     ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.455 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.467 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.758      ;
; 0.510 ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.801      ;
; 0.510 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.801      ;
; 0.740 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.740 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.740 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.741 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.741 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.743 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.034      ;
; 0.743 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.034      ;
; 0.747 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.038      ;
; 0.748 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.039      ;
; 0.749 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.749 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.750 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.041      ;
; 0.750 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.041      ;
; 0.751 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.042      ;
; 0.752 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.043      ;
; 0.755 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.046      ;
; 0.756 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.047      ;
; 0.758 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.049      ;
; 0.758 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.049      ;
; 0.758 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.049      ;
; 0.758 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.049      ;
; 0.760 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.051      ;
; 0.765 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.056      ;
; 0.765 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.056      ;
; 0.765 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.056      ;
; 0.765 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.056      ;
; 0.767 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.058      ;
; 0.772 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.063      ;
; 0.772 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.063      ;
; 0.772 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.063      ;
; 0.781 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.072      ;
; 0.797 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.088      ;
; 0.797 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.088      ;
; 0.829 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.120      ;
; 0.895 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.186      ;
; 0.941 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.232      ;
; 0.941 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.232      ;
; 1.094 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.385      ;
; 1.095 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.386      ;
; 1.095 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.386      ;
; 1.101 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.392      ;
; 1.101 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.392      ;
; 1.102 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.393      ;
; 1.102 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.393      ;
; 1.103 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.394      ;
; 1.104 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.395      ;
; 1.104 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.395      ;
; 1.104 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.395      ;
; 1.109 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.400      ;
; 1.109 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.400      ;
; 1.110 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.401      ;
; 1.110 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.401      ;
; 1.110 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.401      ;
; 1.110 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.401      ;
; 1.111 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.402      ;
; 1.112 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.403      ;
; 1.112 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.403      ;
; 1.113 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.404      ;
; 1.113 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.404      ;
; 1.113 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.404      ;
; 1.118 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.409      ;
; 1.118 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.409      ;
; 1.119 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.410      ;
; 1.119 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.410      ;
; 1.119 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.410      ;
; 1.119 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.410      ;
; 1.119 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.410      ;
; 1.121 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.412      ;
; 1.121 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.412      ;
; 1.122 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.413      ;
; 1.126 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.417      ;
; 1.126 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.417      ;
; 1.126 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.417      ;
; 1.127 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.418      ;
; 1.127 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.418      ;
; 1.128 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.419      ;
; 1.128 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.419      ;
; 1.128 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.419      ;
; 1.130 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.421      ;
; 1.133 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.424      ;
; 1.135 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.426      ;
; 1.137 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.428      ;
; 1.158 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.449      ;
; 1.158 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.449      ;
; 1.167 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.458      ;
; 1.167 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.458      ;
; 1.167 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.458      ;
; 1.176 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.467      ;
; 1.213 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 1.499      ;
; 1.214 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 1.500      ;
; 1.216 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 1.502      ;
; 1.225 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.516      ;
; 1.226 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.517      ;
; 1.226 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.517      ;
; 1.233 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.524      ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 2.208 ; sdram_statemachine:sdram_adaptor|cke_reg                                    ; SDRAM_CKE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.231      ; 2.902      ;
; 2.583 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8                 ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.318      ; 3.364      ;
; 2.583 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9                 ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.318      ; 3.364      ;
; 2.586 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1                 ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.325      ; 3.374      ;
; 2.590 ; sdram_statemachine:sdram_adaptor|dq_output_reg                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.321      ; 3.374      ;
; 2.600 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.311      ; 3.374      ;
; 2.600 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.311      ; 3.374      ;
; 2.601 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.310      ; 3.374      ;
; 2.601 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.310      ; 3.374      ;
; 2.604 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2                 ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.317      ; 3.384      ;
; 2.604 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3                 ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.317      ; 3.384      ;
; 2.608 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.313      ; 3.384      ;
; 2.608 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.313      ; 3.384      ;
; 2.617 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7                 ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.259      ; 3.339      ;
; 2.618 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4                 ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.258      ; 3.339      ;
; 2.618 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6                 ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.258      ; 3.339      ;
; 2.628 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5                 ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.258      ; 3.349      ;
; 2.893 ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                  ; SDRAM_BA[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.245      ; 3.601      ;
; 2.901 ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                             ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.295      ; 3.659      ;
; 2.902 ; sdram_statemachine:sdram_adaptor|ras_n_reg                                  ; SDRAM_nRAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.246      ; 3.611      ;
; 2.903 ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                ; SDRAM_A[0]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.245      ; 3.611      ;
; 2.903 ; sdram_statemachine:sdram_adaptor|addr_reg[10]                               ; SDRAM_A[10]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.245      ; 3.611      ;
; 2.903 ; sdram_statemachine:sdram_adaptor|ba_reg[0]                                  ; SDRAM_BA[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.245      ; 3.611      ;
; 2.903 ; sdram_statemachine:sdram_adaptor|cas_n_reg                                  ; SDRAM_nCAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.245      ; 3.611      ;
; 2.905 ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                ; SDRAM_A[1]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.243      ; 3.611      ;
; 2.905 ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                ; SDRAM_A[2]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.243      ; 3.611      ;
; 2.905 ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                              ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.301      ; 3.669      ;
; 2.905 ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                              ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.301      ; 3.669      ;
; 2.909 ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                             ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.297      ; 3.669      ;
; 2.915 ; sdram_statemachine:sdram_adaptor|we_n_reg                                   ; SDRAM_nWE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.243      ; 3.621      ;
; 2.915 ; sdram_statemachine:sdram_adaptor|ldqm_reg                                   ; SDRAM_DQML                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.243      ; 3.621      ;
; 2.915 ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                              ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.243      ; 3.621      ;
; 2.916 ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                ; SDRAM_A[3]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.242      ; 3.621      ;
; 2.916 ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                              ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.242      ; 3.621      ;
; 2.916 ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                              ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.242      ; 3.621      ;
; 2.920 ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                ; SDRAM_A[4]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.286      ; 3.669      ;
; 2.926 ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                              ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.242      ; 3.631      ;
; 3.029 ; sdram_statemachine:sdram_adaptor|udqm_reg                                   ; SDRAM_DQMH                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.303      ; 3.795      ;
; 3.030 ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                              ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.302      ; 3.795      ;
; 3.030 ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                              ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.302      ; 3.795      ;
; 3.033 ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                              ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.309      ; 3.805      ;
; 3.037 ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.305      ; 3.805      ;
; 3.047 ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                             ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.295      ; 3.805      ;
; 3.048 ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                             ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.294      ; 3.805      ;
; 3.048 ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                             ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.294      ; 3.805      ;
; 3.049 ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                ; SDRAM_A[6]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.293      ; 3.805      ;
; 3.050 ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                ; SDRAM_A[9]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.292      ; 3.805      ;
; 3.053 ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                ; SDRAM_A[7]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.289      ; 3.805      ;
; 3.053 ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                ; SDRAM_A[8]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.289      ; 3.805      ;
; 3.055 ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                             ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.297      ; 3.815      ;
; 3.057 ; sdram_statemachine:sdram_adaptor|addr_reg[11]                               ; SDRAM_A[11]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.295      ; 3.815      ;
; 3.064 ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                ; SDRAM_A[5]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.288      ; 3.815      ;
; 9.470 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -6.853       ; -1.747     ; 1.081      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                      ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 2.219 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.330     ; 6.120      ;
; 2.219 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.330     ; 6.120      ;
; 2.219 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.331     ; 6.119      ;
; 2.219 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.330     ; 6.120      ;
; 2.221 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.393     ; 6.055      ;
; 2.221 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.390     ; 6.058      ;
; 2.221 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.390     ; 6.058      ;
; 2.229 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.382     ; 6.058      ;
; 2.229 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.389     ; 6.051      ;
; 2.229 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.382     ; 6.058      ;
; 2.229 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.389     ; 6.051      ;
; 2.232 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.254     ; 6.195      ;
; 2.234 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.397     ; 6.038      ;
; 2.241 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.385     ; 6.043      ;
; 2.241 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.383     ; 6.045      ;
; 2.241 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.383     ; 6.045      ;
; 2.241 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.385     ; 6.043      ;
; 2.244 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.249     ; 6.188      ;
; 2.244 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.253     ; 6.184      ;
; 2.244 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.256     ; 6.181      ;
; 2.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.250     ; 6.180      ;
; 2.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.250     ; 6.180      ;
; 2.252 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 6.226      ;
; 2.252 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 6.226      ;
; 2.252 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 6.226      ;
; 2.252 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.204     ; 6.225      ;
; 2.252 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.206     ; 6.223      ;
; 2.252 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.206     ; 6.223      ;
; 2.252 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.207     ; 6.222      ;
; 2.252 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.206     ; 6.223      ;
; 2.252 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.204     ; 6.225      ;
; 2.252 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.204     ; 6.225      ;
; 2.252 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.206     ; 6.223      ;
; 2.252 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.204     ; 6.225      ;
; 2.252 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.204     ; 6.225      ;
; 2.252 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 6.226      ;
; 2.252 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.206     ; 6.223      ;
; 2.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.266     ; 6.161      ;
; 2.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.263     ; 6.164      ;
; 2.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.263     ; 6.164      ;
; 2.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.262     ; 6.157      ;
; 2.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.262     ; 6.157      ;
; 2.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.255     ; 6.164      ;
; 2.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.255     ; 6.164      ;
; 2.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.247     ; 6.172      ;
; 2.266 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|udqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.264     ; 6.151      ;
; 2.267 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.270     ; 6.144      ;
; 2.274 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.256     ; 6.151      ;
; 2.274 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.256     ; 6.151      ;
; 2.274 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.258     ; 6.149      ;
; 2.274 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.258     ; 6.149      ;
; 2.454 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.219     ; 5.972      ;
; 2.454 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.219     ; 5.972      ;
; 2.454 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.219     ; 5.972      ;
; 2.454 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.220     ; 5.971      ;
; 2.456 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.282     ; 5.907      ;
; 2.456 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.279     ; 5.910      ;
; 2.456 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.279     ; 5.910      ;
; 2.464 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.278     ; 5.903      ;
; 2.464 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.278     ; 5.903      ;
; 2.464 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.271     ; 5.910      ;
; 2.464 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.271     ; 5.910      ;
; 2.469 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.286     ; 5.890      ;
; 2.476 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.272     ; 5.897      ;
; 2.476 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.272     ; 5.897      ;
; 2.476 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.274     ; 5.895      ;
; 2.476 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.274     ; 5.895      ;
; 2.780 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.816      ;
; 2.780 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.816      ;
; 2.780 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.816      ;
; 2.780 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.816      ;
; 2.780 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.816      ;
; 2.780 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.816      ;
; 2.780 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.816      ;
; 2.780 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.816      ;
; 2.780 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.816      ;
; 2.780 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.816      ;
; 2.780 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.816      ;
; 2.780 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.816      ;
; 2.780 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.816      ;
; 2.780 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.816      ;
; 2.780 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.816      ;
; 2.780 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.816      ;
; 2.781 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.815      ;
; 2.781 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.211     ; 5.819      ;
; 2.781 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.211     ; 5.819      ;
; 2.781 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.815      ;
; 2.781 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.211     ; 5.819      ;
; 2.781 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.815      ;
; 2.781 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.815      ;
; 2.781 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.211     ; 5.819      ;
; 2.781 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.815      ;
; 2.781 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.211     ; 5.819      ;
; 2.781 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.211     ; 5.819      ;
; 2.781 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.815      ;
; 2.781 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.207     ; 5.823      ;
; 2.781 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.207     ; 5.823      ;
; 2.781 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.207     ; 5.823      ;
; 2.781 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.207     ; 5.823      ;
; 2.781 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.207     ; 5.823      ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                         ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 8.628 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.210     ; 8.784      ;
; 8.628 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.210     ; 8.784      ;
; 8.628 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.210     ; 8.784      ;
; 8.628 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[31]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.210     ; 8.784      ;
; 8.628 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.210     ; 8.784      ;
; 8.628 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[20]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.210     ; 8.784      ;
; 8.628 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.210     ; 8.784      ;
; 8.633 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.195     ; 8.794      ;
; 8.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.182     ; 8.798      ;
; 8.643 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.205     ; 8.774      ;
; 8.643 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[28]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.205     ; 8.774      ;
; 8.643 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[24]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.205     ; 8.774      ;
; 8.643 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.205     ; 8.774      ;
; 8.643 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[21]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.205     ; 8.774      ;
; 8.645 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[22]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.201     ; 8.776      ;
; 8.645 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[17]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.201     ; 8.776      ;
; 8.645 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.201     ; 8.776      ;
; 8.645 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.201     ; 8.776      ;
; 8.688 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.181     ; 8.753      ;
; 8.688 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|memory_ready_reg                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.194     ; 8.740      ;
; 9.061 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.232      ; 8.793      ;
; 9.061 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.232      ; 8.793      ;
; 9.061 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.232      ; 8.793      ;
; 9.061 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.232      ; 8.793      ;
; 9.105 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[7]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.196     ; 8.321      ;
; 9.105 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[6]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.196     ; 8.321      ;
; 9.105 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[4]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.196     ; 8.321      ;
; 9.105 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[5]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.196     ; 8.321      ;
; 9.105 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[3]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.196     ; 8.321      ;
; 9.105 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[2]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.196     ; 8.321      ;
; 9.105 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[1]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.196     ; 8.321      ;
; 9.105 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[14] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.207     ; 8.310      ;
; 9.105 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.207     ; 8.310      ;
; 9.105 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[0]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.196     ; 8.321      ;
; 9.105 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.207     ; 8.310      ;
; 9.106 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|stretch                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.195     ; 8.321      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[1]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 8.321      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[2]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 8.321      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.mstr_ack         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 8.322      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.slv_ack2         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 8.321      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.stop             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 8.322      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 8.322      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.start            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 8.322      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 8.322      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|sda_int                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 8.322      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.wr               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 8.322      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.rd               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 8.322      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[0]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 8.321      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.slv_ack1         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 8.321      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[14]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.195     ; 8.310      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[0]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 8.316      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[1]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 8.316      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[2]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 8.316      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[3]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 8.316      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[4]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 8.316      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[5]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 8.316      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[6]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 8.316      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[7]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 8.316      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[8]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 8.316      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_busy_reg                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 8.316      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[2]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 8.321      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[3]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 8.321      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[1]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 8.321      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[4]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 8.321      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[6]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 8.321      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[7]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 8.321      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[5]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 8.321      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_reg                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 8.316      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[11]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 8.320      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[9]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 8.316      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[10]                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 8.316      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[8]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 8.320      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[11]                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 8.316      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[12]                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 8.316      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[13]                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 8.316      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[14]                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 8.316      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[15]                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 8.316      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[30]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.190     ; 8.315      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[10]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.319      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[11]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.319      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[14]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.319      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[12]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.319      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[15]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.319      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[13]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.319      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[15]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 8.320      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[14]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.319      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[13]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.319      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[12]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 8.320      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[9]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 8.320      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[6]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.319      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[7]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.319      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[5]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.319      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[4]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.319      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[3]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.319      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[2]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.319      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[0]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.319      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.319      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[10]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 8.320      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|stretch                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 8.321      ;
; 9.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[0]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 8.321      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.590 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|dffe4                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.430      ; 2.231      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a63 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a62 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a61 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a60 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a59 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a58 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a57 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a56 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a35 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a34 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a33 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a32 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a31 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a29 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a28 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a27 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a26 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a25 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a24 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.256      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a55 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a54 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a53 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a52 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a51 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a50 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a49 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a48 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a47 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a46 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a45 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a44 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a43 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a42 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a41 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a40 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a39 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a38 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a37 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a36 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a23 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a22 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a21 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a20 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a19 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a18 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a17 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 1.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.532      ;
; 4.406 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[0]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.716      ; 5.334      ;
; 4.591 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.637      ; 5.440      ;
; 4.591 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.637      ; 5.440      ;
; 4.621 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[2]                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.612      ; 5.445      ;
; 4.634 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.592      ; 5.438      ;
; 4.634 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[7]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.592      ; 5.438      ;
; 4.634 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[0]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.592      ; 5.438      ;
; 4.634 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[3]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.592      ; 5.438      ;
; 4.634 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[2]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.592      ; 5.438      ;
; 4.634 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[1]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.592      ; 5.438      ;
; 4.643 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_dma_clock_del:antic_dma_clock1|dma_shiftreg_reg[7]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.587      ; 5.442      ;
; 4.644 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[0]                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.580      ; 5.436      ;
; 4.644 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[3]                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.580      ; 5.436      ;
; 4.650 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.574      ; 5.436      ;
; 4.655 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.583      ; 5.450      ;
; 4.655 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.583      ; 5.450      ;
; 4.655 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.583      ; 5.450      ;
; 4.655 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.583      ; 5.450      ;
; 4.655 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.583      ; 5.450      ;
; 4.656 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.582      ; 5.450      ;
; 4.656 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_freezer_reg                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.582      ; 5.450      ;
; 4.656 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.582      ; 5.450      ;
; 4.656 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.582      ; 5.450      ;
; 4.656 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[2]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.582      ; 5.450      ;
; 4.656 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.582      ; 5.450      ;
; 4.656 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.582      ; 5.450      ;
; 4.656 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[7]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.582      ; 5.450      ;
; 4.656 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[1]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.583      ; 5.451      ;
; 4.656 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.583      ; 5.451      ;
; 4.656 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[2]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.583      ; 5.451      ;
; 4.658 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[1]                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.579      ; 5.449      ;
; 4.658 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[3]                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.571      ; 5.441      ;
; 4.658 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.571      ; 5.441      ;
; 4.659 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[3]                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.574      ; 5.445      ;
; 4.659 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[2]                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.574      ; 5.445      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                  ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 4.901 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 5.308      ;
; 4.901 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 5.312      ;
; 4.901 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 5.312      ;
; 4.901 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 5.312      ;
; 4.901 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 5.312      ;
; 4.901 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 5.312      ;
; 4.901 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 5.312      ;
; 4.901 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 5.312      ;
; 4.901 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 5.312      ;
; 4.901 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 5.312      ;
; 4.901 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 5.312      ;
; 4.901 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 5.312      ;
; 4.901 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cke_reg                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 5.325      ;
; 4.902 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 5.309      ;
; 4.902 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 5.309      ;
; 4.902 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 5.309      ;
; 4.906 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 5.300      ;
; 4.906 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 5.300      ;
; 4.906 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 5.300      ;
; 4.907 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 5.303      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 5.323      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 5.323      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 5.323      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 5.323      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 5.323      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 5.323      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 5.323      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 5.323      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 5.323      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 5.323      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 5.323      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 5.323      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 5.323      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 5.323      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 5.318      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 5.318      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 5.318      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 5.318      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 5.318      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 5.318      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 5.318      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 5.318      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 5.318      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 5.318      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 5.318      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 5.318      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 5.318      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 5.318      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 5.318      ;
; 4.917 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 5.318      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 5.318      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 5.322      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 5.322      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 5.318      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 5.322      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 5.318      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 5.318      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 5.322      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 5.318      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 5.322      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 5.322      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 5.318      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 5.327      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 5.327      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 5.327      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 5.327      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 5.327      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 5.327      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 5.327      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 5.327      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 5.327      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 5.327      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 5.327      ;
; 4.918 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 5.327      ;
; 5.110 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 5.444      ;
; 5.110 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 5.444      ;
; 5.110 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 5.444      ;
; 5.110 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 5.443      ;
; 5.135 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.115      ; 5.413      ;
; 5.135 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.115      ; 5.413      ;
; 5.135 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.114      ; 5.412      ;
; 5.135 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.114      ; 5.412      ;
; 5.143 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.101      ; 5.407      ;
; 5.152 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.116      ; 5.431      ;
; 5.152 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.116      ; 5.431      ;
; 5.153 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.110      ; 5.426      ;
; 5.153 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.110      ; 5.426      ;
; 5.159 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.109      ; 5.431      ;
; 5.159 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.109      ; 5.431      ;
; 5.160 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.105      ; 5.428      ;
; 5.467 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.187      ; 5.799      ;
; 5.467 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.187      ; 5.799      ;
; 5.467 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.187      ; 5.799      ;
; 5.467 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.186      ; 5.798      ;
; 5.467 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.184      ; 5.796      ;
; 5.467 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.184      ; 5.796      ;
; 5.467 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 5.795      ;
; 5.467 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.184      ; 5.796      ;
; 5.467 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.186      ; 5.798      ;
; 5.467 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.186      ; 5.798      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                            ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cke_reg                      ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|reply_reg                    ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ;
; 4.204 ; 4.362        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                 ;
; 4.204 ; 4.362        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]                ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]                ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                 ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                 ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                 ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                 ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[11]                 ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[7]                  ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[8]                  ;
; 4.206 ; 4.364        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                 ;
; 4.206 ; 4.364        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                 ;
; 4.206 ; 4.364        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                 ;
; 4.206 ; 4.364        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ;
; 4.206 ; 4.364        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 4.193 ; 4.193        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.193 ; 4.193        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|o                                                                                                                    ;
; 4.224 ; 4.368        ; 0.144          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.312 ; 4.312        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|i                                                                                                                    ;
; 4.316 ; 4.440        ; 0.124          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.329 ; 8.810        ; 4.481          ; Port Rate        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.368 ; 4.368        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.368 ; 4.368        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 4.440 ; 4.440        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.440 ; 4.440        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 4.493 ; 4.493        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|i                                                                                                                    ;
; 4.612 ; 4.612        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.612 ; 4.612        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|o                                                                                                                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.378 ; 8.779        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0] ;
; 8.378 ; 8.779        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1] ;
; 8.378 ; 8.779        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2] ;
; 8.378 ; 8.779        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3] ;
; 8.378 ; 8.779        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4] ;
; 8.378 ; 8.779        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]      ;
; 8.378 ; 8.779        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]      ;
; 8.378 ; 8.779        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]      ;
; 8.378 ; 8.779        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]      ;
; 8.378 ; 8.779        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]      ;
; 8.378 ; 8.779        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]      ;
; 8.378 ; 8.779        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]      ;
; 8.378 ; 8.779        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]      ;
; 8.378 ; 8.779        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]      ;
; 8.378 ; 8.779        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]      ;
; 8.378 ; 8.779        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]      ;
; 8.378 ; 8.779        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]       ;
; 8.378 ; 8.779        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]       ;
; 8.378 ; 8.779        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]       ;
; 8.378 ; 8.779        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]       ;
; 8.378 ; 8.779        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]       ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0] ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1] ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2] ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3] ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4] ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]       ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]       ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]       ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]       ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]       ;
; 8.474 ; 8.694        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|addr_r[4]                                                                                           ;
; 8.475 ; 8.695        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[4]                                                           ;
; 8.475 ; 8.695        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                                           ;
; 8.475 ; 8.695        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[12]                                                                                     ;
; 8.475 ; 8.695        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[16]                                                                                     ;
; 8.476 ; 8.696        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[14]                                                                                                      ;
; 8.476 ; 8.696        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[18]                                                                                                      ;
; 8.476 ; 8.696        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[7]                                                                                                       ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_load                                                                                       ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                        ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                                                                                        ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                                                                                        ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                                                                                        ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                                                                                        ;
; 8.478 ; 8.698        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|pmbase_reg[4]                                                        ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[0]                                          ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[1]                                          ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_32BIT_WRITE_ENABLE_reg                                                                                              ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg                                                                                               ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                                                                                                            ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                                                                          ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                                                          ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[2]                                          ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[1]                                          ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[2]                                          ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colbk_snap_reg[1]                                                      ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colbk_snap_reg[2]                                                      ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colbk_snap_reg[3]                                                      ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf1_snap_reg[1]                                                     ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf1_snap_reg[3]                                                     ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf3_snap_reg[2]                                                     ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf3_snap_reg[3]                                                     ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|addr_r[12]                                                                                          ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|addr_r[14]                                                                                          ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|addr_r[3]                                                                                           ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                          ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                                  ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg                                         ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                                           ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                               ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                                                   ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                                                  ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                                  ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                                  ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                                  ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                                  ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[6]                                                     ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                                          ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[4]                                          ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[7]                                          ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf1_snap_reg[6]                                                     ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf1_snap_reg[7]                                                     ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf3_snap_reg[7]                                                     ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                                                           ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                           ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:prior_longer_delay|shift_reg[0][0]                     ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:prior_longer_delay|shift_reg[0][1]                     ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_control_reg[2]                                                     ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                          ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                ; Clock Edge ; Target                                                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; 16.275 ; 16.275       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.279 ; 16.279       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.279 ; 16.279       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.298 ; 16.298       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.298 ; 16.298       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.298 ; 16.298       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.298 ; 16.298       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.351 ; 16.351       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.351 ; 16.351       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.355 ; 16.355       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'clk_27'                                                                                                              ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target                                                                         ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+
; 18.278 ; 18.466       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.278 ; 18.466       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.278 ; 18.466       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.278 ; 18.466       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.278 ; 18.466       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.278 ; 18.466       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.278 ; 18.466       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.278 ; 18.466       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.278 ; 18.466       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.349 ; 18.569       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.349 ; 18.569       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.349 ; 18.569       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.349 ; 18.569       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.349 ; 18.569       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.349 ; 18.569       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.349 ; 18.569       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.349 ; 18.569       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.349 ; 18.569       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.362 ; 18.362       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.362 ; 18.362       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 18.366 ; 18.366       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.366 ; 18.366       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.400 ; 18.400       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.410 ; 18.410       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.410 ; 18.410       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.418 ; 18.418       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.418 ; 18.418       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.418 ; 18.418       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.418 ; 18.418       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.418 ; 18.418       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.418 ; 18.418       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.418 ; 18.418       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.418 ; 18.418       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.418 ; 18.418       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.434 ; 18.434       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.438 ; 18.438       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.598 ; 18.598       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.602 ; 18.602       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.618 ; 18.618       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.618 ; 18.618       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.618 ; 18.618       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.618 ; 18.618       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.618 ; 18.618       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.618 ; 18.618       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.618 ; 18.618       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.618 ; 18.618       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.618 ; 18.618       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.626 ; 18.626       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.626 ; 18.626       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.637 ; 18.637       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.668 ; 18.668       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.668 ; 18.668       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.672 ; 18.672       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.672 ; 18.672       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 33.037 ; 37.037       ; 4.000          ; Port Rate        ; clk_27 ; Rise       ; CLOCK_27[0]                                                                    ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'SPI_SCK'                                                                                                                                       ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                                                                                  ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+
; 20.416 ; 20.651       ; 0.235          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ;
; 20.416 ; 20.651       ; 0.235          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_we_reg       ;
; 20.417 ; 20.652       ; 0.235          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 20.417 ; 20.652       ; 0.235          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_we_reg       ;
; 20.418 ; 20.653       ; 0.235          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ;
; 20.419 ; 20.654       ; 0.235          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 20.498 ; 20.718       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[0]                                                                   ;
; 20.498 ; 20.718       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[1]                                                                   ;
; 20.498 ; 20.718       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[2]                                                                   ;
; 20.498 ; 20.718       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[3]                                                                   ;
; 20.498 ; 20.718       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[4]                                                                   ;
; 20.498 ; 20.718       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[5]                                                                   ;
; 20.499 ; 20.719       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|SPI_MISO~en                                                                          ;
; 20.499 ; 20.719       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|SPI_MISO~reg0                                                                        ;
; 20.552 ; 20.740       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[2]                                                                       ;
; 20.552 ; 20.740       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[7]                                                                       ;
; 20.552 ; 20.740       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_receiver_strobe_r                                                                ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[0]                                                                           ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[1]                                                                           ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[2]                                                                           ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[0]                                                                               ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[1]                                                                               ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[2]                                                                               ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[3]                                                                               ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[0]                                                                              ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[1]                                                                              ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[2]                                                                              ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[0]                                                                       ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[1]                                                                       ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transfer_end_r                                                                   ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[0]                                                                         ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[1]                                                                         ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[2]                                                                         ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[0]                                                                            ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[1]                                                                            ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[2]                                                                            ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[3]                                                                            ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[4]                                                                            ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[5]                                                                            ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[6]                                                                            ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[0]                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[1]                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[2]                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[3]                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[4]                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[5]                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[6]                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[7]                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_receiver_strobe_r                                                              ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_transfer_end_r                                                                 ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[0]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[10]                                                                                   ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[1]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[2]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[3]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[4]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[5]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[6]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[7]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[8]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[9]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[0]                                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[1]                                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[2]                                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[3]                                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[4]                                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|osd_enable                                                                                 ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[0]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[1]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[2]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.drive_sel_r[0]                                                       ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[10]                                                         ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[14]                                                         ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[17]                                                         ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[18]                                                         ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[1]                                                          ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[22]                                                         ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[25]                                                         ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[26]                                                         ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[2]                                                          ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[30]                                                         ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[6]                                                          ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[9]                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[3]                                                                                     ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[4]                                                                                     ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[5]                                                                                     ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[6]                                                                                     ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[7]                                                                                     ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[3]                                                                                    ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[4]                                                                                    ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[5]                                                                                    ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[6]                                                                                    ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[0]                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[11]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[12]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[13]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[15]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[16]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[19]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[20]                                                         ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                             ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                                                                                                        ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 40.596 ; 41.626       ; 1.030          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                 ;
; 40.674 ; 41.704       ; 1.030          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; rom_loaded                                                                                                                                                                                                    ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                         ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                        ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                        ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                        ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                        ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                        ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                        ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                        ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                         ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                         ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                         ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                         ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                         ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                         ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                         ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                         ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                         ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_reconfig_write_from_rom                                                                                                                                                      ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                      ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                          ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                          ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                          ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                    ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[0]  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_counter_state                                        ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_init_state                                           ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                               ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                         ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|tmp_seq_ena_state                                             ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                   ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[1]                                             ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[2]                                             ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[3]                                             ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[5]                                             ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[6]                                             ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[7]                                             ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[1]                                              ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[2]                                              ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[3]                                              ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[4]                                              ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[6]                                              ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[7]                                              ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|rden_a_store                                                                                ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[0]                                             ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[4]                                             ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[0]                                              ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[5]                                              ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                           ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                           ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                            ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7] ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; 4.668 ; 5.103 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 6.732 ; 6.713 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; 1.131 ; 1.359 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; 1.606 ; 1.897 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 3.027 ; 3.140 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 3.021 ; 3.134 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 3.025 ; 3.138 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 3.027 ; 3.140 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 3.027 ; 3.140 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.964 ; 3.081 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.974 ; 3.091 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.964 ; 3.081 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.965 ; 3.082 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 3.008 ; 3.121 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 3.008 ; 3.121 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 3.010 ; 3.123 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 3.010 ; 3.123 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 3.011 ; 3.124 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 3.011 ; 3.124 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 3.023 ; 3.136 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 3.023 ; 3.136 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                        ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; -2.774 ; -3.091 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 1.080  ; 0.851  ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; -0.685 ; -0.859 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; -0.104 ; -0.280 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; -1.949 ; -2.066 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; -2.009 ; -2.122 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; -2.013 ; -2.126 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; -2.014 ; -2.127 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; -2.014 ; -2.127 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; -1.949 ; -2.066 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; -1.959 ; -2.076 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; -1.949 ; -2.066 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; -1.950 ; -2.067 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; -1.995 ; -2.108 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; -1.995 ; -2.108 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; -1.998 ; -2.111 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; -1.998 ; -2.111 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; -1.999 ; -2.112 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; -1.999 ; -2.112 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; -2.010 ; -2.123 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; -2.010 ; -2.123 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                             ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 10.193 ; 9.520  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 3.295  ; 3.051  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 3.136  ; 2.890  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 3.138  ; 2.892  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 3.138  ; 2.892  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 3.149  ; 2.903  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 3.139  ; 2.908  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 3.295  ; 3.051  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 3.279  ; 3.035  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 3.284  ; 3.040  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 3.284  ; 3.040  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 3.281  ; 3.037  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 3.136  ; 2.890  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 3.288  ; 3.044  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 3.136  ; 2.890  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 3.136  ; 2.890  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 3.126  ; 2.880  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 2.249  ; 2.160  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 3.286  ; 3.042  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 3.267  ; 3.023  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 3.263  ; 3.019  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 3.123  ; 2.892  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 3.123  ; 2.892  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 3.149  ; 2.903  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 3.159  ; 2.913  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 3.149  ; 2.903  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 3.148  ; 2.902  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 3.261  ; 3.017  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 3.261  ; 3.017  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 3.278  ; 3.034  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 3.278  ; 3.034  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 3.118  ; 2.887  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 3.277  ; 3.033  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 3.286  ; 3.042  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 3.127  ; 2.896  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 3.260  ; 3.016  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 3.148  ; 2.902  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 3.136  ; 2.890  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 3.135  ; 2.889  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 3.148  ; 2.902  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 24.653 ; 24.297 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 24.311 ; 23.941 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 24.653 ; 24.297 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 24.375 ; 24.086 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 24.519 ; 24.243 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 24.149 ; 24.033 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 23.309 ; 22.952 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 23.516 ; 23.086 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 22.887 ; 22.581 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 23.444 ; 23.086 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 23.516 ; 23.075 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 22.669 ; 22.334 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 22.569 ; 22.364 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 19.531 ; 18.857 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 7.891  ; 7.309  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 25.769 ; 25.421 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 25.100 ; 24.776 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 25.447 ; 25.183 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 25.769 ; 25.421 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 25.305 ; 25.063 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 25.398 ; 24.954 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 24.594 ; 24.262 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 7.119  ; 6.477  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -1.171 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -1.383 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                     ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 9.990  ; 9.325  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 2.257  ; 2.016  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 2.257  ; 2.016  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 2.259  ; 2.018  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 2.259  ; 2.018  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 2.270  ; 2.029  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 2.258  ; 2.033  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 2.415  ; 2.177  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 2.400  ; 2.162  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 2.404  ; 2.166  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 2.404  ; 2.166  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 2.401  ; 2.163  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 2.257  ; 2.016  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 2.408  ; 2.170  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 2.247  ; 2.006  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 2.257  ; 2.016  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 2.247  ; 2.006  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 1.411  ; 1.321  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 2.239  ; 2.014  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.388  ; 2.150  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.384  ; 2.146  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.243  ; 2.018  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.243  ; 2.018  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.270  ; 2.029  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.280  ; 2.039  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.270  ; 2.029  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.269  ; 2.028  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.381  ; 2.143  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.381  ; 2.143  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.399  ; 2.161  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.399  ; 2.161  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.239  ; 2.014  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.398  ; 2.160  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.406  ; 2.168  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.247  ; 2.022  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 2.380  ; 2.142  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 2.269  ; 2.028  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 2.257  ; 2.016  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 2.256  ; 2.015  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 2.269  ; 2.028  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 6.344  ; 6.058  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 6.593  ; 6.230  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 6.344  ; 6.058  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 6.622  ; 6.144  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 6.639  ; 6.339  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 7.063  ; 6.514  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 6.530  ; 6.145  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 6.092  ; 5.717  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 6.253  ; 5.895  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 6.092  ; 5.717  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 6.688  ; 6.284  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 6.633  ; 6.200  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 6.238  ; 5.908  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 6.986  ; 6.365  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 5.675  ; 5.090  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 6.372  ; 6.086  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 6.372  ; 6.116  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 6.654  ; 6.289  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 6.630  ; 6.322  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 6.486  ; 6.209  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 6.848  ; 6.540  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 6.470  ; 6.086  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 5.385  ; 4.793  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -1.959 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -2.166 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+--------------------------------------------------------------+
; Propagation Delay                                            ;
+------------+-------------+--------+--------+--------+--------+
; Input Port ; Output Port ; RR     ; RF     ; FR     ; FF     ;
+------------+-------------+--------+--------+--------+--------+
; CONF_DATA0 ; SPI_DO      ; 10.717 ; 10.477 ; 11.369 ; 11.369 ;
+------------+-------------+--------+--------+--------+--------+


+------------------------------------------------------------+
; Minimum Propagation Delay                                  ;
+------------+-------------+-------+-------+--------+--------+
; Input Port ; Output Port ; RR    ; RF    ; FR     ; FF     ;
+------------+-------------+-------+-------+--------+--------+
; CONF_DATA0 ; SPI_DO      ; 9.884 ; 9.884 ; 10.511 ; 10.540 ;
+------------+-------------+-------+-------+--------+--------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 9.570 ; 9.570 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 3.143 ; 3.039 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 3.149 ; 3.045 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 3.145 ; 3.041 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 3.164 ; 3.060 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 3.164 ; 3.060 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 3.187 ; 3.084 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 3.197 ; 3.094 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 3.187 ; 3.084 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 3.186 ; 3.083 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 3.143 ; 3.039 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 3.143 ; 3.039 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 3.160 ; 3.056 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 3.160 ; 3.056 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 3.159 ; 3.055 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 3.159 ; 3.055 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 3.168 ; 3.064 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 3.168 ; 3.064 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                     ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 8.809 ; 8.838 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 1.767 ; 1.696 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.774 ; 1.703 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.770 ; 1.699 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.788 ; 1.717 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.788 ; 1.717 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.784 ; 1.731 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.794 ; 1.741 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.784 ; 1.731 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.783 ; 1.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.767 ; 1.696 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.767 ; 1.696 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.785 ; 1.714 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.785 ; 1.714 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.784 ; 1.713 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.784 ; 1.713 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.792 ; 1.721 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.792 ; 1.721 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 8.924     ; 9.164     ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 2.878     ; 3.222     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.884     ; 3.228     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.880     ; 3.224     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.899     ; 3.243     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.899     ; 3.243     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.903     ; 3.266     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.913     ; 3.276     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.903     ; 3.266     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.902     ; 3.265     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.878     ; 3.222     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.878     ; 3.222     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.895     ; 3.239     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.895     ; 3.239     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.894     ; 3.238     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.894     ; 3.238     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.903     ; 3.247     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.903     ; 3.247     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 8.419     ; 8.419     ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 1.743     ; 1.843     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.750     ; 1.850     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.746     ; 1.846     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.764     ; 1.864     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.764     ; 1.864     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.761     ; 1.860     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.771     ; 1.870     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.761     ; 1.860     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.760     ; 1.859     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.743     ; 1.843     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.743     ; 1.843     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.761     ; 1.861     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.761     ; 1.861     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.760     ; 1.860     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.760     ; 1.860     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.768     ; 1.868     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.768     ; 1.868     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                                                                    ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                            ; Note                                                          ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
; 57.32 MHz  ; 57.32 MHz       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                               ;
; 76.18 MHz  ; 76.18 MHz       ; SPI_SCK                                                               ;                                                               ;
; 104.48 MHz ; 100.0 MHz       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; limit due to minimum period restriction (tmin)                ;
; 139.63 MHz ; 139.63 MHz      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                               ;
; 361.27 MHz ; 250.0 MHz       ; clk_27                                                                ; limit due to minimum period restriction (max I/O toggle rate) ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                             ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.298 ; -1.298        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.176  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.979  ; 0.000         ;
; SPI_SCK                                                               ; 14.293 ; 0.000         ;
; clk_27                                                                ; 34.269 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 36.881 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                             ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.336 ; 0.000         ;
; SPI_SCK                                                               ; 0.402 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 0.402 ; 0.000         ;
; clk_27                                                                ; 0.403 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.403 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 2.111 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+-----------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                                         ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.671 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 9.344 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+-----------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                                          ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.463 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.430 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                               ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.097  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 4.167  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.400  ; 0.000         ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 16.279 ; 0.000         ;
; clk_27                                                                ; 18.274 ; 0.000         ;
; SPI_SCK                                                               ; 20.401 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 40.596 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                   ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -1.298 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.958        ; -1.816     ; 1.223      ;
; 2.855  ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                ; SDRAM_A[5]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.992      ; 3.890      ;
; 2.864  ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                             ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.001      ; 3.890      ;
; 2.864  ; sdram_statemachine:sdram_adaptor|addr_reg[11]                               ; SDRAM_A[11]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.001      ; 3.890      ;
; 2.867  ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                ; SDRAM_A[7]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.994      ; 3.880      ;
; 2.867  ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                ; SDRAM_A[8]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.994      ; 3.880      ;
; 2.871  ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                ; SDRAM_A[9]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.998      ; 3.880      ;
; 2.872  ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                             ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.999      ; 3.880      ;
; 2.872  ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                ; SDRAM_A[6]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.999      ; 3.880      ;
; 2.872  ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                             ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.999      ; 3.880      ;
; 2.873  ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                             ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.000      ; 3.880      ;
; 2.883  ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.010      ; 3.880      ;
; 2.887  ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                              ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.014      ; 3.880      ;
; 2.890  ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                              ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.007      ; 3.870      ;
; 2.890  ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                              ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.007      ; 3.870      ;
; 2.891  ; sdram_statemachine:sdram_adaptor|udqm_reg                                   ; SDRAM_DQMH                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.008      ; 3.870      ;
; 2.988  ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                              ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.951      ; 3.716      ;
; 2.998  ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                              ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.951      ; 3.706      ;
; 2.998  ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                              ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.951      ; 3.706      ;
; 2.998  ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                              ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.951      ; 3.706      ;
; 2.999  ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                ; SDRAM_A[3]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.952      ; 3.706      ;
; 2.999  ; sdram_statemachine:sdram_adaptor|we_n_reg                                   ; SDRAM_nWE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.952      ; 3.706      ;
; 2.999  ; sdram_statemachine:sdram_adaptor|ldqm_reg                                   ; SDRAM_DQML                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.952      ; 3.706      ;
; 3.009  ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                ; SDRAM_A[2]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.952      ; 3.696      ;
; 3.010  ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                ; SDRAM_A[1]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.953      ; 3.696      ;
; 3.010  ; sdram_statemachine:sdram_adaptor|addr_reg[10]                               ; SDRAM_A[10]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.953      ; 3.696      ;
; 3.011  ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                ; SDRAM_A[0]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.954      ; 3.696      ;
; 3.011  ; sdram_statemachine:sdram_adaptor|cas_n_reg                                  ; SDRAM_nCAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.954      ; 3.696      ;
; 3.012  ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                ; SDRAM_A[4]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.990      ; 3.731      ;
; 3.012  ; sdram_statemachine:sdram_adaptor|ba_reg[0]                                  ; SDRAM_BA[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.955      ; 3.696      ;
; 3.012  ; sdram_statemachine:sdram_adaptor|ras_n_reg                                  ; SDRAM_nRAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.955      ; 3.696      ;
; 3.020  ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                  ; SDRAM_BA[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.953      ; 3.686      ;
; 3.023  ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                             ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.001      ; 3.731      ;
; 3.027  ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                              ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.005      ; 3.731      ;
; 3.027  ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                              ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.005      ; 3.731      ;
; 3.032  ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                             ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.000      ; 3.721      ;
; 3.216  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5                 ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.965      ; 3.502      ;
; 3.226  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7                 ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.965      ; 3.492      ;
; 3.226  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4                 ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.965      ; 3.492      ;
; 3.226  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6                 ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.965      ; 3.492      ;
; 3.247  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.015      ; 3.521      ;
; 3.247  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.015      ; 3.521      ;
; 3.251  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2                 ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.019      ; 3.521      ;
; 3.251  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3                 ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.019      ; 3.521      ;
; 3.255  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.013      ; 3.511      ;
; 3.255  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.013      ; 3.511      ;
; 3.256  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.014      ; 3.511      ;
; 3.256  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.014      ; 3.511      ;
; 3.266  ; sdram_statemachine:sdram_adaptor|dq_output_reg                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.024      ; 3.511      ;
; 3.270  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1                 ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.028      ; 3.511      ;
; 3.273  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8                 ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.021      ; 3.501      ;
; 3.273  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9                 ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.021      ; 3.501      ;
; 3.724  ; sdram_statemachine:sdram_adaptor|cke_reg                                    ; SDRAM_CKE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.944      ; 2.973      ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                              ;
+-------+------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                              ; To Node                                                                                                                ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.176 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 17.376     ;
; 0.418 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 17.134     ;
; 0.635 ; ioctl_state.IOCTL_IDLE                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.096     ; 16.892     ;
; 0.703 ; reset_load                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.093     ; 16.827     ;
; 0.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 16.763     ;
; 0.805 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.380      ; 17.198     ;
; 0.805 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.380      ; 17.198     ;
; 0.805 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.380      ; 17.198     ;
; 0.805 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.380      ; 17.198     ;
; 0.805 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.380      ; 17.198     ;
; 0.808 ; cart_type_byte[3]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.066     ; 16.749     ;
; 0.821 ; DMA_16BIT_WRITE_ENABLE_IOCTL                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.096     ; 16.706     ;
; 0.915 ; cart_type_byte[2]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.065     ; 16.643     ;
; 0.923 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.521     ; 16.179     ;
; 0.966 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.096     ; 16.561     ;
; 0.974 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 16.581     ;
; 0.990 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.096     ; 16.537     ;
; 0.998 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.096     ; 16.529     ;
; 1.047 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.380      ; 16.956     ;
; 1.047 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.380      ; 16.956     ;
; 1.047 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.380      ; 16.956     ;
; 1.047 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.380      ; 16.956     ;
; 1.047 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.380      ; 16.956     ;
; 1.067 ; cart_type_byte[0]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.066     ; 16.490     ;
; 1.111 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[0]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.525     ; 15.987     ;
; 1.122 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 16.433     ;
; 1.124 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.522     ; 15.977     ;
; 1.127 ; user_io:my_user_io|status[1]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 16.428     ;
; 1.134 ; cart_type_byte[4]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.066     ; 16.423     ;
; 1.138 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[3]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.056     ; 16.429     ;
; 1.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 16.399     ;
; 1.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 16.399     ;
; 1.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 16.399     ;
; 1.152 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.525     ; 15.946     ;
; 1.162 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 16.390     ;
; 1.177 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.170     ; 16.276     ;
; 1.185 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 16.353     ;
; 1.185 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 16.353     ;
; 1.218 ; cart_type_byte[6]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 16.338     ;
; 1.240 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.337      ; 16.720     ;
; 1.240 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.337      ; 16.720     ;
; 1.240 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.337      ; 16.720     ;
; 1.240 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.337      ; 16.720     ;
; 1.240 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.337      ; 16.720     ;
; 1.240 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.337      ; 16.720     ;
; 1.243 ; cart_type_byte[5]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 16.313     ;
; 1.264 ; ioctl_state.IOCTL_IDLE                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.355      ; 16.714     ;
; 1.264 ; ioctl_state.IOCTL_IDLE                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.355      ; 16.714     ;
; 1.264 ; ioctl_state.IOCTL_IDLE                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.355      ; 16.714     ;
; 1.264 ; ioctl_state.IOCTL_IDLE                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.355      ; 16.714     ;
; 1.264 ; ioctl_state.IOCTL_IDLE                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.355      ; 16.714     ;
; 1.284 ; cart_type_byte[1]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.066     ; 16.273     ;
; 1.307 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.541     ; 15.775     ;
; 1.319 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.066     ; 16.238     ;
; 1.324 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 16.226     ;
; 1.329 ; user_io:my_user_io|but_sw[1]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.092     ; 16.202     ;
; 1.332 ; reset_load                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.358      ; 16.649     ;
; 1.332 ; reset_load                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.358      ; 16.649     ;
; 1.332 ; reset_load                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.358      ; 16.649     ;
; 1.332 ; reset_load                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.358      ; 16.649     ;
; 1.332 ; reset_load                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.358      ; 16.649     ;
; 1.336 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 16.198     ;
; 1.336 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 16.198     ;
; 1.357 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 16.195     ;
; 1.362 ; cart_type_byte[7]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 16.194     ;
; 1.364 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[8]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 16.205     ;
; 1.379 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.325      ; 16.569     ;
; 1.379 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.053     ; 16.191     ;
; 1.392 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 16.157     ;
; 1.392 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 16.157     ;
; 1.392 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 16.157     ;
; 1.399 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 16.145     ;
; 1.399 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 16.145     ;
; 1.404 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 16.148     ;
; 1.407 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 16.135     ;
; 1.418 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.380      ; 16.585     ;
; 1.418 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.380      ; 16.585     ;
; 1.418 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.380      ; 16.585     ;
; 1.418 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.380      ; 16.585     ;
; 1.418 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.380      ; 16.585     ;
; 1.424 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.053     ; 16.146     ;
; 1.427 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 16.111     ;
; 1.427 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 16.111     ;
; 1.432 ; DMA_ADDR_FETCH_IOCTL[18]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 16.120     ;
; 1.437 ; cart_type_byte[3]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.385      ; 16.571     ;
; 1.437 ; cart_type_byte[3]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.385      ; 16.571     ;
; 1.437 ; cart_type_byte[3]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.385      ; 16.571     ;
; 1.437 ; cart_type_byte[3]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.385      ; 16.571     ;
; 1.437 ; cart_type_byte[3]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.385      ; 16.571     ;
; 1.445 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.541     ; 15.637     ;
; 1.450 ; DMA_16BIT_WRITE_ENABLE_IOCTL                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.355      ; 16.528     ;
; 1.450 ; DMA_16BIT_WRITE_ENABLE_IOCTL                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.355      ; 16.528     ;
; 1.450 ; DMA_16BIT_WRITE_ENABLE_IOCTL                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.355      ; 16.528     ;
; 1.450 ; DMA_16BIT_WRITE_ENABLE_IOCTL                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.355      ; 16.528     ;
; 1.450 ; DMA_16BIT_WRITE_ENABLE_IOCTL                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.355      ; 16.528     ;
; 1.457 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 16.084     ;
; 1.457 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 16.084     ;
; 1.457 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 16.084     ;
; 1.458 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[5]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.057     ; 16.108     ;
; 1.473 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.521     ; 15.629     ;
+-------+------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.979 ; SDRAM_DQ[3]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.440     ; 1.213      ;
; 0.979 ; SDRAM_DQ[2]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.440     ; 1.213      ;
; 0.981 ; SDRAM_DQ[1]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.448     ; 1.203      ;
; 0.983 ; SDRAM_DQ[14]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.436     ; 1.213      ;
; 0.983 ; SDRAM_DQ[15]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.436     ; 1.213      ;
; 0.985 ; SDRAM_DQ[0]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.444     ; 1.203      ;
; 0.994 ; SDRAM_DQ[13]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.435     ; 1.203      ;
; 0.994 ; SDRAM_DQ[12]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.435     ; 1.203      ;
; 0.995 ; SDRAM_DQ[11]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.434     ; 1.203      ;
; 0.995 ; SDRAM_DQ[10]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.434     ; 1.203      ;
; 0.998 ; SDRAM_DQ[8]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.441     ; 1.193      ;
; 0.998 ; SDRAM_DQ[9]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.441     ; 1.193      ;
; 1.021 ; SDRAM_DQ[5]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.388     ; 1.223      ;
; 1.031 ; SDRAM_DQ[4]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.388     ; 1.213      ;
; 1.031 ; SDRAM_DQ[7]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.388     ; 1.213      ;
; 1.031 ; SDRAM_DQ[6]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.388     ; 1.213      ;
; 1.238 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.405        ; -1.816     ; 1.224      ;
; 1.648 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.124     ; 6.914      ;
; 1.670 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.124     ; 6.892      ;
; 1.757 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.125     ; 6.804      ;
; 1.856 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.124     ; 6.706      ;
; 1.891 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.122     ; 6.673      ;
; 1.969 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.124     ; 6.593      ;
; 1.983 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 6.574      ;
; 2.005 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 6.552      ;
; 2.026 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 6.576      ;
; 2.042 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 6.560      ;
; 2.113 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.085     ; 6.488      ;
; 2.116 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.125     ; 6.445      ;
; 2.178 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.124     ; 6.384      ;
; 2.191 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 6.366      ;
; 2.208 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 6.348      ;
; 2.234 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 6.368      ;
; 2.294 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 6.271      ;
; 2.303 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 6.253      ;
; 2.304 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 6.253      ;
; 2.308 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.122     ; 6.256      ;
; 2.347 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 6.255      ;
; 2.348 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 6.208      ;
; 2.351 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.085     ; 6.250      ;
; 2.360 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.085     ; 6.241      ;
; 2.363 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 6.193      ;
; 2.377 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|udqm_reg                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.122     ; 6.187      ;
; 2.381 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|udqm_reg                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 6.184      ;
; 2.383 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 6.172      ;
; 2.393 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 6.162      ;
; 2.404 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.125     ; 6.157      ;
; 2.419 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]                           ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.177     ; 6.090      ;
; 2.421 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 6.144      ;
; 2.431 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.086     ; 6.169      ;
; 2.436 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 6.119      ;
; 2.451 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 6.105      ;
; 2.481 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 6.074      ;
; 2.494 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.085     ; 6.107      ;
; 2.496 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 6.059      ;
; 2.516 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 6.038      ;
; 2.526 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 6.028      ;
; 2.526 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.067     ; 6.093      ;
; 2.530 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 6.026      ;
; 2.559 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.085     ; 6.042      ;
; 2.569 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.123     ; 5.994      ;
; 2.574 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.124     ; 5.988      ;
; 2.586 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 5.969      ;
; 2.616 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.087     ; 5.983      ;
; 2.617 ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[6]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.227     ; 5.842      ;
; 2.636 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|udqm_reg                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 5.929      ;
; 2.651 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 5.914      ;
; 2.654 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.124     ; 5.908      ;
; 2.663 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 5.892      ;
; 2.667 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 5.935      ;
; 2.672 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.085     ; 5.929      ;
; 2.694 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 5.863      ;
; 2.708 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.123     ; 5.855      ;
; 2.719 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 5.835      ;
; 2.739 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 5.817      ;
; 2.739 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 5.818      ;
; 2.751 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 5.804      ;
; 2.754 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 5.803      ;
; 2.773 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 5.782      ;
; 2.774 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 5.782      ;
; 2.780 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 5.785      ;
; 2.782 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.085     ; 5.819      ;
; 2.784 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 5.772      ;
; 2.804 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 5.754      ;
; 2.819 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.086     ; 5.781      ;
; 2.826 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 5.732      ;
; 2.837 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 5.720      ;
; 2.855 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 5.700      ;
; 2.884 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 5.670      ;
; 2.891 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]                           ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.224     ; 5.571      ;
; 2.908 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 5.650      ;
; 2.920 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 5.682      ;
; 2.921 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 5.636      ;
; 2.922 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|udqm_reg                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.122     ; 5.642      ;
; 2.932 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]                           ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.225     ; 5.529      ;
; 2.933 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 5.624      ;
; 2.934 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]                           ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.223     ; 5.529      ;
; 2.938 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.123     ; 5.625      ;
; 2.940 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|udqm_reg                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 5.625      ;
; 2.948 ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[3]                         ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.180     ; 5.558      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'SPI_SCK'                                                                                                                 ;
+--------+--------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                      ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 14.293 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 6.589      ;
; 14.293 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 6.589      ;
; 14.293 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 6.589      ;
; 14.293 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 6.589      ;
; 14.293 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 6.589      ;
; 14.674 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 6.208      ;
; 14.674 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 6.208      ;
; 14.674 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 6.208      ;
; 14.674 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 6.208      ;
; 14.674 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 6.208      ;
; 14.751 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 6.131      ;
; 14.900 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.982      ;
; 14.900 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.982      ;
; 14.900 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.982      ;
; 14.900 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.982      ;
; 14.900 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.982      ;
; 14.997 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.885      ;
; 14.997 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.885      ;
; 14.997 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.885      ;
; 14.997 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.885      ;
; 14.997 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.885      ;
; 15.132 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.750      ;
; 15.358 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.524      ;
; 15.455 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.427      ;
; 16.488 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.394      ;
; 16.488 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.394      ;
; 16.488 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.394      ;
; 16.488 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.394      ;
; 16.488 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.394      ;
; 16.534 ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 4.340      ;
; 16.534 ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 4.340      ;
; 16.534 ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 4.340      ;
; 16.534 ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 4.340      ;
; 16.534 ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 4.340      ;
; 16.635 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.247      ;
; 16.635 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.247      ;
; 16.635 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.247      ;
; 16.635 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.247      ;
; 16.635 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.247      ;
; 16.650 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.232      ;
; 16.650 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.232      ;
; 16.650 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.232      ;
; 16.650 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.232      ;
; 16.650 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.232      ;
; 16.710 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.005      ; 4.163      ;
; 16.710 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.005      ; 4.163      ;
; 16.710 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.005      ; 4.163      ;
; 16.710 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.005      ; 4.163      ;
; 16.710 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.005      ; 4.163      ;
; 16.730 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 4.144      ;
; 16.730 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 4.144      ;
; 16.730 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 4.144      ;
; 16.730 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 4.144      ;
; 16.730 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 4.144      ;
; 16.751 ; user_io:my_user_io|cmd[1]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 4.123      ;
; 16.751 ; user_io:my_user_io|cmd[1]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 4.123      ;
; 16.751 ; user_io:my_user_io|cmd[1]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 4.123      ;
; 16.751 ; user_io:my_user_io|cmd[1]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 4.123      ;
; 16.751 ; user_io:my_user_io|cmd[1]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 4.123      ;
; 16.785 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 4.089      ;
; 16.785 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 4.089      ;
; 16.785 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 4.089      ;
; 16.785 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 4.089      ;
; 16.785 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 4.089      ;
; 16.812 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.070      ;
; 16.812 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.070      ;
; 16.812 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.070      ;
; 16.812 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.070      ;
; 16.812 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.070      ;
; 16.825 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.005      ; 4.048      ;
; 16.825 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.005      ; 4.048      ;
; 16.825 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.005      ; 4.048      ;
; 16.825 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.005      ; 4.048      ;
; 16.825 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.005      ; 4.048      ;
; 16.899 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.983      ;
; 16.899 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.983      ;
; 16.899 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.983      ;
; 16.899 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.983      ;
; 16.899 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.983      ;
; 16.946 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.936      ;
; 16.977 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.005      ; 3.896      ;
; 16.977 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.005      ; 3.896      ;
; 16.977 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.005      ; 3.896      ;
; 16.977 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.005      ; 3.896      ;
; 16.977 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.005      ; 3.896      ;
; 17.015 ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 3.859      ;
; 17.056 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.826      ;
; 17.056 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.826      ;
; 17.056 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.826      ;
; 17.056 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.826      ;
; 17.056 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.826      ;
; 17.108 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.774      ;
; 17.116 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.766      ;
; 17.191 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.005      ; 3.682      ;
; 17.211 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 3.663      ;
; 17.232 ; user_io:my_user_io|cmd[1]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 3.642      ;
; 17.266 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.006      ; 3.608      ;
; 17.270 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.612      ;
; 17.306 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.005      ; 3.567      ;
; 17.380 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.502      ;
+--------+--------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'clk_27'                                                                                                                                                                 ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 34.269 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.699      ;
; 34.347 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.621      ;
; 34.357 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.611      ;
; 34.382 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.586      ;
; 34.392 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.576      ;
; 34.459 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.509      ;
; 34.471 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.497      ;
; 34.474 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.494      ;
; 34.476 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.492      ;
; 34.511 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.457      ;
; 34.522 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.446      ;
; 34.522 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.446      ;
; 34.582 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.386      ;
; 34.597 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.371      ;
; 34.598 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.370      ;
; 34.607 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.361      ;
; 34.610 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.358      ;
; 34.633 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.335      ;
; 34.727 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.241      ;
; 34.761 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.207      ;
; 35.062 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.906      ;
; 35.072 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.896      ;
; 35.086 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.882      ;
; 35.098 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.870      ;
; 35.104 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.864      ;
; 35.114 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.854      ;
; 35.129 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.839      ;
; 35.151 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.817      ;
; 35.164 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.804      ;
; 35.174 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.794      ;
; 35.181 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.787      ;
; 35.209 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.759      ;
; 35.228 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.740      ;
; 35.239 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.729      ;
; 35.240 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.728      ;
; 35.247 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.721      ;
; 35.251 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.717      ;
; 35.257 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.711      ;
; 35.270 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.698      ;
; 35.288 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.680      ;
; 35.290 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.678      ;
; 35.293 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.675      ;
; 35.293 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.675      ;
; 35.395 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.573      ;
; 35.398 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.570      ;
; 35.407 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.561      ;
; 35.413 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.555      ;
; 35.421 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.547      ;
; 35.440 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.528      ;
; 35.562 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.406      ;
; 35.575 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.393      ;
; 35.583 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.385      ;
; 35.588 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.380      ;
; 35.588 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.380      ;
; 35.729 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.239      ;
; 35.755 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.213      ;
; 35.817 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.151      ;
; 35.819 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.149      ;
; 35.852 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.116      ;
; 36.198 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 0.770      ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 36.881 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_we_reg ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.737     ; 6.162      ;
; 36.956 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.609      ; 8.322      ;
; 38.704 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.378     ; 4.698      ;
; 38.972 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.378     ; 4.430      ;
; 39.024 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.373     ; 4.383      ;
; 39.026 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.373     ; 4.381      ;
; 39.145 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.378     ; 4.257      ;
; 39.225 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.373     ; 4.182      ;
; 39.283 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.378     ; 4.119      ;
; 39.307 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.621      ; 5.983      ;
; 39.352 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.373     ; 4.055      ;
; 39.406 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.621      ; 5.884      ;
; 39.593 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.621      ; 5.697      ;
; 39.599 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.373     ; 3.808      ;
; 39.820 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.378     ; 3.582      ;
; 40.480 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.385     ; 2.915      ;
; 40.546 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate3_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.119     ; 1.003      ;
; 40.865 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                             ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.386     ; 2.529      ;
; 75.748 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.086     ; 7.501      ;
; 75.775 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.084     ; 7.476      ;
; 77.867 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.072     ; 5.396      ;
; 77.950 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.074     ; 5.311      ;
; 77.977 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.293      ; 5.688      ;
; 77.997 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.072     ; 5.266      ;
; 78.080 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.074     ; 5.181      ;
; 78.159 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.072     ; 5.104      ;
; 78.199 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.293      ; 5.466      ;
; 78.242 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.074     ; 5.019      ;
; 78.498 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                                                 ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.293      ; 5.167      ;
; 78.498 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                                                 ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.293      ; 5.167      ;
; 78.793 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.074     ; 4.468      ;
; 78.903 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                                                ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.281      ; 4.750      ;
; 78.903 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                                                ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.281      ; 4.750      ;
; 79.004 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 3.609      ; 7.940      ;
; 79.113 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.060     ; 4.162      ;
; 79.146 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.070     ; 4.119      ;
; 79.146 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.070     ; 4.119      ;
; 79.146 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.070     ; 4.119      ;
; 79.146 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.070     ; 4.119      ;
; 79.146 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.070     ; 4.119      ;
; 79.146 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.070     ; 4.119      ;
; 79.146 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.070     ; 4.119      ;
; 79.146 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.070     ; 4.119      ;
; 79.172 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.290      ; 4.490      ;
; 79.172 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.290      ; 4.490      ;
; 79.178 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_last_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.283      ; 4.477      ;
; 79.183 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.076      ;
; 79.183 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.076      ;
; 79.183 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.076      ;
; 79.183 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.076      ;
; 79.183 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.076      ;
; 79.183 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.060     ; 4.092      ;
; 79.183 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.060     ; 4.092      ;
; 79.183 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.060     ; 4.092      ;
; 79.183 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.060     ; 4.092      ;
; 79.183 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.060     ; 4.092      ;
; 79.183 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.060     ; 4.092      ;
; 79.183 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.060     ; 4.092      ;
; 79.183 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.060     ; 4.092      ;
; 79.220 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.066     ; 4.049      ;
; 79.220 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.066     ; 4.049      ;
; 79.220 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.066     ; 4.049      ;
; 79.220 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.066     ; 4.049      ;
; 79.220 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.066     ; 4.049      ;
; 79.355 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.060     ; 3.920      ;
; 79.356 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 3.894      ;
; 79.363 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.086     ; 3.886      ;
; 79.363 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.086     ; 3.886      ;
; 79.363 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.086     ; 3.886      ;
; 79.363 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.086     ; 3.886      ;
; 79.363 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.086     ; 3.886      ;
; 79.363 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.086     ; 3.886      ;
; 79.363 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.086     ; 3.886      ;
; 79.363 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.086     ; 3.886      ;
; 79.377 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.060     ; 3.898      ;
; 79.406 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_datain_reg0  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.298      ; 4.264      ;
; 79.415 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.060     ; 3.860      ;
; 79.432 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.038     ; 5.977      ;
; 79.434 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.060     ; 3.841      ;
; 79.447 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 3.803      ;
; 79.456 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.283      ; 4.199      ;
; 79.456 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.283      ; 4.199      ;
; 79.458 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.060     ; 3.817      ;
; 79.475 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.060     ; 3.800      ;
; 79.486 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.060     ; 3.789      ;
; 79.486 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.060     ; 3.789      ;
; 79.511 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.059     ; 3.765      ;
; 79.523 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.066     ; 3.746      ;
; 79.523 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.066     ; 3.746      ;
; 79.523 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.066     ; 3.746      ;
; 79.523 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.066     ; 3.746      ;
; 79.523 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.066     ; 3.746      ;
; 79.545 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.291      ; 4.118      ;
; 79.575 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.296      ; 4.093      ;
; 79.576 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.296      ; 4.092      ;
; 79.595 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.062     ; 3.678      ;
; 79.595 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.062     ; 3.678      ;
; 79.595 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.062     ; 3.678      ;
; 79.595 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.062     ; 3.678      ;
; 79.595 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.062     ; 3.678      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                              ; To Node                                                                                                                                                                                                                                ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.336 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[7]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.422      ; 0.988      ;
; 0.337 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[1]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.422      ; 0.989      ;
; 0.383 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_freezer_reg                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_freezer_reg                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 0.669      ;
; 0.383 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 0.669      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[3]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[3]                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[2]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[2]                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[1]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[1]                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[0]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[0]                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[6]                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[6]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.385 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqa_reg[1]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqa_reg[1]                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.089      ; 0.669      ;
; 0.385 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[4]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[4]                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.089      ; 0.669      ;
; 0.385 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[3]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[3]                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.089      ; 0.669      ;
; 0.386 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 0.669      ;
; 0.386 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 0.669      ;
; 0.386 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 0.669      ;
; 0.386 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 0.669      ;
; 0.387 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.087      ; 0.669      ;
; 0.390 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.427      ; 1.047      ;
; 0.392 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[3]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.427      ; 1.049      ;
; 0.394 ; user_io:my_user_io|sd_dout[2]                                                                                                                                                          ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.423      ; 1.047      ;
; 0.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1]                                                                                       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.423      ; 1.054      ;
; 0.402 ; user_io:my_user_io|ps2_kbd_wptr[0]                                                                                                                                                     ; user_io:my_user_io|ps2_kbd_wptr[0]                                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|ps2_kbd_wptr[1]                                                                                                                                                     ; user_io:my_user_io|ps2_kbd_wptr[1]                                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|ps2_kbd_wptr[2]                                                                                                                                                     ; user_io:my_user_io|ps2_kbd_wptr[2]                                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[1]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ZPU_IN1[30]                                                                                                                                                                            ; ZPU_IN1[30]                                                                                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                                                                        ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[89]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[89]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|low_addressa[2] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|low_addressa[2]                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                                                                                                           ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ZPU_IN1[31]                                                                                                                                                                            ; ZPU_IN1[31]                                                                                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|scl_ena                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|scl_ena                                                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|ack_error                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|ack_error                                                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; scandoubler:scandoubler1|buffer_select_reg                                                                                                                                             ; scandoubler:scandoubler1|buffer_select_reg                                                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; scandoubler:scandoubler1|vga_odd_reg                                                                                                                                                   ; scandoubler:scandoubler1|vga_odd_reg                                                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; scandoubler:scandoubler1|vga_hsync_reg                                                                                                                                                 ; scandoubler:scandoubler1|vga_hsync_reg                                                                                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|status[23]                                                                                                                                                          ; user_io:my_user_io|status[23]                                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|status[0]                                                                                                                                                           ; user_io:my_user_io|status[0]                                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                                                                                                     ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[8]                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[8]                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[9]                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[9]                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[11]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[11]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[0]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[0]                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|use_status_as_ram_address                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|use_status_as_ram_address                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|vector_a2                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|vector_a2                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[2]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[2]                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hblank_reg                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hblank_reg                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_display_active_reg                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_display_active_reg                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vsync_reg                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vsync_reg                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[0]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[0]                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[1]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[1]                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[0]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[0]                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[2]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[2]                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[3]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[3]                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[1]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[1]                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqst_reg[6]                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqst_reg[6]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|keyboard_overrun_reg                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|keyboard_overrun_reg                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[1]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[1]                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[2]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[2]                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[3]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[3]                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_pending_reg                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_pending_reg                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[12]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[12]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; sdram_statemachine:sdram_adaptor|sdram_request_reg                                                                                                                                     ; sdram_statemachine:sdram_adaptor|sdram_request_reg                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[10]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[10]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_32bit_reg                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_32bit_reg                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; data_io:mist_data_io|ioctl_download                                                                                                                                                    ; data_io:mist_data_io|ioctl_download                                                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5                                                                                                                   ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_insn_fetch                                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_insn_fetch                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'SPI_SCK'                                                                                                                                                                                               ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                  ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.402 ; osd:osd_inst|osd_enable                    ; osd:osd_inst|osd_enable                                                                                 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|bit_cnt[1]              ; user_io:my_user_io|bit_cnt[1]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|bit_cnt[2]              ; user_io:my_user_io|bit_cnt[2]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|byte_cnt[0]             ; user_io:my_user_io|byte_cnt[0]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|cmd[6]                  ; user_io:my_user_io|cmd[6]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|cmd[7]                  ; user_io:my_user_io|cmd[7]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|cmd[3]                  ; user_io:my_user_io|cmd[3]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|cmd[0]                  ; user_io:my_user_io|cmd[0]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|cmd[1]                  ; user_io:my_user_io|cmd[1]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|cmd[2]                  ; user_io:my_user_io|cmd[2]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; data_io:mist_data_io|bit_cnt[1]            ; data_io:mist_data_io|bit_cnt[1]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; data_io:mist_data_io|bit_cnt[2]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.669      ;
; 0.405 ; osd:osd_inst|sbuf[2]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.426      ; 1.061      ;
; 0.406 ; user_io:my_user_io|serial_out_rptr[0]      ; user_io:my_user_io|serial_out_rptr[0]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.068      ; 0.669      ;
; 0.409 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.426      ; 1.065      ;
; 0.410 ; osd:osd_inst|sbuf[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.426      ; 1.066      ;
; 0.415 ; osd:osd_inst|sbuf[0]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.426      ; 1.071      ;
; 0.417 ; osd:osd_inst|bcnt[0]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.420      ; 1.067      ;
; 0.417 ; user_io:my_user_io|bit_cnt[0]              ; user_io:my_user_io|bit_cnt[0]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.684      ;
; 0.417 ; user_io:my_user_io|spi_receiver_strobe_r   ; user_io:my_user_io|spi_receiver_strobe_r                                                                ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.684      ;
; 0.418 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[0]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.684      ;
; 0.418 ; data_io:mist_data_io|spi_receiver_strobe_r ; data_io:mist_data_io|spi_receiver_strobe_r                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.684      ;
; 0.425 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.426      ; 1.081      ;
; 0.425 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.426      ; 1.081      ;
; 0.432 ; osd:osd_inst|sbuf[6]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.426      ; 1.088      ;
; 0.432 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.420      ; 1.082      ;
; 0.440 ; osd:osd_inst|bcnt[3]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.421      ; 1.091      ;
; 0.453 ; osd:osd_inst|bcnt[10]                      ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.420      ; 1.103      ;
; 0.455 ; osd:osd_inst|bcnt[5]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.421      ; 1.106      ;
; 0.461 ; user_io:my_user_io|serial_out_rptr[5]      ; user_io:my_user_io|serial_out_rptr[5]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.068      ; 0.724      ;
; 0.462 ; osd:osd_inst|bcnt[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.420      ; 1.112      ;
; 0.465 ; osd:osd_inst|cnt[4]                        ; osd:osd_inst|cnt[4]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.732      ;
; 0.465 ; osd:osd_inst|bcnt[8]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.421      ; 1.116      ;
; 0.470 ; data_io:mist_data_io|sbuf[6]               ; data_io:mist_data_io|spi_byte_in[7]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.737      ;
; 0.473 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[1]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.739      ;
; 0.477 ; data_io:mist_data_io|sbuf[1]               ; data_io:mist_data_io|spi_byte_in[2]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.744      ;
; 0.477 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.743      ;
; 0.478 ; data_io:mist_data_io|sbuf[0]               ; data_io:mist_data_io|sbuf[1]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.745      ;
; 0.478 ; data_io:mist_data_io|sbuf[1]               ; data_io:mist_data_io|sbuf[2]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.745      ;
; 0.478 ; data_io:mist_data_io|sbuf[2]               ; data_io:mist_data_io|sbuf[3]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.745      ;
; 0.478 ; data_io:mist_data_io|sbuf[3]               ; data_io:mist_data_io|sbuf[4]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.745      ;
; 0.478 ; data_io:mist_data_io|sbuf[4]               ; data_io:mist_data_io|sbuf[5]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.745      ;
; 0.478 ; data_io:mist_data_io|sbuf[3]               ; data_io:mist_data_io|spi_byte_in[4]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.745      ;
; 0.478 ; data_io:mist_data_io|sbuf[4]               ; data_io:mist_data_io|spi_byte_in[5]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.745      ;
; 0.478 ; data_io:mist_data_io|sbuf[2]               ; data_io:mist_data_io|spi_byte_in[3]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.745      ;
; 0.478 ; data_io:mist_data_io|sbuf[0]               ; data_io:mist_data_io|spi_byte_in[1]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.745      ;
; 0.486 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|sbuf[6]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.753      ;
; 0.486 ; user_io:my_user_io|sbuf[4]                 ; user_io:my_user_io|spi_byte_in[5]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.753      ;
; 0.487 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|spi_byte_in[6]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.754      ;
; 0.489 ; user_io:my_user_io|sbuf[4]                 ; user_io:my_user_io|sbuf[5]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.756      ;
; 0.499 ; user_io:my_user_io|bit_cnt[1]              ; user_io:my_user_io|bit_cnt[2]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.766      ;
; 0.506 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|sbuf[4]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.773      ;
; 0.508 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|cmd[4]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.775      ;
; 0.608 ; osd:osd_inst|bcnt[3]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.420      ; 1.258      ;
; 0.653 ; data_io:mist_data_io|sbuf[5]               ; data_io:mist_data_io|spi_byte_in[6]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.920      ;
; 0.654 ; data_io:mist_data_io|sbuf[5]               ; data_io:mist_data_io|sbuf[6]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.921      ;
; 0.661 ; user_io:my_user_io|sbuf[3]                 ; user_io:my_user_io|sbuf[4]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.928      ;
; 0.662 ; user_io:my_user_io|sbuf[3]                 ; user_io:my_user_io|spi_byte_in[4]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.929      ;
; 0.670 ; user_io:my_user_io|sbuf[0]                 ; user_io:my_user_io|spi_byte_in[1]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.937      ;
; 0.672 ; user_io:my_user_io|sbuf[0]                 ; user_io:my_user_io|sbuf[1]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.939      ;
; 0.682 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|cmd[6]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.949      ;
; 0.683 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|sbuf[5]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.950      ;
; 0.684 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|sbuf[6]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.951      ;
; 0.684 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|cmd[5]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.951      ;
; 0.685 ; osd:osd_inst|bcnt[2]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.421      ; 1.336      ;
; 0.690 ; osd:osd_inst|bcnt[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.421      ; 1.341      ;
; 0.699 ; user_io:my_user_io|serial_out_rptr[2]      ; user_io:my_user_io|serial_out_rptr[2]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.068      ; 0.962      ;
; 0.699 ; user_io:my_user_io|serial_out_rptr[3]      ; user_io:my_user_io|serial_out_rptr[3]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.068      ; 0.962      ;
; 0.701 ; user_io:my_user_io|serial_out_rptr[4]      ; user_io:my_user_io|serial_out_rptr[4]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.068      ; 0.964      ;
; 0.702 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|cmd[6]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.969      ;
; 0.706 ; osd:osd_inst|cnt[1]                        ; osd:osd_inst|cnt[1]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.973      ;
; 0.708 ; osd:osd_inst|cnt[2]                        ; osd:osd_inst|cnt[2]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.975      ;
; 0.708 ; osd:osd_inst|bcnt[5]                       ; osd:osd_inst|bcnt[5]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.974      ;
; 0.708 ; user_io:my_user_io|sbuf[6]                 ; user_io:my_user_io|cmd[7]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.975      ;
; 0.708 ; user_io:my_user_io|sbuf[1]                 ; user_io:my_user_io|cmd[2]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.975      ;
; 0.709 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|bcnt[1]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.975      ;
; 0.709 ; osd:osd_inst|bcnt[2]                       ; osd:osd_inst|bcnt[2]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.975      ;
; 0.709 ; osd:osd_inst|bcnt[6]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.420      ; 1.359      ;
; 0.709 ; user_io:my_user_io|byte_cnt[2]             ; user_io:my_user_io|byte_cnt[2]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.976      ;
; 0.710 ; osd:osd_inst|bcnt[3]                       ; osd:osd_inst|bcnt[3]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.976      ;
; 0.710 ; osd:osd_inst|bcnt[4]                       ; osd:osd_inst|bcnt[4]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.976      ;
; 0.710 ; user_io:my_user_io|sbuf[0]                 ; user_io:my_user_io|cmd[1]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.977      ;
; 0.711 ; data_io:mist_data_io|bit_cnt[1]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.977      ;
; 0.711 ; osd:osd_inst|bcnt[7]                       ; osd:osd_inst|bcnt[7]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.977      ;
; 0.711 ; osd:osd_inst|bcnt[9]                       ; osd:osd_inst|bcnt[9]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.977      ;
; 0.712 ; osd:osd_inst|bcnt[10]                      ; osd:osd_inst|bcnt[10]                                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.978      ;
; 0.714 ; osd:osd_inst|bcnt[6]                       ; osd:osd_inst|bcnt[6]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.980      ;
; 0.714 ; osd:osd_inst|bcnt[8]                       ; osd:osd_inst|bcnt[8]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.980      ;
; 0.717 ; user_io:my_user_io|byte_cnt[3]             ; user_io:my_user_io|byte_cnt[3]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.984      ;
; 0.717 ; user_io:my_user_io|byte_cnt[4]             ; user_io:my_user_io|byte_cnt[4]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.984      ;
; 0.718 ; osd:osd_inst|cnt[3]                        ; osd:osd_inst|cnt[3]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.985      ;
; 0.718 ; user_io:my_user_io|byte_cnt[8]             ; user_io:my_user_io|byte_cnt[8]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.985      ;
; 0.719 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.421      ; 1.370      ;
; 0.719 ; user_io:my_user_io|byte_cnt[6]             ; user_io:my_user_io|byte_cnt[6]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.986      ;
; 0.720 ; user_io:my_user_io|sbuf[2]                 ; user_io:my_user_io|cmd[3]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.987      ;
; 0.721 ; user_io:my_user_io|byte_cnt[5]             ; user_io:my_user_io|byte_cnt[5]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.988      ;
; 0.722 ; user_io:my_user_io|serial_out_rptr[1]      ; user_io:my_user_io|serial_out_rptr[1]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.068      ; 0.985      ;
; 0.724 ; user_io:my_user_io|serial_out_rptr[0]      ; user_io:my_user_io|serial_out_rptr[1]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.068      ; 0.987      ;
; 0.729 ; osd:osd_inst|cnt[0]                        ; osd:osd_inst|cnt[0]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.996      ;
; 0.735 ; osd:osd_inst|bcnt[0]                       ; osd:osd_inst|bcnt[0]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.001      ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                     ; To Node                                                                                                                                                                                                       ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.402 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; rom_loaded                                                                                                                                                                                                    ; rom_loaded                                                                                                                                                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.417 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.684      ;
; 0.455 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.721      ;
; 0.457 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.724      ;
; 0.457 ; rom_loaded                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.723      ;
; 0.471 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.737      ;
; 0.476 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.743      ;
; 0.479 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.745      ;
; 0.480 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.746      ;
; 0.511 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.777      ;
; 0.517 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.783      ;
; 0.518 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.784      ;
; 0.519 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.785      ;
; 0.520 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.786      ;
; 0.609 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.875      ;
; 0.611 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|tmp_seq_ena_state                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.877      ;
; 0.612 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.878      ;
; 0.622 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.888      ;
; 0.625 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_counter_state                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.891      ;
; 0.625 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                              ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.420      ; 1.275      ;
; 0.645 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[2]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[2]                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.912      ;
; 0.645 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[1]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[1]                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.912      ;
; 0.646 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[6]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[6]                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.913      ;
; 0.647 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                          ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.913      ;
; 0.647 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[7]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[7]                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.914      ;
; 0.647 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[3]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[3]                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.914      ;
; 0.647 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[0]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[0]                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.914      ;
; 0.669 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.936      ;
; 0.683 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.950      ;
; 0.683 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.950      ;
; 0.684 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.951      ;
; 0.686 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.952      ;
; 0.687 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.954      ;
; 0.687 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.953      ;
; 0.687 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.953      ;
; 0.689 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.956      ;
; 0.689 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.689 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.690 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.957      ;
; 0.690 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.957      ;
; 0.690 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.956      ;
; 0.691 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.957      ;
; 0.692 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.958      ;
; 0.693 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.960      ;
; 0.694 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.960      ;
; 0.694 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.961      ;
; 0.695 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.962      ;
; 0.695 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.962      ;
; 0.695 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.962      ;
; 0.696 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.963      ;
; 0.696 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.963      ;
; 0.696 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.963      ;
; 0.696 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.962      ;
; 0.697 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.964      ;
; 0.697 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.964      ;
; 0.698 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.964      ;
; 0.700 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.967      ;
; 0.700 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.967      ;
; 0.700 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.966      ;
; 0.707 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.974      ;
; 0.707 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.974      ;
; 0.707 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.973      ;
; 0.708 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.975      ;
; 0.709 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.976      ;
; 0.709 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.975      ;
; 0.709 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.975      ;
; 0.710 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.976      ;
; 0.710 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.976      ;
; 0.712 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.979      ;
; 0.713 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.980      ;
; 0.713 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.979      ;
; 0.713 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.979      ;
; 0.713 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.980      ;
; 0.714 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.981      ;
; 0.714 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.980      ;
; 0.714 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.980      ;
; 0.715 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.982      ;
; 0.718 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.984      ;
; 0.718 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.984      ;
; 0.720 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.986      ;
; 0.720 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.986      ;
; 0.722 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.988      ;
; 0.724 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.991      ;
; 0.730 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.996      ;
; 0.730 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.996      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'clk_27'                                                                                                                                                                 ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 0.669      ;
; 0.696 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 0.962      ;
; 0.698 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 0.964      ;
; 0.701 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 0.967      ;
; 0.878 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.144      ;
; 0.884 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.150      ;
; 0.884 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.150      ;
; 0.891 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.157      ;
; 0.891 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.157      ;
; 0.892 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.158      ;
; 1.008 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.274      ;
; 1.016 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.282      ;
; 1.019 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.285      ;
; 1.022 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.288      ;
; 1.023 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.289      ;
; 1.024 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.290      ;
; 1.026 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.292      ;
; 1.030 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.296      ;
; 1.031 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.297      ;
; 1.031 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.297      ;
; 1.031 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.297      ;
; 1.033 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.299      ;
; 1.034 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.300      ;
; 1.112 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.378      ;
; 1.138 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.404      ;
; 1.141 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.407      ;
; 1.156 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.422      ;
; 1.157 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.423      ;
; 1.163 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.429      ;
; 1.164 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.430      ;
; 1.165 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.431      ;
; 1.168 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.434      ;
; 1.170 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.436      ;
; 1.175 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.441      ;
; 1.177 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.443      ;
; 1.190 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.456      ;
; 1.191 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.457      ;
; 1.192 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.458      ;
; 1.193 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.459      ;
; 1.197 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.463      ;
; 1.198 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.464      ;
; 1.198 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.464      ;
; 1.199 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.465      ;
; 1.200 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.466      ;
; 1.200 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.466      ;
; 1.203 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.469      ;
; 1.294 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.560      ;
; 1.299 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.565      ;
; 1.301 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.567      ;
; 1.325 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.591      ;
; 1.326 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.592      ;
; 1.332 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.598      ;
; 1.333 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.599      ;
; 1.333 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.599      ;
; 1.334 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.600      ;
; 1.462 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.728      ;
; 1.463 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.729      ;
; 1.467 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.733      ;
; 1.468 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.734      ;
; 1.469 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.735      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                             ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                     ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.403 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.418 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.684      ;
; 0.469 ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.735      ;
; 0.470 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.736      ;
; 0.687 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.953      ;
; 0.688 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.954      ;
; 0.689 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.689 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.689 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.692 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.958      ;
; 0.692 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.958      ;
; 0.696 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.962      ;
; 0.696 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.962      ;
; 0.696 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.962      ;
; 0.697 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.963      ;
; 0.697 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.963      ;
; 0.699 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.965      ;
; 0.701 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.967      ;
; 0.701 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.967      ;
; 0.703 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.969      ;
; 0.704 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.970      ;
; 0.706 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.972      ;
; 0.706 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.972      ;
; 0.707 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.973      ;
; 0.709 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.975      ;
; 0.710 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.976      ;
; 0.710 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.976      ;
; 0.711 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.977      ;
; 0.711 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.977      ;
; 0.714 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.980      ;
; 0.715 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.981      ;
; 0.717 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.983      ;
; 0.718 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.984      ;
; 0.718 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.984      ;
; 0.729 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.995      ;
; 0.739 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.005      ;
; 0.740 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.006      ;
; 0.774 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.040      ;
; 0.852 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.118      ;
; 0.856 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.122      ;
; 0.893 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.159      ;
; 1.006 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.272      ;
; 1.007 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.273      ;
; 1.010 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.276      ;
; 1.010 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.276      ;
; 1.013 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.279      ;
; 1.013 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.279      ;
; 1.013 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.279      ;
; 1.013 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.279      ;
; 1.015 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.281      ;
; 1.018 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.284      ;
; 1.020 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.286      ;
; 1.020 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.286      ;
; 1.020 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.286      ;
; 1.021 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.287      ;
; 1.021 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.287      ;
; 1.021 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.287      ;
; 1.022 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.288      ;
; 1.023 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.289      ;
; 1.024 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.290      ;
; 1.025 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.291      ;
; 1.026 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.292      ;
; 1.026 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.292      ;
; 1.027 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.293      ;
; 1.028 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.294      ;
; 1.028 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.294      ;
; 1.028 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.294      ;
; 1.029 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.295      ;
; 1.030 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.296      ;
; 1.030 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.296      ;
; 1.031 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.297      ;
; 1.031 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.297      ;
; 1.035 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.301      ;
; 1.035 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.301      ;
; 1.035 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.301      ;
; 1.035 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.301      ;
; 1.039 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.305      ;
; 1.039 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.305      ;
; 1.040 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.306      ;
; 1.042 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.308      ;
; 1.042 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.308      ;
; 1.042 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.308      ;
; 1.043 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.309      ;
; 1.044 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.310      ;
; 1.044 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.310      ;
; 1.048 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.314      ;
; 1.058 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.324      ;
; 1.059 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.325      ;
; 1.069 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.335      ;
; 1.073 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.339      ;
; 1.074 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.340      ;
; 1.084 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.350      ;
; 1.085 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 1.346      ;
; 1.089 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 1.350      ;
; 1.092 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 1.353      ;
; 1.107 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.373      ;
; 1.108 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.374      ;
; 1.108 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.374      ;
; 1.115 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.381      ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 2.111 ; sdram_statemachine:sdram_adaptor|cke_reg                                    ; SDRAM_CKE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.256      ; 2.830      ;
; 2.225 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8                 ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.334      ; 3.022      ;
; 2.225 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9                 ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.334      ; 3.022      ;
; 2.228 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1                 ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.341      ; 3.032      ;
; 2.232 ; sdram_statemachine:sdram_adaptor|dq_output_reg                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.337      ; 3.032      ;
; 2.241 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.328      ; 3.032      ;
; 2.241 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.328      ; 3.032      ;
; 2.242 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.327      ; 3.032      ;
; 2.242 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.327      ; 3.032      ;
; 2.246 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2                 ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.333      ; 3.042      ;
; 2.246 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3                 ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.333      ; 3.042      ;
; 2.248 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7                 ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.281      ; 2.992      ;
; 2.248 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4                 ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.281      ; 2.992      ;
; 2.248 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6                 ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.281      ; 2.992      ;
; 2.250 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.329      ; 3.042      ;
; 2.250 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.329      ; 3.042      ;
; 2.258 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5                 ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.281      ; 3.002      ;
; 2.716 ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                  ; SDRAM_BA[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.270      ; 3.449      ;
; 2.719 ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                             ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.315      ; 3.497      ;
; 2.724 ; sdram_statemachine:sdram_adaptor|ba_reg[0]                                  ; SDRAM_BA[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.272      ; 3.459      ;
; 2.724 ; sdram_statemachine:sdram_adaptor|ras_n_reg                                  ; SDRAM_nRAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.272      ; 3.459      ;
; 2.724 ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                              ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.320      ; 3.507      ;
; 2.724 ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                              ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.320      ; 3.507      ;
; 2.725 ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                ; SDRAM_A[0]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.271      ; 3.459      ;
; 2.725 ; sdram_statemachine:sdram_adaptor|cas_n_reg                                  ; SDRAM_nCAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.271      ; 3.459      ;
; 2.726 ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                ; SDRAM_A[1]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.270      ; 3.459      ;
; 2.726 ; sdram_statemachine:sdram_adaptor|addr_reg[10]                               ; SDRAM_A[10]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.270      ; 3.459      ;
; 2.727 ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                ; SDRAM_A[2]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.269      ; 3.459      ;
; 2.728 ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                             ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.316      ; 3.507      ;
; 2.737 ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                ; SDRAM_A[3]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.269      ; 3.469      ;
; 2.737 ; sdram_statemachine:sdram_adaptor|we_n_reg                                   ; SDRAM_nWE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.269      ; 3.469      ;
; 2.737 ; sdram_statemachine:sdram_adaptor|ldqm_reg                                   ; SDRAM_DQML                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.269      ; 3.469      ;
; 2.738 ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                ; SDRAM_A[4]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.306      ; 3.507      ;
; 2.738 ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                              ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.268      ; 3.469      ;
; 2.738 ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                              ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.268      ; 3.469      ;
; 2.738 ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                              ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.268      ; 3.469      ;
; 2.748 ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                              ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.268      ; 3.479      ;
; 2.848 ; sdram_statemachine:sdram_adaptor|udqm_reg                                   ; SDRAM_DQMH                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.322      ; 3.633      ;
; 2.849 ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                              ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.321      ; 3.633      ;
; 2.849 ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                              ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.321      ; 3.633      ;
; 2.852 ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                              ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.328      ; 3.643      ;
; 2.856 ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.324      ; 3.643      ;
; 2.865 ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                             ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.315      ; 3.643      ;
; 2.866 ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                ; SDRAM_A[6]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.314      ; 3.643      ;
; 2.866 ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                             ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.314      ; 3.643      ;
; 2.866 ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                             ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.314      ; 3.643      ;
; 2.867 ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                ; SDRAM_A[9]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.313      ; 3.643      ;
; 2.871 ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                ; SDRAM_A[7]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.309      ; 3.643      ;
; 2.871 ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                ; SDRAM_A[8]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.309      ; 3.643      ;
; 2.874 ; sdram_statemachine:sdram_adaptor|addr_reg[11]                               ; SDRAM_A[11]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.316      ; 3.653      ;
; 2.874 ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                             ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.316      ; 3.653      ;
; 2.882 ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                ; SDRAM_A[5]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.308      ; 3.653      ;
; 9.190 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -6.853       ; -1.566     ; 0.973      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                 ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                      ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 2.671 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.301     ; 5.703      ;
; 2.671 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.301     ; 5.703      ;
; 2.671 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.301     ; 5.703      ;
; 2.671 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.301     ; 5.703      ;
; 2.695 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.357     ; 5.623      ;
; 2.695 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.354     ; 5.626      ;
; 2.695 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.354     ; 5.626      ;
; 2.700 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.347     ; 5.628      ;
; 2.700 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.353     ; 5.622      ;
; 2.700 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.347     ; 5.628      ;
; 2.700 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.353     ; 5.622      ;
; 2.705 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.361     ; 5.609      ;
; 2.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 5.797      ;
; 2.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 5.797      ;
; 2.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 5.797      ;
; 2.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 5.797      ;
; 2.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 5.793      ;
; 2.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 5.793      ;
; 2.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.182     ; 5.796      ;
; 2.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.182     ; 5.796      ;
; 2.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.184     ; 5.794      ;
; 2.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.183     ; 5.795      ;
; 2.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.182     ; 5.796      ;
; 2.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.182     ; 5.796      ;
; 2.709 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.349     ; 5.617      ;
; 2.709 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.348     ; 5.618      ;
; 2.709 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.348     ; 5.618      ;
; 2.709 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.349     ; 5.617      ;
; 2.709 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.183     ; 5.794      ;
; 2.709 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.184     ; 5.793      ;
; 2.709 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.183     ; 5.794      ;
; 2.712 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.227     ; 5.747      ;
; 2.722 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.221     ; 5.743      ;
; 2.722 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.226     ; 5.738      ;
; 2.722 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.229     ; 5.735      ;
; 2.729 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.222     ; 5.735      ;
; 2.729 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.222     ; 5.735      ;
; 2.732 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.237     ; 5.717      ;
; 2.732 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.234     ; 5.720      ;
; 2.732 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.234     ; 5.720      ;
; 2.737 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.233     ; 5.716      ;
; 2.737 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.233     ; 5.716      ;
; 2.737 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.227     ; 5.722      ;
; 2.737 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.227     ; 5.722      ;
; 2.739 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.219     ; 5.728      ;
; 2.740 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|udqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.235     ; 5.711      ;
; 2.742 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.241     ; 5.703      ;
; 2.746 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.228     ; 5.712      ;
; 2.746 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.228     ; 5.712      ;
; 2.746 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.229     ; 5.711      ;
; 2.746 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.229     ; 5.711      ;
; 2.895 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.194     ; 5.561      ;
; 2.895 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.194     ; 5.561      ;
; 2.895 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.194     ; 5.561      ;
; 2.895 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.194     ; 5.561      ;
; 2.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.250     ; 5.481      ;
; 2.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.247     ; 5.484      ;
; 2.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.247     ; 5.484      ;
; 2.924 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.246     ; 5.480      ;
; 2.924 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.246     ; 5.480      ;
; 2.924 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.240     ; 5.486      ;
; 2.924 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.240     ; 5.486      ;
; 2.929 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.254     ; 5.467      ;
; 2.933 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.241     ; 5.476      ;
; 2.933 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.241     ; 5.476      ;
; 2.933 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.242     ; 5.475      ;
; 2.933 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.242     ; 5.475      ;
; 3.219 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.191     ; 5.402      ;
; 3.219 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.187     ; 5.406      ;
; 3.219 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.187     ; 5.406      ;
; 3.219 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.191     ; 5.402      ;
; 3.219 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.187     ; 5.406      ;
; 3.219 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.191     ; 5.402      ;
; 3.219 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.191     ; 5.402      ;
; 3.219 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.187     ; 5.406      ;
; 3.219 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.191     ; 5.402      ;
; 3.219 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.187     ; 5.406      ;
; 3.219 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.187     ; 5.406      ;
; 3.219 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.191     ; 5.402      ;
; 3.220 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 5.402      ;
; 3.220 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 5.402      ;
; 3.220 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 5.402      ;
; 3.220 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 5.402      ;
; 3.220 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 5.402      ;
; 3.220 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 5.402      ;
; 3.220 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 5.402      ;
; 3.220 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 5.402      ;
; 3.220 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 5.402      ;
; 3.220 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 5.402      ;
; 3.220 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 5.402      ;
; 3.220 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 5.402      ;
; 3.220 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 5.402      ;
; 3.220 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 5.402      ;
; 3.220 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 5.402      ;
; 3.220 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 5.402      ;
; 3.222 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 5.405      ;
; 3.222 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 5.405      ;
; 3.222 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 5.405      ;
; 3.222 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 5.405      ;
; 3.222 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 5.405      ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                          ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 9.344 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.093      ;
; 9.344 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.093      ;
; 9.344 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.093      ;
; 9.344 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[31]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.093      ;
; 9.344 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.093      ;
; 9.344 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[20]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.093      ;
; 9.344 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.093      ;
; 9.348 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.175     ; 8.100      ;
; 9.354 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.162     ; 8.107      ;
; 9.355 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 8.085      ;
; 9.355 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[28]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 8.085      ;
; 9.355 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[24]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 8.085      ;
; 9.355 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 8.085      ;
; 9.355 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[21]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 8.085      ;
; 9.362 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[22]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.179     ; 8.082      ;
; 9.362 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[17]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.179     ; 8.082      ;
; 9.362 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.179     ; 8.082      ;
; 9.362 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.179     ; 8.082      ;
; 9.406 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.162     ; 8.055      ;
; 9.407 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|memory_ready_reg                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.175     ; 8.041      ;
; 9.748 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[7]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.173     ; 7.702      ;
; 9.748 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[6]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.173     ; 7.702      ;
; 9.748 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[4]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.173     ; 7.702      ;
; 9.748 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[5]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.173     ; 7.702      ;
; 9.748 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[3]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.173     ; 7.702      ;
; 9.748 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[2]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.173     ; 7.702      ;
; 9.748 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[1]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.173     ; 7.702      ;
; 9.748 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[14] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 7.692      ;
; 9.748 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 7.692      ;
; 9.748 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[0]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.173     ; 7.702      ;
; 9.748 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 7.692      ;
; 9.749 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|stretch                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.172     ; 7.702      ;
; 9.755 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.229      ; 8.097      ;
; 9.755 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.229      ; 8.097      ;
; 9.755 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.229      ; 8.097      ;
; 9.755 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.229      ; 8.097      ;
; 9.756 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.mstr_ack         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.703      ;
; 9.756 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.691      ;
; 9.756 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.691      ;
; 9.756 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.691      ;
; 9.756 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.691      ;
; 9.756 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.691      ;
; 9.756 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.691      ;
; 9.756 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.691      ;
; 9.756 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.691      ;
; 9.756 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.691      ;
; 9.756 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[16] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.691      ;
; 9.756 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[15] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.691      ;
; 9.756 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.691      ;
; 9.756 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[12] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.691      ;
; 9.756 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[11] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.691      ;
; 9.756 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.stop             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.703      ;
; 9.756 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.703      ;
; 9.756 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.start            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.703      ;
; 9.756 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.703      ;
; 9.756 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|sda_int                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.703      ;
; 9.756 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.wr               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.703      ;
; 9.756 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.rd               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.703      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[1]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.702      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[2]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.702      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.slv_ack2         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.702      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[4]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.167     ; 7.699      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[5]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.167     ; 7.699      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[7]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.167     ; 7.699      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[6]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.167     ; 7.699      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[0]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.167     ; 7.699      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.167     ; 7.699      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[3]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.167     ; 7.699      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[2]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.167     ; 7.699      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[0]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.702      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.slv_ack1         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.702      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|scl_ena                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.163     ; 7.703      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|ack_error              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.163     ; 7.703      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|spi_speed_reg[7]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.181     ; 7.685      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[11]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 7.683      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[0]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 7.683      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[4]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 7.683      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[5]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 7.683      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[6]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 7.683      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[7]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.180     ; 7.686      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[8]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 7.683      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[9]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 7.683      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[10]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.180     ; 7.686      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[11]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.180     ; 7.686      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[12]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.180     ; 7.686      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[13]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.682      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[14]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.180     ; 7.686      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[15]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 7.683      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[16]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.682      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[17]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.682      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[20]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.682      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[21]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.682      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[25]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.682      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[26]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.682      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[27]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.682      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[28]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.181     ; 7.685      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[31]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.682      ;
; 9.757 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[17]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.181     ; 7.685      ;
; 9.758 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.187     ; 7.678      ;
; 9.758 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.681      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.463 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|dffe4                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.381      ; 2.034      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a63 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a62 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a61 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a60 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a59 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a58 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a57 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a56 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a35 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a34 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a33 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a32 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a31 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a29 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a28 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a27 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a26 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a25 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a24 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.339      ; 2.039      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a55 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a54 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a53 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a52 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a51 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a50 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a49 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a48 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a47 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a46 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a45 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a44 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a43 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a42 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a41 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a40 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a39 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a38 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a37 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a36 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a23 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a22 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a21 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a20 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a19 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a18 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a17 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 1.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.336      ; 2.280      ;
; 3.959 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[0]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.669      ; 4.823      ;
; 4.085 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.597      ; 4.877      ;
; 4.085 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.597      ; 4.877      ;
; 4.107 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[2]                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.579      ; 4.881      ;
; 4.117 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.562      ; 4.874      ;
; 4.117 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[7]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.562      ; 4.874      ;
; 4.117 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[0]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.562      ; 4.874      ;
; 4.117 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[3]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.562      ; 4.874      ;
; 4.117 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[2]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.562      ; 4.874      ;
; 4.117 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[1]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.562      ; 4.874      ;
; 4.125 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_dma_clock_del:antic_dma_clock1|dma_shiftreg_reg[7]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.559      ; 4.879      ;
; 4.126 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[0]                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.551      ; 4.872      ;
; 4.126 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[3]                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.551      ; 4.872      ;
; 4.133 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.544      ; 4.872      ;
; 4.139 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[1]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.553      ; 4.887      ;
; 4.139 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.553      ; 4.887      ;
; 4.139 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[2]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.553      ; 4.887      ;
; 4.140 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.552      ; 4.887      ;
; 4.140 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.552      ; 4.887      ;
; 4.140 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.552      ; 4.887      ;
; 4.140 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.552      ; 4.887      ;
; 4.140 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.552      ; 4.887      ;
; 4.141 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[3]                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.543      ; 4.879      ;
; 4.141 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[2]                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.543      ; 4.879      ;
; 4.141 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[1]                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.543      ; 4.879      ;
; 4.141 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[0]                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.543      ; 4.879      ;
; 4.141 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0]                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.543      ; 4.879      ;
; 4.141 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.551      ; 4.887      ;
; 4.141 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_freezer_reg                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.551      ; 4.887      ;
; 4.141 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.551      ; 4.887      ;
; 4.141 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[1]                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.550      ; 4.886      ;
; 4.141 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.551      ; 4.887      ;
; 4.141 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[2]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.551      ; 4.887      ;
; 4.141 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.551      ; 4.887      ;
; 4.141 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.551      ; 4.887      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                   ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 4.430 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cke_reg                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 4.815      ;
; 4.431 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 4.799      ;
; 4.431 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 4.800      ;
; 4.431 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 4.800      ;
; 4.431 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 4.804      ;
; 4.431 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 4.804      ;
; 4.431 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 4.804      ;
; 4.431 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 4.804      ;
; 4.431 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 4.804      ;
; 4.431 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 4.804      ;
; 4.431 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 4.804      ;
; 4.431 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 4.804      ;
; 4.431 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 4.804      ;
; 4.431 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 4.804      ;
; 4.431 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 4.804      ;
; 4.431 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 4.800      ;
; 4.438 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 4.793      ;
; 4.438 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 4.796      ;
; 4.438 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 4.793      ;
; 4.438 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 4.793      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 4.811      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 4.811      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 4.811      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 4.811      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 4.811      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 4.811      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 4.811      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 4.811      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 4.811      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 4.811      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 4.811      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 4.811      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 4.811      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 4.811      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 4.805      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 4.809      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 4.809      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 4.806      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 4.806      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 4.806      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 4.806      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 4.806      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 4.806      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 4.806      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 4.806      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 4.806      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 4.805      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 4.806      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 4.806      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 4.806      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 4.809      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 4.806      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 4.805      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 4.806      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 4.805      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 4.809      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 4.806      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 4.806      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 4.805      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 4.809      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 4.809      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 4.805      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 4.814      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 4.814      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 4.814      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 4.814      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 4.814      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 4.814      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 4.814      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 4.814      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 4.814      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 4.814      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 4.814      ;
; 4.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 4.814      ;
; 4.623 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 4.921      ;
; 4.623 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 4.921      ;
; 4.623 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 4.921      ;
; 4.623 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 4.921      ;
; 4.638 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.100      ; 4.886      ;
; 4.638 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.100      ; 4.886      ;
; 4.641 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.101      ; 4.890      ;
; 4.641 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.101      ; 4.890      ;
; 4.646 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 4.881      ;
; 4.652 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.096      ; 4.896      ;
; 4.652 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.096      ; 4.896      ;
; 4.653 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.102      ; 4.903      ;
; 4.653 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.102      ; 4.903      ;
; 4.659 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.091      ; 4.898      ;
; 4.660 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 4.902      ;
; 4.660 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 4.902      ;
; 4.958 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 5.253      ;
; 4.958 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 5.253      ;
; 4.958 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 5.253      ;
; 4.958 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 5.253      ;
; 4.958 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 5.249      ;
; 4.958 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 5.251      ;
; 4.958 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 5.249      ;
; 4.958 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 5.250      ;
; 4.958 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 5.252      ;
; 4.958 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 5.252      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                             ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cke_reg                      ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|reply_reg                    ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ;
; 4.205 ; 4.355        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]               ;
; 4.205 ; 4.355        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[4]                  ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[5]                  ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[7]                  ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[8]                  ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[11]                 ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[6]                  ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|udqm_reg                     ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[9]                  ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[0]                  ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[10]                 ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[1]                  ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[2]                  ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[3]                  ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                     ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 4.167 ; 4.167        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.167 ; 4.167        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|o                                                                                                                    ;
; 4.244 ; 4.370        ; 0.126          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.286 ; 4.286        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|i                                                                                                                    ;
; 4.329 ; 8.810        ; 4.481          ; Port Rate        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.330 ; 4.439        ; 0.109          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.370 ; 4.370        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.370 ; 4.370        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 4.439 ; 4.439        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.439 ; 4.439        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 4.521 ; 4.521        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|i                                                                                                                    ;
; 4.640 ; 4.640        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.640 ; 4.640        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|o                                                                                                                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                         ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0] ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1] ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2] ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3] ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4] ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]      ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]      ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]      ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]      ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]      ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]      ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]      ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]      ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]      ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]      ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]      ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]       ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]       ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]       ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]       ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]       ;
; 8.443 ; 8.825        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0] ;
; 8.443 ; 8.825        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1] ;
; 8.443 ; 8.825        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2] ;
; 8.443 ; 8.825        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3] ;
; 8.443 ; 8.825        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4] ;
; 8.443 ; 8.825        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]      ;
; 8.443 ; 8.825        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]      ;
; 8.443 ; 8.825        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]      ;
; 8.443 ; 8.825        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]      ;
; 8.443 ; 8.825        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]      ;
; 8.443 ; 8.825        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]      ;
; 8.443 ; 8.825        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]      ;
; 8.443 ; 8.825        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]      ;
; 8.443 ; 8.825        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]      ;
; 8.443 ; 8.825        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]      ;
; 8.443 ; 8.825        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]      ;
; 8.443 ; 8.825        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]       ;
; 8.443 ; 8.825        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]       ;
; 8.443 ; 8.825        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]       ;
; 8.443 ; 8.825        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]       ;
; 8.443 ; 8.825        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]       ;
; 8.447 ; 8.663        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[2]                                                     ;
; 8.447 ; 8.663        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[0]                                                                                                         ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[0]                                          ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                                          ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[7]                                          ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]                                   ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                   ;
; 8.451 ; 8.667        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|pmbase_reg[4]                                                        ;
; 8.451 ; 8.667        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22]                                   ;
; 8.451 ; 8.667        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                   ;
; 8.451 ; 8.667        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                                                           ;
; 8.451 ; 8.667        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                           ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_dma_clock_del:antic_dma_clock1|dma_shiftreg_reg[0]             ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_dma_clock_del:antic_dma_clock1|dma_shiftreg_reg[3]             ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_dma_clock_del:antic_dma_clock1|dma_shiftreg_reg[6]             ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf1_snap_reg[6]                                                     ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf1_snap_reg[7]                                                     ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf3_snap_reg[7]                                                     ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_direction_reg[4]                                                   ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_direction_reg[5]                                                   ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                        ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                                                                                        ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                                                                                        ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                                                                                        ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                                                                                        ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[0]                                          ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[1]                                          ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[1]                                          ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[2]                                          ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[0]                                     ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                                    ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                                    ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[4]                                     ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[17]                                   ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]                                    ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28]                                   ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]                                   ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]                                    ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                                    ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                                     ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                    ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39]                                   ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[7]                                    ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[1]                                                      ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[2]                                                      ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                                      ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[12]                                                                                     ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[16]                                                                                     ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_32BIT_WRITE_ENABLE_reg                                                                                              ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg                                                                                               ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                                                                                                            ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                                          ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[2]                                          ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[4]                                          ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[7]                                          ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[3]                                          ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0]                                                          ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[0]                                                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                           ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                ; Clock Edge ; Target                                                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; 16.279 ; 16.279       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.279 ; 16.279       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.282 ; 16.282       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.295 ; 16.295       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.295 ; 16.295       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.295 ; 16.295       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.295 ; 16.295       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.335 ; 16.335       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.335 ; 16.335       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.335 ; 16.335       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.335 ; 16.335       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.347 ; 16.347       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.350 ; 16.350       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.350 ; 16.350       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'clk_27'                                                                                                               ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target                                                                         ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+
; 18.274 ; 18.458       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.274 ; 18.458       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.274 ; 18.458       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.274 ; 18.458       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.274 ; 18.458       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.274 ; 18.458       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.274 ; 18.458       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.274 ; 18.458       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.274 ; 18.458       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.344 ; 18.344       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.344 ; 18.344       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 18.351 ; 18.351       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.351 ; 18.351       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.400 ; 18.400       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.407 ; 18.407       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.407 ; 18.407       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.407 ; 18.407       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.407 ; 18.407       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.407 ; 18.407       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.407 ; 18.407       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.407 ; 18.407       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.407 ; 18.407       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.407 ; 18.407       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.423 ; 18.423       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.430 ; 18.430       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.606 ; 18.606       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.613 ; 18.613       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.633 ; 18.633       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.633 ; 18.633       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.637 ; 18.637       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.684 ; 18.684       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.684 ; 18.684       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.691 ; 18.691       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.691 ; 18.691       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 33.037 ; 37.037       ; 4.000          ; Port Rate        ; clk_27 ; Rise       ; CLOCK_27[0]                                                                    ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'SPI_SCK'                                                                                                                                        ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                                                                                  ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+
; 20.401 ; 20.631       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 20.401 ; 20.631       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_we_reg       ;
; 20.401 ; 20.631       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ;
; 20.401 ; 20.631       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_we_reg       ;
; 20.403 ; 20.633       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 20.403 ; 20.633       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ;
; 20.508 ; 20.724       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|SPI_MISO~en                                                                          ;
; 20.508 ; 20.724       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|SPI_MISO~reg0                                                                        ;
; 20.508 ; 20.724       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[0]                                                                   ;
; 20.508 ; 20.724       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[1]                                                                   ;
; 20.508 ; 20.724       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[2]                                                                   ;
; 20.508 ; 20.724       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[3]                                                                   ;
; 20.508 ; 20.724       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[4]                                                                   ;
; 20.508 ; 20.724       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[5]                                                                   ;
; 20.546 ; 20.730       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_receiver_strobe_r                                                                ;
; 20.547 ; 20.731       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[0]                                                                               ;
; 20.547 ; 20.731       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[1]                                                                               ;
; 20.547 ; 20.731       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[2]                                                                               ;
; 20.547 ; 20.731       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[3]                                                                               ;
; 20.547 ; 20.731       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[0]                                                                              ;
; 20.547 ; 20.731       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[1]                                                                              ;
; 20.547 ; 20.731       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[2]                                                                              ;
; 20.547 ; 20.731       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[0]                                                                       ;
; 20.547 ; 20.731       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[1]                                                                       ;
; 20.547 ; 20.731       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[2]                                                                       ;
; 20.547 ; 20.731       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[7]                                                                       ;
; 20.548 ; 20.732       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[0]                                                                           ;
; 20.548 ; 20.732       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[1]                                                                           ;
; 20.548 ; 20.732       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[2]                                                                           ;
; 20.548 ; 20.732       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transfer_end_r                                                                   ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[0]                                                                            ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[1]                                                                            ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[2]                                                                            ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[3]                                                                            ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[4]                                                                            ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[5]                                                                            ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[6]                                                                            ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[0]                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[1]                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[2]                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[3]                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[4]                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[5]                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[6]                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[7]                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[0]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[10]                                                                                   ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[1]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[2]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[3]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[4]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[5]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[6]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[7]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[8]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[9]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[3]                                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[4]                                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[5]                                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[6]                                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[7]                                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[0]                                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[1]                                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[2]                                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[3]                                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[4]                                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|osd_enable                                                                                 ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[0]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[1]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[2]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[3]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[4]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[5]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[6]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[0]                                                          ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[10]                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[11]                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[12]                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[14]                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[15]                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[16]                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[18]                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[19]                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[20]                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[22]                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[23]                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[24]                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[26]                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[27]                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[28]                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[2]                                                          ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[30]                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[31]                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[3]                                                          ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[4]                                                          ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[6]                                                          ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[7]                                                          ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[8]                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[0]                                                                         ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[1]                                                                         ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                                                                                                        ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 40.596 ; 41.606       ; 1.010          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                 ;
; 40.713 ; 41.723       ; 1.010          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                 ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; rom_loaded                                                                                                                                                                                                    ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                         ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                         ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                         ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                         ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                         ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                         ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                         ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                         ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_reconfig_write_from_rom                                                                                                                                                      ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                      ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                          ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                          ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                    ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_init_state                                           ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                               ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                   ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                        ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                        ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                        ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                        ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                        ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                        ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                        ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                         ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                         ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                          ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[0]  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_counter_state                                        ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                         ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|tmp_seq_ena_state                                             ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|rden_a_store                                                                                ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[0]                                             ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[1]                                             ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[2]                                             ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[3]                                             ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[4]                                             ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[5]                                             ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[6]                                             ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[7]                                             ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[0]                                              ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[1]                                              ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[2]                                              ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[3]                                              ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[4]                                              ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[6]                                              ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[7]                                              ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                           ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                           ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                            ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3] ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; 4.190 ; 4.633 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 6.438 ; 6.324 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; 1.050 ; 1.427 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; 1.446 ; 1.934 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 2.636 ; 2.749 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.630 ; 2.743 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.634 ; 2.747 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.636 ; 2.749 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.636 ; 2.749 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.580 ; 2.697 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.590 ; 2.707 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.580 ; 2.697 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.580 ; 2.697 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.617 ; 2.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.617 ; 2.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.620 ; 2.733 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.620 ; 2.733 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.621 ; 2.734 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.621 ; 2.734 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.632 ; 2.745 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.632 ; 2.745 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                        ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; -2.494 ; -2.726 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 0.948  ; 0.618  ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; -0.653 ; -0.944 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; -0.121 ; -0.402 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; -1.684 ; -1.802 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; -1.737 ; -1.851 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; -1.741 ; -1.855 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; -1.742 ; -1.856 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; -1.742 ; -1.856 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; -1.684 ; -1.802 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; -1.694 ; -1.812 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; -1.684 ; -1.802 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; -1.684 ; -1.802 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; -1.724 ; -1.838 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; -1.724 ; -1.838 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; -1.726 ; -1.840 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; -1.726 ; -1.840 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; -1.727 ; -1.841 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; -1.727 ; -1.841 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; -1.738 ; -1.852 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; -1.738 ; -1.852 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                             ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 9.875  ; 9.034  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 3.319  ; 3.129  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 3.163  ; 2.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 3.164  ; 2.971  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 3.165  ; 2.972  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 3.175  ; 2.982  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 3.162  ; 2.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 3.319  ; 3.129  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 3.302  ; 3.112  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 3.307  ; 3.117  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 3.307  ; 3.117  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 3.303  ; 3.113  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 3.164  ; 2.971  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 3.310  ; 3.120  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 3.162  ; 2.969  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 3.162  ; 2.969  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 3.154  ; 2.961  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 2.450  ; 2.326  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 3.310  ; 3.120  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 3.291  ; 3.101  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 3.287  ; 3.097  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 3.147  ; 2.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 3.147  ; 2.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 3.176  ; 2.983  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 3.186  ; 2.993  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 3.176  ; 2.983  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 3.176  ; 2.983  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 3.284  ; 3.094  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 3.284  ; 3.094  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 3.302  ; 3.112  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 3.302  ; 3.112  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 3.142  ; 2.965  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 3.301  ; 3.111  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 3.310  ; 3.120  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 3.151  ; 2.974  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 3.283  ; 3.093  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 3.175  ; 2.982  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 3.163  ; 2.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 3.162  ; 2.969  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 3.175  ; 2.982  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 23.289 ; 22.823 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 22.906 ; 22.426 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 23.289 ; 22.823 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 23.037 ; 22.635 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 23.134 ; 22.753 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 22.751 ; 22.521 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 22.036 ; 21.465 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 22.473 ; 21.851 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 21.881 ; 21.428 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 22.348 ; 21.834 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 22.473 ; 21.851 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 21.568 ; 21.092 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 21.473 ; 21.117 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 18.712 ; 17.737 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 7.977  ; 7.346  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 24.364 ; 23.856 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 23.668 ; 23.257 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 24.030 ; 23.622 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 24.364 ; 23.856 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 23.846 ; 23.452 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 24.068 ; 23.311 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 23.261 ; 22.734 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 7.223  ; 6.427  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -0.884 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -1.122 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                     ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 9.689  ; 8.863  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 2.393  ; 2.207  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 2.396  ; 2.207  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 2.397  ; 2.208  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 2.398  ; 2.209  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 2.408  ; 2.219  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 2.393  ; 2.220  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 2.550  ; 2.364  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 2.534  ; 2.348  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 2.539  ; 2.353  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 2.539  ; 2.353  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 2.535  ; 2.349  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 2.397  ; 2.208  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 2.542  ; 2.356  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 2.387  ; 2.198  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 2.395  ; 2.206  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 2.387  ; 2.198  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 1.717  ; 1.593  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 2.374  ; 2.201  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.524  ; 2.338  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.520  ; 2.334  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.379  ; 2.206  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.379  ; 2.206  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.409  ; 2.220  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.419  ; 2.230  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.409  ; 2.220  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.409  ; 2.220  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.517  ; 2.331  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.517  ; 2.331  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.534  ; 2.348  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.534  ; 2.348  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.374  ; 2.201  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.533  ; 2.347  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.542  ; 2.356  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.383  ; 2.210  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 2.516  ; 2.330  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 2.408  ; 2.219  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 2.396  ; 2.207  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 2.395  ; 2.206  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 2.408  ; 2.219  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 6.211  ; 5.830  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 6.441  ; 5.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 6.211  ; 5.830  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 6.464  ; 5.895  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 6.503  ; 6.096  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 6.921  ; 6.229  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 6.535  ; 5.916  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 6.033  ; 5.534  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 6.174  ; 5.699  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 6.033  ; 5.534  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 6.596  ; 6.032  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 6.532  ; 5.976  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 6.180  ; 5.709  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 7.122  ; 6.138  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 5.779  ; 5.153  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 6.206  ; 5.842  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 6.206  ; 5.882  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 6.460  ; 6.029  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 6.507  ; 6.058  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 6.359  ; 5.965  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 6.743  ; 6.246  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 6.408  ; 5.842  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 5.613  ; 4.942  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -1.570 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -1.805 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------+
; Propagation Delay                                          ;
+------------+-------------+-------+-------+--------+--------+
; Input Port ; Output Port ; RR    ; RF    ; FR     ; FF     ;
+------------+-------------+-------+-------+--------+--------+
; CONF_DATA0 ; SPI_DO      ; 9.567 ; 9.496 ; 10.292 ; 10.292 ;
+------------+-------------+-------+-------+--------+--------+


+----------------------------------------------------------+
; Minimum Propagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 9.118 ; 8.982 ; 9.672 ; 9.672 ;
+------------+-------------+-------+-------+-------+-------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 8.832 ; 8.832 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 2.825 ; 2.761 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.832 ; 2.768 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.828 ; 2.764 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.847 ; 2.783 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.847 ; 2.783 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.872 ; 2.808 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.882 ; 2.818 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.872 ; 2.808 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.872 ; 2.808 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.825 ; 2.761 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.825 ; 2.761 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.843 ; 2.779 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.843 ; 2.779 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.842 ; 2.778 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.842 ; 2.778 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.851 ; 2.787 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.851 ; 2.787 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                     ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 8.297 ; 8.297 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 1.769 ; 1.707 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.776 ; 1.714 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.772 ; 1.710 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.790 ; 1.728 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.790 ; 1.728 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.792 ; 1.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.802 ; 1.740 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.792 ; 1.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.792 ; 1.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.769 ; 1.707 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.769 ; 1.707 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.786 ; 1.724 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.786 ; 1.724 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.785 ; 1.723 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.785 ; 1.723 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.794 ; 1.732 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.794 ; 1.732 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 8.097     ; 8.168     ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 2.766     ; 2.901     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.773     ; 2.908     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.769     ; 2.904     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.788     ; 2.923     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.788     ; 2.923     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.785     ; 2.948     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.795     ; 2.958     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.785     ; 2.948     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.785     ; 2.948     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.766     ; 2.901     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.766     ; 2.901     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.784     ; 2.919     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.784     ; 2.919     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.783     ; 2.918     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.783     ; 2.918     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.792     ; 2.927     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.792     ; 2.927     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 7.660     ; 7.796     ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 1.780     ; 1.978     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.787     ; 1.985     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.783     ; 1.981     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.801     ; 1.999     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.801     ; 1.999     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.803     ; 1.996     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.813     ; 2.006     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.803     ; 1.996     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.803     ; 1.996     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.780     ; 1.978     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.780     ; 1.978     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.797     ; 1.995     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.797     ; 1.995     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.796     ; 1.994     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.796     ; 1.994     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.805     ; 2.003     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.805     ; 2.003     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                             ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0.321  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.392  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 6.894  ; 0.000         ;
; SPI_SCK                                                               ; 18.385 ; 0.000         ;
; clk_27                                                                ; 35.701 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 39.547 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                             ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.107 ; 0.000         ;
; SPI_SCK                                                               ; 0.142 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 0.186 ; 0.000         ;
; clk_27                                                                ; 0.187 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.187 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.849 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                                          ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.668  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 13.380 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                                          ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.683 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.249 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                               ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.187  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 4.331  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.559  ; 0.000         ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 16.300 ; 0.000         ;
; clk_27                                                                ; 17.784 ; 0.000         ;
; SPI_SCK                                                               ; 20.000 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 40.631 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.321 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.958        ; -0.963     ; 0.512      ;
; 3.005 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.146      ; 2.894      ;
; 3.005 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.146      ; 2.894      ;
; 3.006 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2                 ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.147      ; 2.894      ;
; 3.006 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3                 ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.147      ; 2.894      ;
; 3.012 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.143      ; 2.884      ;
; 3.012 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.143      ; 2.884      ;
; 3.013 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.144      ; 2.884      ;
; 3.013 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.144      ; 2.884      ;
; 3.020 ; sdram_statemachine:sdram_adaptor|dq_output_reg                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.151      ; 2.884      ;
; 3.024 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1                 ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.155      ; 2.884      ;
; 3.024 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5                 ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.118      ; 2.847      ;
; 3.027 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8                 ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.148      ; 2.874      ;
; 3.027 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9                 ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.148      ; 2.874      ;
; 3.034 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4                 ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.118      ; 2.837      ;
; 3.035 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7                 ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.119      ; 2.837      ;
; 3.035 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6                 ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.119      ; 2.837      ;
; 3.701 ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                ; SDRAM_A[5]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.133      ; 2.185      ;
; 3.706 ; sdram_statemachine:sdram_adaptor|addr_reg[11]                               ; SDRAM_A[11]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.138      ; 2.185      ;
; 3.706 ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                             ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.138      ; 2.185      ;
; 3.713 ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                ; SDRAM_A[7]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.135      ; 2.175      ;
; 3.713 ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                ; SDRAM_A[8]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.135      ; 2.175      ;
; 3.713 ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                ; SDRAM_A[9]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.135      ; 2.175      ;
; 3.713 ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                             ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.135      ; 2.175      ;
; 3.713 ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                             ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.135      ; 2.175      ;
; 3.714 ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                             ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.136      ; 2.175      ;
; 3.717 ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                ; SDRAM_A[6]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.139      ; 2.175      ;
; 3.721 ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.143      ; 2.175      ;
; 3.725 ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                              ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.147      ; 2.175      ;
; 3.728 ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                              ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.140      ; 2.165      ;
; 3.728 ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                              ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.140      ; 2.165      ;
; 3.729 ; sdram_statemachine:sdram_adaptor|udqm_reg                                   ; SDRAM_DQMH                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.141      ; 2.165      ;
; 3.759 ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                              ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.110      ; 2.104      ;
; 3.769 ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                              ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.110      ; 2.094      ;
; 3.770 ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                ; SDRAM_A[3]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.111      ; 2.094      ;
; 3.770 ; sdram_statemachine:sdram_adaptor|we_n_reg                                   ; SDRAM_nWE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.111      ; 2.094      ;
; 3.770 ; sdram_statemachine:sdram_adaptor|ldqm_reg                                   ; SDRAM_DQML                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.111      ; 2.094      ;
; 3.770 ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                              ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.111      ; 2.094      ;
; 3.770 ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                              ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.111      ; 2.094      ;
; 3.777 ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                ; SDRAM_A[4]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.131      ; 2.107      ;
; 3.780 ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                ; SDRAM_A[2]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.111      ; 2.084      ;
; 3.781 ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                ; SDRAM_A[1]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.112      ; 2.084      ;
; 3.781 ; sdram_statemachine:sdram_adaptor|addr_reg[10]                               ; SDRAM_A[10]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.112      ; 2.084      ;
; 3.782 ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                ; SDRAM_A[0]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.113      ; 2.084      ;
; 3.782 ; sdram_statemachine:sdram_adaptor|cas_n_reg                                  ; SDRAM_nCAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.113      ; 2.084      ;
; 3.783 ; sdram_statemachine:sdram_adaptor|ba_reg[0]                                  ; SDRAM_BA[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.114      ; 2.084      ;
; 3.784 ; sdram_statemachine:sdram_adaptor|ras_n_reg                                  ; SDRAM_nRAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.115      ; 2.084      ;
; 3.784 ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                             ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.138      ; 2.107      ;
; 3.785 ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                              ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.139      ; 2.107      ;
; 3.785 ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                              ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.139      ; 2.107      ;
; 3.791 ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                  ; SDRAM_BA[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.112      ; 2.074      ;
; 3.792 ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                             ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.136      ; 2.097      ;
; 4.257 ; sdram_statemachine:sdram_adaptor|cke_reg                                    ; SDRAM_CKE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.100      ; 1.596      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 2.392 ; SDRAM_DQ[3]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.364     ; 0.949      ;
; 2.392 ; SDRAM_DQ[2]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.364     ; 0.949      ;
; 2.393 ; SDRAM_DQ[14]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.363     ; 0.949      ;
; 2.393 ; SDRAM_DQ[15]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.363     ; 0.949      ;
; 2.394 ; SDRAM_DQ[1]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.372     ; 0.939      ;
; 2.398 ; SDRAM_DQ[0]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.368     ; 0.939      ;
; 2.401 ; SDRAM_DQ[5]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.336     ; 0.968      ;
; 2.404 ; SDRAM_DQ[13]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.362     ; 0.939      ;
; 2.404 ; SDRAM_DQ[12]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.362     ; 0.939      ;
; 2.405 ; SDRAM_DQ[11]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.361     ; 0.939      ;
; 2.405 ; SDRAM_DQ[10]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.361     ; 0.939      ;
; 2.410 ; SDRAM_DQ[7]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.337     ; 0.958      ;
; 2.410 ; SDRAM_DQ[8]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.366     ; 0.929      ;
; 2.410 ; SDRAM_DQ[9]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.366     ; 0.929      ;
; 2.410 ; SDRAM_DQ[6]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.337     ; 0.958      ;
; 2.411 ; SDRAM_DQ[4]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.336     ; 0.958      ;
; 2.858 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.405        ; -0.962     ; 0.513      ;
; 5.394 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.073     ; 3.283      ;
; 5.424 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.073     ; 3.253      ;
; 5.453 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.073     ; 3.224      ;
; 5.461 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.070     ; 3.219      ;
; 5.509 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.073     ; 3.168      ;
; 5.554 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.077     ; 3.119      ;
; 5.570 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.073     ; 3.107      ;
; 5.585 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.051     ; 3.114      ;
; 5.594 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.051     ; 3.105      ;
; 5.597 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.073     ; 3.080      ;
; 5.623 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.051     ; 3.076      ;
; 5.628 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.072     ; 3.050      ;
; 5.636 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.077     ; 3.037      ;
; 5.640 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.077     ; 3.033      ;
; 5.641 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.070     ; 3.039      ;
; 5.669 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.077     ; 3.004      ;
; 5.676 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.070     ; 3.004      ;
; 5.700 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.051     ; 2.999      ;
; 5.712 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.963      ;
; 5.716 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.959      ;
; 5.717 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.958      ;
; 5.726 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.073     ; 2.951      ;
; 5.730 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.077     ; 2.943      ;
; 5.735 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.070     ; 2.945      ;
; 5.740 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|udqm_reg                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.069     ; 2.941      ;
; 5.744 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.076     ; 2.930      ;
; 5.746 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|udqm_reg                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.069     ; 2.935      ;
; 5.749 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.076     ; 2.925      ;
; 5.751 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.924      ;
; 5.756 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]                           ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.891      ;
; 5.757 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.077     ; 2.916      ;
; 5.761 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.051     ; 2.938      ;
; 5.768 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.051     ; 2.931      ;
; 5.768 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.907      ;
; 5.773 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.076     ; 2.901      ;
; 5.774 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.051     ; 2.925      ;
; 5.788 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.051     ; 2.911      ;
; 5.788 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.072     ; 2.890      ;
; 5.788 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.040     ; 2.922      ;
; 5.797 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.051     ; 2.902      ;
; 5.800 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.875      ;
; 5.808 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.076     ; 2.866      ;
; 5.812 ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[6]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.133     ; 2.805      ;
; 5.823 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.072     ; 2.855      ;
; 5.825 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.076     ; 2.849      ;
; 5.837 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|udqm_reg                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.069     ; 2.844      ;
; 5.851 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.070     ; 2.829      ;
; 5.852 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.070     ; 2.828      ;
; 5.857 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.076     ; 2.817      ;
; 5.858 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.073     ; 2.819      ;
; 5.861 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.050     ; 2.839      ;
; 5.861 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]                           ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 2.761      ;
; 5.864 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.811      ;
; 5.872 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.052     ; 2.826      ;
; 5.878 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.077     ; 2.795      ;
; 5.882 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.072     ; 2.796      ;
; 5.886 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.077     ; 2.787      ;
; 5.887 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]                           ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.102     ; 2.761      ;
; 5.889 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.051     ; 2.810      ;
; 5.895 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]                           ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 2.726      ;
; 5.896 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.076     ; 2.778      ;
; 5.917 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.051     ; 2.782      ;
; 5.935 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 2.741      ;
; 5.942 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 2.734      ;
; 5.945 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 2.731      ;
; 5.947 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 2.729      ;
; 5.950 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.051     ; 2.749      ;
; 5.952 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.077     ; 2.721      ;
; 5.958 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.077     ; 2.715      ;
; 5.960 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.077     ; 2.713      ;
; 5.969 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.077     ; 2.704      ;
; 5.970 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 2.706      ;
; 5.977 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.051     ; 2.722      ;
; 5.979 ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[3]                         ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.668      ;
; 5.987 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 2.689      ;
; 5.993 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.077     ; 2.680      ;
; 5.998 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.072     ; 2.680      ;
; 5.999 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.072     ; 2.679      ;
; 5.999 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|udqm_reg                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.069     ; 2.682      ;
; 6.005 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 2.671      ;
; 6.009 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]                           ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.638      ;
; 6.018 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.077     ; 2.655      ;
; 6.019 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 2.657      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                              ;
+--------+------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                              ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 6.894  ; user_io:my_user_io|ps2_clk                                                                                             ; user_io:my_user_io|ps2_kbd_tx_byte[6]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.066     ; 1.838      ;
; 6.894  ; user_io:my_user_io|ps2_clk                                                                                             ; user_io:my_user_io|ps2_kbd_tx_byte[5]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.066     ; 1.838      ;
; 6.894  ; user_io:my_user_io|ps2_clk                                                                                             ; user_io:my_user_io|ps2_kbd_tx_byte[4]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.066     ; 1.838      ;
; 6.894  ; user_io:my_user_io|ps2_clk                                                                                             ; user_io:my_user_io|ps2_kbd_tx_byte[3]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.066     ; 1.838      ;
; 6.894  ; user_io:my_user_io|ps2_clk                                                                                             ; user_io:my_user_io|ps2_kbd_tx_byte[2]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.066     ; 1.838      ;
; 6.894  ; user_io:my_user_io|ps2_clk                                                                                             ; user_io:my_user_io|ps2_kbd_tx_byte[1]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.066     ; 1.838      ;
; 6.894  ; user_io:my_user_io|ps2_clk                                                                                             ; user_io:my_user_io|ps2_kbd_tx_byte[0]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.066     ; 1.838      ;
; 6.941  ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                                                                    ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 1.772      ;
; 7.005  ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                    ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 1.708      ;
; 7.039  ; sdram_statemachine:sdram_adaptor|data_out_reg[9]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[9]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.071     ; 1.688      ;
; 7.072  ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                    ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 1.641      ;
; 7.199  ; sdram_statemachine:sdram_adaptor|data_out_reg[12]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[12]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.071     ; 1.528      ;
; 7.221  ; sdram_statemachine:sdram_adaptor|data_out_reg[15]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[15]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.071     ; 1.506      ;
; 7.223  ; sdram_statemachine:sdram_adaptor|data_out_reg[11]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[11]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.071     ; 1.504      ;
; 7.240  ; sdram_statemachine:sdram_adaptor|data_out_reg[14]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[14]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.071     ; 1.487      ;
; 7.246  ; user_io:my_user_io|ps2_clk                                                                                             ; user_io:my_user_io|ps2_kbd_tx_state[0]                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.069     ; 1.483      ;
; 7.263  ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0]                                            ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:1:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.810        ; -0.962     ; 0.513      ;
; 7.287  ; user_io:my_user_io|ps2_clk                                                                                             ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.069     ; 1.442      ;
; 7.336  ; user_io:my_user_io|ps2_clk                                                                                             ; user_io:my_user_io|ps2_kbd_parity                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.069     ; 1.393      ;
; 7.358  ; sdram_statemachine:sdram_adaptor|data_out_reg[8]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[8]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.071     ; 1.369      ;
; 7.425  ; sdram_statemachine:sdram_adaptor|data_out_reg[10]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[10]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.082     ; 1.291      ;
; 7.437  ; user_io:my_user_io|ps2_clk                                                                                             ; user_io:my_user_io|ps2_kbd_tx_state[2]                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.069     ; 1.292      ;
; 7.437  ; user_io:my_user_io|ps2_clk                                                                                             ; user_io:my_user_io|ps2_kbd_tx_state[1]                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.069     ; 1.292      ;
; 7.438  ; user_io:my_user_io|ps2_clk                                                                                             ; user_io:my_user_io|ps2_kbd_tx_state[3]                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.069     ; 1.291      ;
; 7.473  ; sdram_statemachine:sdram_adaptor|data_out_reg[23]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[23]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.086     ; 1.239      ;
; 7.484  ; sdram_statemachine:sdram_adaptor|data_out_reg[13]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[13]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.077     ; 1.237      ;
; 7.525  ; sdram_statemachine:sdram_adaptor|data_out_reg[3]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[3]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.080     ; 1.193      ;
; 7.543  ; user_io:my_user_io|ps2_clk                                                                                             ; user_io:my_user_io|ps2_kbd_r_inc                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.068     ; 1.187      ;
; 7.574  ; sdram_statemachine:sdram_adaptor|data_out_reg[2]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[2]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.083     ; 1.141      ;
; 7.597  ; sdram_statemachine:sdram_adaptor|data_out_reg[0]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[0]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; 0.118      ; 1.319      ;
; 7.646  ; user_io:my_user_io|ps2_clk                                                                                             ; user_io:my_user_io|ps2_kbd_rptr[2]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.068     ; 1.084      ;
; 7.712  ; sdram_statemachine:sdram_adaptor|data_out_reg[1]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[1]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.083     ; 1.003      ;
; 7.724  ; sdram_statemachine:sdram_adaptor|data_out_reg[6]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[6]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.083     ; 0.991      ;
; 7.725  ; sdram_statemachine:sdram_adaptor|data_out_reg[7]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[7]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.083     ; 0.990      ;
; 7.774  ; user_io:my_user_io|ps2_clk                                                                                             ; user_io:my_user_io|ps2_kbd_tx_byte[7]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.068     ; 0.956      ;
; 7.777  ; user_io:my_user_io|ps2_clk                                                                                             ; user_io:my_user_io|ps2_kbd_rptr[1]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.068     ; 0.953      ;
; 7.805  ; user_io:my_user_io|ps2_clk                                                                                             ; user_io:my_user_io|ps2_kbd_rptr[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.068     ; 0.925      ;
; 7.818  ; user_io:my_user_io|ps2_clk                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_clk|ff_reg[2]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.068     ; 0.912      ;
; 7.897  ; sdram_statemachine:sdram_adaptor|reply_reg                                                                             ; sdram_statemachine:sdram_adaptor|reply_sreg                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 0.816      ;
; 7.969  ; user_io:my_user_io|ps2_clk                                                                                             ; user_io:my_user_io|ps2_kbd.ps2_clkD                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.068     ; 0.761      ;
; 8.007  ; sdram_statemachine:sdram_adaptor|data_out_reg[5]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[5]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.084     ; 0.707      ;
; 8.033  ; sdram_statemachine:sdram_adaptor|data_out_reg[25]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[25]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.088     ; 0.677      ;
; 8.114  ; sdram_statemachine:sdram_adaptor|data_out_reg[4]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[4]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 0.599      ;
; 8.168  ; sdram_statemachine:sdram_adaptor|data_out_reg[27]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[27]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.086     ; 0.544      ;
; 8.169  ; sdram_statemachine:sdram_adaptor|data_out_reg[30]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[30]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.087     ; 0.542      ;
; 8.169  ; sdram_statemachine:sdram_adaptor|data_out_reg[22]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[22]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.087     ; 0.542      ;
; 8.169  ; sdram_statemachine:sdram_adaptor|data_out_reg[28]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[28]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.086     ; 0.543      ;
; 8.169  ; sdram_statemachine:sdram_adaptor|data_out_reg[19]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[19]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.087     ; 0.542      ;
; 8.169  ; sdram_statemachine:sdram_adaptor|data_out_reg[21]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[21]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.086     ; 0.543      ;
; 8.170  ; sdram_statemachine:sdram_adaptor|data_out_reg[17]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[17]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.087     ; 0.541      ;
; 8.170  ; sdram_statemachine:sdram_adaptor|data_out_reg[26]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[26]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.086     ; 0.542      ;
; 8.170  ; sdram_statemachine:sdram_adaptor|data_out_reg[18]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[18]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.086     ; 0.542      ;
; 8.172  ; sdram_statemachine:sdram_adaptor|data_out_reg[31]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[31]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.086     ; 0.540      ;
; 8.264  ; sdram_statemachine:sdram_adaptor|data_out_reg[29]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[29]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.083     ; 0.451      ;
; 8.272  ; sdram_statemachine:sdram_adaptor|data_out_reg[24]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[24]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.086     ; 0.440      ;
; 8.272  ; sdram_statemachine:sdram_adaptor|data_out_reg[20]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[20]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.086     ; 0.440      ;
; 8.274  ; sdram_statemachine:sdram_adaptor|data_out_reg[16]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[16]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.087     ; 0.437      ;
; 9.742  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.035     ; 7.831      ;
; 9.782  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.035     ; 7.791      ;
; 9.861  ; reset_load                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 7.699      ;
; 9.930  ; ioctl_state.IOCTL_IDLE                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.052     ; 7.626      ;
; 9.955  ; cart_type_byte[3]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.031     ; 7.622      ;
; 9.956  ; DMA_16BIT_WRITE_ENABLE_IOCTL                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.052     ; 7.600      ;
; 9.969  ; cart_type_byte[2]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.030     ; 7.609      ;
; 9.969  ; cart_type_byte[0]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.031     ; 7.608      ;
; 9.986  ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.032     ; 7.590      ;
; 9.986  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 7.571      ;
; 10.011 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.035     ; 7.562      ;
; 10.025 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[0]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.223     ; 7.360      ;
; 10.035 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.153      ; 7.726      ;
; 10.035 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.153      ; 7.726      ;
; 10.035 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.153      ; 7.726      ;
; 10.035 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.153      ; 7.726      ;
; 10.035 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.153      ; 7.726      ;
; 10.037 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 7.520      ;
; 10.042 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.220     ; 7.346      ;
; 10.046 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 7.511      ;
; 10.069 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.221     ; 7.318      ;
; 10.072 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.223     ; 7.313      ;
; 10.075 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.153      ; 7.686      ;
; 10.075 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.153      ; 7.686      ;
; 10.075 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.153      ; 7.686      ;
; 10.075 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.153      ; 7.686      ;
; 10.075 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.153      ; 7.686      ;
; 10.075 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.032     ; 7.501      ;
; 10.076 ; user_io:my_user_io|status[1]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.032     ; 7.500      ;
; 10.105 ; cart_type_byte[4]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.031     ; 7.472      ;
; 10.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.091     ; 7.400      ;
; 10.127 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[3]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.026     ; 7.455      ;
; 10.142 ; cart_type_byte[1]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.031     ; 7.435      ;
; 10.149 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.130      ; 7.589      ;
; 10.154 ; reset_load                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.140      ; 7.594      ;
; 10.154 ; reset_load                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.140      ; 7.594      ;
; 10.154 ; reset_load                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.140      ; 7.594      ;
; 10.154 ; reset_load                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.140      ; 7.594      ;
; 10.154 ; reset_load                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.140      ; 7.594      ;
; 10.170 ; cart_type_byte[5]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.032     ; 7.406      ;
; 10.170 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 7.401      ;
; 10.178 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.035     ; 7.395      ;
; 10.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.022     ; 7.407      ;
+--------+------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'SPI_SCK'                                                                                                                        ;
+--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                             ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 18.385 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.993      ;
; 18.385 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.993      ;
; 18.385 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.993      ;
; 18.385 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.993      ;
; 18.385 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.993      ;
; 18.590 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.788      ;
; 18.591 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.787      ;
; 18.591 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.787      ;
; 18.591 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.787      ;
; 18.591 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.787      ;
; 18.591 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.787      ;
; 18.707 ; user_io:my_user_io|serial_out_rptr[2] ; user_io:my_user_io|spi_byte_out[0]    ; SPI_SCK      ; SPI_SCK     ; 20.800       ; -0.602     ; 1.478      ;
; 18.712 ; user_io:my_user_io|serial_out_rptr[1] ; user_io:my_user_io|spi_byte_out[0]    ; SPI_SCK      ; SPI_SCK     ; 20.800       ; -0.602     ; 1.473      ;
; 18.712 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.666      ;
; 18.712 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.666      ;
; 18.712 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.666      ;
; 18.712 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.666      ;
; 18.712 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.666      ;
; 18.755 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.623      ;
; 18.755 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.623      ;
; 18.755 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.623      ;
; 18.755 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.623      ;
; 18.755 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.623      ;
; 18.793 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|spi_byte_out[0]    ; SPI_SCK      ; SPI_SCK     ; 20.800       ; -0.602     ; 1.392      ;
; 18.798 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.580      ;
; 18.865 ; user_io:my_user_io|serial_out_rptr[3] ; user_io:my_user_io|spi_byte_out[0]    ; SPI_SCK      ; SPI_SCK     ; 20.800       ; -0.602     ; 1.320      ;
; 18.869 ; user_io:my_user_io|serial_out_rptr[5] ; user_io:my_user_io|spi_byte_out[0]    ; SPI_SCK      ; SPI_SCK     ; 20.800       ; -0.602     ; 1.316      ;
; 18.928 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.450      ;
; 18.963 ; user_io:my_user_io|serial_out_rptr[4] ; user_io:my_user_io|spi_byte_out[0]    ; SPI_SCK      ; SPI_SCK     ; 20.800       ; -0.602     ; 1.222      ;
; 18.968 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 2.410      ;
; 19.352 ; user_io:my_user_io|cmd[0]             ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 2.020      ;
; 19.352 ; user_io:my_user_io|cmd[0]             ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 2.020      ;
; 19.352 ; user_io:my_user_io|cmd[0]             ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 2.020      ;
; 19.352 ; user_io:my_user_io|cmd[0]             ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 2.020      ;
; 19.352 ; user_io:my_user_io|cmd[0]             ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 2.020      ;
; 19.420 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.958      ;
; 19.420 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.958      ;
; 19.420 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.958      ;
; 19.420 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.958      ;
; 19.420 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.958      ;
; 19.446 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.932      ;
; 19.446 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.932      ;
; 19.446 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.932      ;
; 19.446 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.932      ;
; 19.446 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.932      ;
; 19.454 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.918      ;
; 19.454 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.918      ;
; 19.454 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.918      ;
; 19.454 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.918      ;
; 19.454 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.918      ;
; 19.456 ; user_io:my_user_io|cmd[1]             ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.916      ;
; 19.456 ; user_io:my_user_io|cmd[1]             ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.916      ;
; 19.456 ; user_io:my_user_io|cmd[1]             ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.916      ;
; 19.456 ; user_io:my_user_io|cmd[1]             ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.916      ;
; 19.456 ; user_io:my_user_io|cmd[1]             ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.916      ;
; 19.462 ; user_io:my_user_io|cmd[2]             ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.910      ;
; 19.462 ; user_io:my_user_io|cmd[2]             ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.910      ;
; 19.462 ; user_io:my_user_io|cmd[2]             ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.910      ;
; 19.462 ; user_io:my_user_io|cmd[2]             ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.910      ;
; 19.462 ; user_io:my_user_io|cmd[2]             ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.910      ;
; 19.472 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.900      ;
; 19.472 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.900      ;
; 19.472 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.900      ;
; 19.472 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.900      ;
; 19.472 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.900      ;
; 19.504 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.874      ;
; 19.504 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.874      ;
; 19.504 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.874      ;
; 19.504 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.874      ;
; 19.504 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.874      ;
; 19.528 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.844      ;
; 19.528 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.844      ;
; 19.528 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.844      ;
; 19.528 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.844      ;
; 19.528 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.844      ;
; 19.538 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.840      ;
; 19.538 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.840      ;
; 19.538 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.840      ;
; 19.538 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.840      ;
; 19.538 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.840      ;
; 19.557 ; user_io:my_user_io|cmd[0]             ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.815      ;
; 19.577 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.801      ;
; 19.577 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.801      ;
; 19.577 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.801      ;
; 19.577 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.801      ;
; 19.577 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.801      ;
; 19.617 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.761      ;
; 19.617 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.761      ;
; 19.617 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.761      ;
; 19.617 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.761      ;
; 19.617 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.761      ;
; 19.619 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.753      ;
; 19.619 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.753      ;
; 19.619 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.753      ;
; 19.619 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.753      ;
; 19.619 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.753      ;
; 19.625 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.753      ;
; 19.651 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.525      ; 1.727      ;
; 19.659 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.713      ;
; 19.661 ; user_io:my_user_io|cmd[1]             ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.519      ; 1.711      ;
+--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'clk_27'                                                                                                                                                                 ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 35.701 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.287      ;
; 35.744 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.244      ;
; 35.765 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.223      ;
; 35.766 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.222      ;
; 35.777 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.211      ;
; 35.779 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.209      ;
; 35.790 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.198      ;
; 35.811 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.177      ;
; 35.830 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.158      ;
; 35.834 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.154      ;
; 35.835 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.153      ;
; 35.843 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.145      ;
; 35.845 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.143      ;
; 35.858 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.130      ;
; 35.878 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.110      ;
; 35.881 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.107      ;
; 35.912 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.076      ;
; 35.914 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.074      ;
; 35.927 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.061      ;
; 35.995 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.993      ;
; 36.071 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.917      ;
; 36.077 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.911      ;
; 36.083 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.905      ;
; 36.093 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.895      ;
; 36.094 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.894      ;
; 36.099 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.889      ;
; 36.123 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.865      ;
; 36.131 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.857      ;
; 36.137 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.851      ;
; 36.146 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.842      ;
; 36.155 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.833      ;
; 36.158 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.830      ;
; 36.158 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.830      ;
; 36.164 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.824      ;
; 36.165 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.823      ;
; 36.169 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.819      ;
; 36.175 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.813      ;
; 36.177 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.811      ;
; 36.181 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.807      ;
; 36.197 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.791      ;
; 36.204 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.784      ;
; 36.229 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.759      ;
; 36.237 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.751      ;
; 36.237 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.751      ;
; 36.247 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.741      ;
; 36.251 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.737      ;
; 36.253 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.735      ;
; 36.256 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.732      ;
; 36.259 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.729      ;
; 36.322 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.666      ;
; 36.331 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.657      ;
; 36.333 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.655      ;
; 36.338 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.650      ;
; 36.340 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.648      ;
; 36.406 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.582      ;
; 36.415 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.573      ;
; 36.443 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.545      ;
; 36.446 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.542      ;
; 36.456 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.532      ;
; 36.629 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.359      ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 39.547 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.966      ; 4.073      ;
; 39.853 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_we_reg ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.333     ; 2.666      ;
; 40.507 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.975      ; 3.122      ;
; 40.545 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.140     ; 2.167      ;
; 40.572 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.975      ; 3.057      ;
; 40.633 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.975      ; 2.996      ;
; 40.647 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.137     ; 2.068      ;
; 40.647 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.137     ; 2.068      ;
; 40.659 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.140     ; 2.053      ;
; 40.731 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.137     ; 1.984      ;
; 40.738 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.140     ; 1.974      ;
; 40.791 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.137     ; 1.924      ;
; 40.812 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.140     ; 1.900      ;
; 40.904 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.137     ; 1.811      ;
; 41.046 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.140     ; 1.666      ;
; 41.197 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate3_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.017     ; 0.439      ;
; 41.336 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.145     ; 1.371      ;
; 41.504 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                             ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.146     ; 1.202      ;
; 78.949 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.021     ; 5.549      ;
; 79.666 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.046     ; 3.608      ;
; 79.675 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.046     ; 3.599      ;
; 80.747 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 2.536      ;
; 80.753 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 2.530      ;
; 80.812 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 2.471      ;
; 80.818 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 2.465      ;
; 80.873 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 2.410      ;
; 80.879 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 2.404      ;
; 80.934 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.149      ; 2.557      ;
; 81.017 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 1.966      ; 4.269      ;
; 81.035 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.149      ; 2.456      ;
; 81.063 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                                                 ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.151      ; 2.430      ;
; 81.063 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                                                 ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.151      ; 2.430      ;
; 81.209 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.039     ; 2.072      ;
; 81.277 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                                                ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.207      ;
; 81.277 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                                                ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.207      ;
; 81.353 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.028     ; 1.939      ;
; 81.384 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.028     ; 1.908      ;
; 81.384 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.028     ; 1.908      ;
; 81.384 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.028     ; 1.908      ;
; 81.384 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.028     ; 1.908      ;
; 81.384 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.028     ; 1.908      ;
; 81.384 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.028     ; 1.908      ;
; 81.384 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.028     ; 1.908      ;
; 81.384 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.028     ; 1.908      ;
; 81.399 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.033     ; 1.888      ;
; 81.399 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.033     ; 1.888      ;
; 81.399 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.033     ; 1.888      ;
; 81.399 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.033     ; 1.888      ;
; 81.399 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.033     ; 1.888      ;
; 81.403 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.035     ; 1.882      ;
; 81.403 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.035     ; 1.882      ;
; 81.403 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.035     ; 1.882      ;
; 81.403 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.035     ; 1.882      ;
; 81.403 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.035     ; 1.882      ;
; 81.403 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.035     ; 1.882      ;
; 81.403 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.035     ; 1.882      ;
; 81.403 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.035     ; 1.882      ;
; 81.418 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.040     ; 1.862      ;
; 81.418 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.040     ; 1.862      ;
; 81.418 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.040     ; 1.862      ;
; 81.418 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.040     ; 1.862      ;
; 81.418 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.040     ; 1.862      ;
; 81.428 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.148      ; 2.062      ;
; 81.428 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.148      ; 2.062      ;
; 81.469 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.046     ; 1.805      ;
; 81.472 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_last_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.012      ;
; 81.478 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.028     ; 1.814      ;
; 81.506 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.028     ; 1.786      ;
; 81.511 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_datain_reg0  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.152      ; 1.983      ;
; 81.512 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.028     ; 1.780      ;
; 81.516 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.028     ; 1.776      ;
; 81.521 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.028     ; 1.771      ;
; 81.525 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.143      ; 1.960      ;
; 81.525 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.143      ; 1.960      ;
; 81.528 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.047     ; 1.745      ;
; 81.528 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.047     ; 1.745      ;
; 81.528 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.047     ; 1.745      ;
; 81.528 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.047     ; 1.745      ;
; 81.528 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.047     ; 1.745      ;
; 81.528 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.047     ; 1.745      ;
; 81.528 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.047     ; 1.745      ;
; 81.528 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.047     ; 1.745      ;
; 81.531 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.028     ; 1.761      ;
; 81.544 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.046     ; 1.730      ;
; 81.554 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.028     ; 1.738      ;
; 81.554 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.028     ; 1.738      ;
; 81.555 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.027     ; 1.738      ;
; 81.569 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.033     ; 1.718      ;
; 81.569 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.033     ; 1.718      ;
; 81.569 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.033     ; 1.718      ;
; 81.569 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.033     ; 1.718      ;
; 81.569 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.033     ; 1.718      ;
; 81.589 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.151      ; 1.904      ;
; 81.589 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.151      ; 1.904      ;
; 81.608 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.143      ; 1.877      ;
; 81.608 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.143      ; 1.877      ;
; 81.612 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_datain_reg0  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.152      ; 1.882      ;
; 81.614 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                                                 ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|rden_a_store                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.029     ; 1.677      ;
; 81.616 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.046     ; 1.658      ;
; 81.618 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.029     ; 1.673      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                     ; To Node                                                                                                                                                                                                                                 ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.107 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[7]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.432      ;
; 0.109 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.434      ;
; 0.140 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.468      ;
; 0.140 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.466      ;
; 0.141 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.469      ;
; 0.143 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[5]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.471      ;
; 0.143 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.469      ;
; 0.144 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[2]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.472      ;
; 0.145 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[5]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.471      ;
; 0.146 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[5]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.474      ;
; 0.147 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[7]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.473      ;
; 0.149 ; user_io:my_user_io|sd_buff_addr[1]                                                                                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.475      ;
; 0.149 ; user_io:my_user_io|sd_dout[3]                                                                                                                                                                                 ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.474      ;
; 0.149 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.477      ;
; 0.150 ; zpu_secbuf_d[2]                                                                                                                                                                                               ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.479      ;
; 0.150 ; user_io:my_user_io|sd_dout[2]                                                                                                                                                                                 ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.475      ;
; 0.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1]                                                                                                              ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.475      ;
; 0.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.476      ;
; 0.152 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.478      ;
; 0.153 ; user_io:my_user_io|sd_buff_addr[2]                                                                                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.479      ;
; 0.153 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[7]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.482      ;
; 0.155 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[2]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.483      ;
; 0.155 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe3a[0]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~portb_address_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.484      ;
; 0.157 ; user_io:my_user_io|sd_buff_addr[0]                                                                                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.483      ;
; 0.157 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2]                                                                                                              ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.482      ;
; 0.161 ; zpu_secbuf_addr[2]                                                                                                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.489      ;
; 0.163 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.489      ;
; 0.164 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[2]                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.489      ;
; 0.165 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[2]                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.488      ;
; 0.166 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.494      ;
; 0.167 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe3a[0]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~portb_address_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.227      ; 0.498      ;
; 0.168 ; user_io:my_user_io|sd_buff_addr[6]                                                                                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.494      ;
; 0.173 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[5]                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.498      ;
; 0.174 ; sdram_statemachine:sdram_adaptor|data_out_reg[29]                                                                                                                                                             ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[29]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.102      ; 0.381      ;
; 0.174 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[5]                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.497      ;
; 0.175 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.226      ; 0.505      ;
; 0.179 ; user_io:my_user_io|sd_buff_addr[8]                                                                                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.505      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[3]                                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[3]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[2]                                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[2]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[1]                                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[1]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[0]                                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[0]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[6]                                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[6]                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_freezer_reg                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_freezer_reg                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqa_reg[1]                                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqa_reg[1]                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[4]                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[3]                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|cntr_tnf:cntr1|counter_reg_bit[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_address_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.506      ;
; 0.180 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 0.307      ;
; 0.180 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 0.307      ;
; 0.180 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 0.307      ;
; 0.180 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 0.307      ;
; 0.180 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 0.307      ;
; 0.181 ; user_io:my_user_io|sd_buff_addr[7]                                                                                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.507      ;
; 0.182 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|cntr_tnf:cntr1|counter_reg_bit[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_address_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.511      ;
; 0.183 ; sdram_statemachine:sdram_adaptor|data_out_reg[16]                                                                                                                                                             ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[16]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 0.386      ;
; 0.184 ; user_io:my_user_io|ps2_clk                                                                                                                                                                                    ; user_io:my_user_io|ps2_clk                                                                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 0.307      ;
; 0.185 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[4]                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.510      ;
; 0.186 ; sdram_statemachine:sdram_adaptor|data_out_reg[24]                                                                                                                                                             ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[24]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 0.389      ;
; 0.186 ; sdram_statemachine:sdram_adaptor|data_out_reg[20]                                                                                                                                                             ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[20]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 0.389      ;
; 0.186 ; user_io:my_user_io|ps2_kbd_wptr[0]                                                                                                                                                                            ; user_io:my_user_io|ps2_kbd_wptr[0]                                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; user_io:my_user_io|ps2_kbd_wptr[1]                                                                                                                                                                            ; user_io:my_user_io|ps2_kbd_wptr[1]                                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; user_io:my_user_io|ps2_kbd_wptr[2]                                                                                                                                                                            ; user_io:my_user_io|ps2_kbd_wptr[2]                                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[1]                                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[1]                                                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[82]                                                                                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[82]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[52]                                                                                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[52]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[369]                                                                                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[369]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[364]                                                                                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[364]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[50]                                                                                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[50]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[91]                                                                                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[91]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[34]                                                                                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[34]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                                                                                 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[5]                                                                                                                                                                 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[5]                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|state_reg[0]                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|state_reg[0]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|state_reg[1]                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|state_reg[1]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[18]                                                                                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[18]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[276]                                                                                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[276]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[20]                                                                                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[20]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[14]                                                                                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[14]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[119]                                                                                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[119]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|full_dff                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|full_dff                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[2]                                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[2]                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[0]                                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[0]                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[1]                                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[1]                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[3]                                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[3]                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|usedw_is_0_dff                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|usedw_is_0_dff                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|low_addressa[7]                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|low_addressa[7]                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|low_addressa[6]                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|low_addressa[6]                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|low_addressa[5]                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|low_addressa[5]                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|low_addressa[4]                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|low_addressa[4]                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'SPI_SCK'                                                                                                                                                                                               ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                  ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.142 ; osd:osd_inst|sbuf[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.224      ; 0.470      ;
; 0.143 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.224      ; 0.471      ;
; 0.144 ; osd:osd_inst|sbuf[2]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.224      ; 0.472      ;
; 0.151 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.224      ; 0.479      ;
; 0.151 ; osd:osd_inst|sbuf[0]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.224      ; 0.479      ;
; 0.156 ; osd:osd_inst|sbuf[6]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.224      ; 0.484      ;
; 0.157 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.222      ; 0.483      ;
; 0.159 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.224      ; 0.487      ;
; 0.160 ; osd:osd_inst|bcnt[0]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.222      ; 0.486      ;
; 0.163 ; osd:osd_inst|bcnt[3]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.223      ; 0.490      ;
; 0.168 ; osd:osd_inst|bcnt[5]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.223      ; 0.495      ;
; 0.171 ; osd:osd_inst|bcnt[10]                      ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.222      ; 0.497      ;
; 0.172 ; osd:osd_inst|bcnt[8]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.223      ; 0.499      ;
; 0.174 ; osd:osd_inst|bcnt[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.222      ; 0.500      ;
; 0.186 ; osd:osd_inst|osd_enable                    ; osd:osd_inst|osd_enable                                                                                 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; user_io:my_user_io|byte_cnt[0]             ; user_io:my_user_io|byte_cnt[0]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; user_io:my_user_io|cmd[3]                  ; user_io:my_user_io|cmd[3]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; user_io:my_user_io|cmd[0]                  ; user_io:my_user_io|cmd[0]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; user_io:my_user_io|cmd[1]                  ; user_io:my_user_io|cmd[1]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; user_io:my_user_io|cmd[2]                  ; user_io:my_user_io|cmd[2]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; user_io:my_user_io|serial_out_rptr[0]      ; user_io:my_user_io|serial_out_rptr[0]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.307      ;
; 0.187 ; data_io:mist_data_io|bit_cnt[1]            ; data_io:mist_data_io|bit_cnt[1]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; data_io:mist_data_io|bit_cnt[2]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|bit_cnt[1]              ; user_io:my_user_io|bit_cnt[1]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|bit_cnt[2]              ; user_io:my_user_io|bit_cnt[2]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|cmd[6]                  ; user_io:my_user_io|cmd[6]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|cmd[7]                  ; user_io:my_user_io|cmd[7]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.307      ;
; 0.193 ; data_io:mist_data_io|sbuf[6]               ; data_io:mist_data_io|spi_byte_in[7]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.314      ;
; 0.194 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[0]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; data_io:mist_data_io|spi_receiver_strobe_r ; data_io:mist_data_io|spi_receiver_strobe_r                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; user_io:my_user_io|bit_cnt[0]              ; user_io:my_user_io|bit_cnt[0]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; user_io:my_user_io|spi_receiver_strobe_r   ; user_io:my_user_io|spi_receiver_strobe_r                                                                ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.314      ;
; 0.196 ; data_io:mist_data_io|sbuf[2]               ; data_io:mist_data_io|sbuf[3]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.317      ;
; 0.196 ; data_io:mist_data_io|sbuf[3]               ; data_io:mist_data_io|sbuf[4]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.317      ;
; 0.196 ; data_io:mist_data_io|sbuf[3]               ; data_io:mist_data_io|spi_byte_in[4]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.317      ;
; 0.196 ; data_io:mist_data_io|sbuf[4]               ; data_io:mist_data_io|spi_byte_in[5]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.317      ;
; 0.196 ; data_io:mist_data_io|sbuf[1]               ; data_io:mist_data_io|spi_byte_in[2]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.317      ;
; 0.197 ; data_io:mist_data_io|sbuf[0]               ; data_io:mist_data_io|sbuf[1]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.318      ;
; 0.197 ; data_io:mist_data_io|sbuf[1]               ; data_io:mist_data_io|sbuf[2]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.318      ;
; 0.197 ; data_io:mist_data_io|sbuf[4]               ; data_io:mist_data_io|sbuf[5]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.318      ;
; 0.197 ; user_io:my_user_io|serial_out_rptr[5]      ; user_io:my_user_io|serial_out_rptr[5]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.318      ;
; 0.198 ; data_io:mist_data_io|sbuf[0]               ; data_io:mist_data_io|spi_byte_in[1]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.319      ;
; 0.199 ; data_io:mist_data_io|sbuf[2]               ; data_io:mist_data_io|spi_byte_in[3]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.320      ;
; 0.201 ; osd:osd_inst|cnt[4]                        ; osd:osd_inst|cnt[4]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.321      ;
; 0.202 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|sbuf[6]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.322      ;
; 0.202 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|spi_byte_in[6]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.322      ;
; 0.202 ; user_io:my_user_io|sbuf[4]                 ; user_io:my_user_io|spi_byte_in[5]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.322      ;
; 0.204 ; user_io:my_user_io|sbuf[4]                 ; user_io:my_user_io|sbuf[5]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.324      ;
; 0.205 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[1]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.325      ;
; 0.211 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.331      ;
; 0.212 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|sbuf[4]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.333      ;
; 0.212 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|cmd[4]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.333      ;
; 0.220 ; user_io:my_user_io|bit_cnt[1]              ; user_io:my_user_io|bit_cnt[2]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.340      ;
; 0.251 ; osd:osd_inst|bcnt[3]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.222      ; 0.577      ;
; 0.269 ; data_io:mist_data_io|sbuf[5]               ; data_io:mist_data_io|spi_byte_in[6]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.390      ;
; 0.271 ; data_io:mist_data_io|sbuf[5]               ; data_io:mist_data_io|sbuf[6]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.392      ;
; 0.276 ; user_io:my_user_io|sbuf[3]                 ; user_io:my_user_io|spi_byte_in[4]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.396      ;
; 0.278 ; user_io:my_user_io|sbuf[3]                 ; user_io:my_user_io|sbuf[4]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.398      ;
; 0.280 ; user_io:my_user_io|sbuf[0]                 ; user_io:my_user_io|spi_byte_in[1]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.401      ;
; 0.282 ; user_io:my_user_io|sbuf[0]                 ; user_io:my_user_io|sbuf[1]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.403      ;
; 0.285 ; osd:osd_inst|bcnt[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.223      ; 0.612      ;
; 0.286 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|sbuf[6]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.407      ;
; 0.286 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|cmd[6]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.407      ;
; 0.287 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|cmd[5]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.408      ;
; 0.288 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|sbuf[5]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.409      ;
; 0.294 ; osd:osd_inst|bcnt[2]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.223      ; 0.621      ;
; 0.296 ; osd:osd_inst|bcnt[6]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.222      ; 0.622      ;
; 0.298 ; user_io:my_user_io|serial_out_rptr[2]      ; user_io:my_user_io|serial_out_rptr[2]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.419      ;
; 0.298 ; user_io:my_user_io|serial_out_rptr[3]      ; user_io:my_user_io|serial_out_rptr[3]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.419      ;
; 0.299 ; user_io:my_user_io|serial_out_rptr[4]      ; user_io:my_user_io|serial_out_rptr[4]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.420      ;
; 0.303 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|cmd[6]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.423      ;
; 0.304 ; osd:osd_inst|cnt[2]                        ; osd:osd_inst|cnt[2]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.424      ;
; 0.305 ; osd:osd_inst|cnt[1]                        ; osd:osd_inst|cnt[1]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.425      ;
; 0.305 ; osd:osd_inst|bcnt[5]                       ; osd:osd_inst|bcnt[5]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.425      ;
; 0.305 ; user_io:my_user_io|sbuf[1]                 ; user_io:my_user_io|cmd[2]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.426      ;
; 0.305 ; user_io:my_user_io|serial_out_rptr[1]      ; user_io:my_user_io|serial_out_rptr[1]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.426      ;
; 0.306 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|bcnt[1]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; osd:osd_inst|bcnt[2]                       ; osd:osd_inst|bcnt[2]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; osd:osd_inst|bcnt[4]                       ; osd:osd_inst|bcnt[4]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; osd:osd_inst|bcnt[7]                       ; osd:osd_inst|bcnt[7]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; user_io:my_user_io|byte_cnt[2]             ; user_io:my_user_io|byte_cnt[2]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.427      ;
; 0.306 ; user_io:my_user_io|sbuf[0]                 ; user_io:my_user_io|cmd[1]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.427      ;
; 0.307 ; osd:osd_inst|bcnt[3]                       ; osd:osd_inst|bcnt[3]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.427      ;
; 0.307 ; osd:osd_inst|bcnt[6]                       ; osd:osd_inst|bcnt[6]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.427      ;
; 0.307 ; osd:osd_inst|bcnt[9]                       ; osd:osd_inst|bcnt[9]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.427      ;
; 0.307 ; osd:osd_inst|bcnt[10]                      ; osd:osd_inst|bcnt[10]                                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.427      ;
; 0.307 ; user_io:my_user_io|sbuf[6]                 ; user_io:my_user_io|cmd[7]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.427      ;
; 0.307 ; user_io:my_user_io|serial_out_rptr[0]      ; user_io:my_user_io|serial_out_rptr[1]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.428      ;
; 0.308 ; data_io:mist_data_io|bit_cnt[1]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.428      ;
; 0.308 ; osd:osd_inst|bcnt[8]                       ; osd:osd_inst|bcnt[8]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.428      ;
; 0.308 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.223      ; 0.635      ;
; 0.309 ; user_io:my_user_io|byte_cnt[3]             ; user_io:my_user_io|byte_cnt[3]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.430      ;
; 0.309 ; user_io:my_user_io|byte_cnt[4]             ; user_io:my_user_io|byte_cnt[4]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.430      ;
; 0.310 ; osd:osd_inst|cnt[3]                        ; osd:osd_inst|cnt[3]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.430      ;
; 0.310 ; user_io:my_user_io|byte_cnt[6]             ; user_io:my_user_io|byte_cnt[6]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.431      ;
; 0.310 ; user_io:my_user_io|byte_cnt[8]             ; user_io:my_user_io|byte_cnt[8]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.431      ;
; 0.311 ; user_io:my_user_io|byte_cnt[5]             ; user_io:my_user_io|byte_cnt[5]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.432      ;
; 0.313 ; user_io:my_user_io|sbuf[2]                 ; user_io:my_user_io|cmd[3]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.434      ;
; 0.314 ; osd:osd_inst|cnt[0]                        ; osd:osd_inst|cnt[0]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.434      ;
; 0.317 ; osd:osd_inst|bcnt[0]                       ; osd:osd_inst|bcnt[0]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.437      ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                     ; To Node                                                                                                                                                                                                       ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.186 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; rom_loaded                                                                                                                                                                                                    ; rom_loaded                                                                                                                                                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.193 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.314      ;
; 0.196 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.317      ;
; 0.197 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.317      ;
; 0.197 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.317      ;
; 0.198 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.318      ;
; 0.201 ; rom_loaded                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.321      ;
; 0.205 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.325      ;
; 0.210 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.330      ;
; 0.217 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.337      ;
; 0.221 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                              ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.547      ;
; 0.234 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.354      ;
; 0.235 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.355      ;
; 0.235 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.355      ;
; 0.236 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.356      ;
; 0.257 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.377      ;
; 0.258 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.378      ;
; 0.259 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|tmp_seq_ena_state                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.379      ;
; 0.264 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.384      ;
; 0.265 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[1]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[1]                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.386      ;
; 0.266 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[2]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[2]                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.387      ;
; 0.267 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                          ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[7]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[7]                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.388      ;
; 0.267 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[6]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[6]                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.388      ;
; 0.267 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[3]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[3]                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.388      ;
; 0.268 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_counter_state                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.388      ;
; 0.268 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[0]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[0]                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.388      ;
; 0.279 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.400      ;
; 0.292 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.412      ;
; 0.292 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.412      ;
; 0.293 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.293 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.294 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.295 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.296 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.297 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.418      ;
; 0.298 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.298 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.298 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.299 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.420      ;
; 0.299 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.420      ;
; 0.299 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.300 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.421      ;
; 0.301 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.421      ;
; 0.305 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.425      ;
; 0.305 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.425      ;
; 0.305 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.425      ;
; 0.306 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.307 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.427      ;
; 0.307 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.428      ;
; 0.307 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.427      ;
; 0.307 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.427      ;
; 0.307 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.427      ;
; 0.308 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.428      ;
; 0.309 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.429      ;
; 0.310 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.430      ;
; 0.310 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.430      ;
; 0.311 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.431      ;
; 0.311 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.431      ;
; 0.311 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.432      ;
; 0.311 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.432      ;
; 0.312 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.432      ;
; 0.315 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.435      ;
; 0.317 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.437      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'clk_27'                                                                                                                                                                 ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.307      ;
; 0.299 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.419      ;
; 0.300 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.420      ;
; 0.367 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.487      ;
; 0.369 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.489      ;
; 0.374 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.494      ;
; 0.375 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.495      ;
; 0.375 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.495      ;
; 0.376 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.496      ;
; 0.426 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.546      ;
; 0.428 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.548      ;
; 0.432 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.552      ;
; 0.433 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.553      ;
; 0.434 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.554      ;
; 0.434 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.554      ;
; 0.435 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.555      ;
; 0.439 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.559      ;
; 0.439 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.559      ;
; 0.448 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.568      ;
; 0.457 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.577      ;
; 0.459 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.579      ;
; 0.460 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.580      ;
; 0.492 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.612      ;
; 0.496 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.616      ;
; 0.499 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.619      ;
; 0.499 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.619      ;
; 0.502 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.622      ;
; 0.503 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.623      ;
; 0.503 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.623      ;
; 0.503 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.623      ;
; 0.504 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.624      ;
; 0.505 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.625      ;
; 0.509 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.629      ;
; 0.510 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.630      ;
; 0.510 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.630      ;
; 0.510 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.630      ;
; 0.510 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.630      ;
; 0.511 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.631      ;
; 0.511 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.631      ;
; 0.511 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.631      ;
; 0.511 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.631      ;
; 0.512 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.632      ;
; 0.513 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.633      ;
; 0.525 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.645      ;
; 0.528 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.648      ;
; 0.556 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.676      ;
; 0.563 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.683      ;
; 0.563 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.683      ;
; 0.566 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.686      ;
; 0.569 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.689      ;
; 0.573 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.693      ;
; 0.573 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.693      ;
; 0.576 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.696      ;
; 0.576 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.696      ;
; 0.630 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.750      ;
; 0.633 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.753      ;
; 0.637 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.757      ;
; 0.637 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.757      ;
; 0.640 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.760      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                             ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                     ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.187 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.194 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.203 ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.324      ;
; 0.205 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.325      ;
; 0.293 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.414      ;
; 0.294 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.294 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.294 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.294 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.294 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.295 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.416      ;
; 0.298 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.299 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.300 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.301 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.421      ;
; 0.302 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.422      ;
; 0.303 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.423      ;
; 0.303 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.423      ;
; 0.304 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.424      ;
; 0.304 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.424      ;
; 0.305 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.425      ;
; 0.305 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.425      ;
; 0.306 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.307 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.427      ;
; 0.307 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.427      ;
; 0.307 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.427      ;
; 0.308 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.428      ;
; 0.309 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.430      ;
; 0.309 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.430      ;
; 0.310 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.431      ;
; 0.314 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.434      ;
; 0.320 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.441      ;
; 0.321 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.442      ;
; 0.337 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.458      ;
; 0.366 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.486      ;
; 0.382 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.502      ;
; 0.398 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.518      ;
; 0.443 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.564      ;
; 0.443 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.564      ;
; 0.443 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.564      ;
; 0.447 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.567      ;
; 0.448 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.568      ;
; 0.448 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.568      ;
; 0.448 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.568      ;
; 0.450 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.570      ;
; 0.451 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.572      ;
; 0.452 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.573      ;
; 0.452 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.573      ;
; 0.452 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.572      ;
; 0.453 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.574      ;
; 0.453 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.573      ;
; 0.453 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.573      ;
; 0.455 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.576      ;
; 0.455 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.576      ;
; 0.456 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.576      ;
; 0.456 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.576      ;
; 0.456 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.576      ;
; 0.456 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.577      ;
; 0.457 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.577      ;
; 0.458 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.579      ;
; 0.458 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.578      ;
; 0.458 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.579      ;
; 0.459 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.579      ;
; 0.459 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.579      ;
; 0.459 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.580      ;
; 0.459 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.579      ;
; 0.460 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.580      ;
; 0.461 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.581      ;
; 0.461 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.581      ;
; 0.462 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.582      ;
; 0.462 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.582      ;
; 0.462 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.582      ;
; 0.463 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.583      ;
; 0.464 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.584      ;
; 0.464 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.584      ;
; 0.465 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.585      ;
; 0.465 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.585      ;
; 0.466 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.586      ;
; 0.466 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.586      ;
; 0.467 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.587      ;
; 0.469 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.589      ;
; 0.474 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.594      ;
; 0.478 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.599      ;
; 0.479 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.600      ;
; 0.481 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.602      ;
; 0.482 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.603      ;
; 0.484 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.605      ;
; 0.487 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.608      ;
; 0.496 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.032      ; 0.612      ;
; 0.498 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.032      ; 0.614      ;
; 0.500 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.032      ; 0.616      ;
; 0.506 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.627      ;
; 0.506 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.627      ;
; 0.506 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.627      ;
; 0.509 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.630      ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.849 ; sdram_statemachine:sdram_adaptor|cke_reg                                    ; SDRAM_CKE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.269      ; 1.581      ;
; 2.081 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8                 ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.321      ; 1.865      ;
; 2.081 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9                 ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.321      ; 1.865      ;
; 2.085 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1                 ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.327      ; 1.875      ;
; 2.089 ; sdram_statemachine:sdram_adaptor|dq_output_reg                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.323      ; 1.875      ;
; 2.095 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.317      ; 1.875      ;
; 2.095 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.317      ; 1.875      ;
; 2.096 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.316      ; 1.875      ;
; 2.096 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.316      ; 1.875      ;
; 2.103 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2                 ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.319      ; 1.885      ;
; 2.103 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7                 ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.292      ; 1.858      ;
; 2.103 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6                 ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.292      ; 1.858      ;
; 2.103 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3                 ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.319      ; 1.885      ;
; 2.104 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.318      ; 1.885      ;
; 2.104 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.318      ; 1.885      ;
; 2.104 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4                 ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.291      ; 1.858      ;
; 2.114 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5                 ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.291      ; 1.868      ;
; 2.181 ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                  ; SDRAM_BA[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.285      ; 1.929      ;
; 2.185 ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                             ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.308      ; 1.956      ;
; 2.189 ; sdram_statemachine:sdram_adaptor|ras_n_reg                                  ; SDRAM_nRAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.287      ; 1.939      ;
; 2.190 ; sdram_statemachine:sdram_adaptor|ba_reg[0]                                  ; SDRAM_BA[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.286      ; 1.939      ;
; 2.190 ; sdram_statemachine:sdram_adaptor|cas_n_reg                                  ; SDRAM_nCAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.286      ; 1.939      ;
; 2.191 ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                ; SDRAM_A[0]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.285      ; 1.939      ;
; 2.191 ; sdram_statemachine:sdram_adaptor|addr_reg[10]                               ; SDRAM_A[10]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.285      ; 1.939      ;
; 2.192 ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                ; SDRAM_A[1]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.284      ; 1.939      ;
; 2.192 ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                ; SDRAM_A[2]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.284      ; 1.939      ;
; 2.193 ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                              ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.310      ; 1.966      ;
; 2.193 ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                              ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.310      ; 1.966      ;
; 2.194 ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                             ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.309      ; 1.966      ;
; 2.200 ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                ; SDRAM_A[4]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.303      ; 1.966      ;
; 2.203 ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                ; SDRAM_A[3]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.283      ; 1.949      ;
; 2.203 ; sdram_statemachine:sdram_adaptor|we_n_reg                                   ; SDRAM_nWE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.283      ; 1.949      ;
; 2.203 ; sdram_statemachine:sdram_adaptor|ldqm_reg                                   ; SDRAM_DQML                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.283      ; 1.949      ;
; 2.203 ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                              ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.283      ; 1.949      ;
; 2.203 ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                              ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.283      ; 1.949      ;
; 2.204 ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                              ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.282      ; 1.949      ;
; 2.214 ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                              ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.282      ; 1.959      ;
; 2.230 ; sdram_statemachine:sdram_adaptor|udqm_reg                                   ; SDRAM_DQMH                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.312      ; 2.005      ;
; 2.230 ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                              ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.312      ; 2.005      ;
; 2.230 ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                              ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.312      ; 2.005      ;
; 2.234 ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                              ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.318      ; 2.015      ;
; 2.238 ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.314      ; 2.015      ;
; 2.242 ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                ; SDRAM_A[6]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.310      ; 2.015      ;
; 2.244 ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                             ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.308      ; 2.015      ;
; 2.245 ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                ; SDRAM_A[9]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.307      ; 2.015      ;
; 2.245 ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                             ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.307      ; 2.015      ;
; 2.245 ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                             ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.307      ; 2.015      ;
; 2.246 ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                ; SDRAM_A[7]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.306      ; 2.015      ;
; 2.246 ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                ; SDRAM_A[8]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.306      ; 2.015      ;
; 2.252 ; sdram_statemachine:sdram_adaptor|addr_reg[11]                               ; SDRAM_A[11]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.310      ; 2.025      ;
; 2.253 ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                             ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.309      ; 2.025      ;
; 2.257 ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                ; SDRAM_A[5]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.305      ; 2.025      ;
; 7.982 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -6.853       ; -0.825     ; 0.471      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                 ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                      ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 5.668 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.133     ; 2.949      ;
; 5.675 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 2.947      ;
; 5.676 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.135     ; 2.939      ;
; 5.676 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.135     ; 2.939      ;
; 5.676 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 2.944      ;
; 5.676 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.133     ; 2.941      ;
; 5.677 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 2.936      ;
; 5.678 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.189     ; 2.881      ;
; 5.678 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.189     ; 2.881      ;
; 5.679 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.191     ; 2.878      ;
; 5.682 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 2.939      ;
; 5.682 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 2.939      ;
; 5.683 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.133     ; 2.934      ;
; 5.683 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.133     ; 2.934      ;
; 5.683 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 2.937      ;
; 5.683 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 2.937      ;
; 5.683 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.126     ; 2.941      ;
; 5.685 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.184     ; 2.879      ;
; 5.685 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.187     ; 2.876      ;
; 5.685 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.184     ; 2.879      ;
; 5.685 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.187     ; 2.876      ;
; 5.686 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 2.923      ;
; 5.686 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|udqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.135     ; 2.929      ;
; 5.688 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 2.865      ;
; 5.692 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 2.927      ;
; 5.692 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 2.927      ;
; 5.692 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 2.926      ;
; 5.692 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 2.926      ;
; 5.694 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.186     ; 2.868      ;
; 5.694 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 2.869      ;
; 5.694 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 2.869      ;
; 5.694 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.186     ; 2.868      ;
; 5.704 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 2.939      ;
; 5.705 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 2.940      ;
; 5.705 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 2.940      ;
; 5.705 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 2.939      ;
; 5.705 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 2.939      ;
; 5.705 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.109     ; 2.936      ;
; 5.705 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 2.937      ;
; 5.705 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.110     ; 2.935      ;
; 5.705 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.109     ; 2.936      ;
; 5.705 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 2.939      ;
; 5.705 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 2.939      ;
; 5.705 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 2.937      ;
; 5.705 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 2.938      ;
; 5.705 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 2.939      ;
; 5.705 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 2.937      ;
; 5.707 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.159     ; 2.882      ;
; 5.707 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.159     ; 2.882      ;
; 5.707 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.160     ; 2.881      ;
; 5.707 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.160     ; 2.881      ;
; 5.776 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 2.818      ;
; 5.776 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 2.818      ;
; 5.777 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 2.815      ;
; 5.783 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 2.813      ;
; 5.783 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 2.813      ;
; 5.783 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.139     ; 2.816      ;
; 5.783 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.139     ; 2.816      ;
; 5.786 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.150     ; 2.802      ;
; 5.792 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.140     ; 2.806      ;
; 5.792 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.140     ; 2.806      ;
; 5.792 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 2.805      ;
; 5.792 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 2.805      ;
; 5.805 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.114     ; 2.819      ;
; 5.805 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.114     ; 2.819      ;
; 5.805 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.115     ; 2.818      ;
; 5.805 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.115     ; 2.818      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.772      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.772      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.772      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.772      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.772      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.772      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.772      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.772      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.772      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.772      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.772      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.772      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.772      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.772      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.775      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.775      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.775      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.775      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.775      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.775      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.775      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.775      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.775      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.775      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.775      ;
; 5.922 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.775      ;
; 5.923 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 2.766      ;
; 5.923 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.104     ; 2.770      ;
; 5.923 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.104     ; 2.770      ;
; 5.923 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 2.767      ;
; 5.923 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 2.767      ;
; 5.923 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 2.767      ;
; 5.923 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 2.767      ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                        ;
+--------+------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                                                            ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 13.380 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.105     ; 4.123      ;
; 13.380 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.105     ; 4.123      ;
; 13.380 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.105     ; 4.123      ;
; 13.380 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[31]                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.105     ; 4.123      ;
; 13.380 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.105     ; 4.123      ;
; 13.380 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[20]                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.105     ; 4.123      ;
; 13.380 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.105     ; 4.123      ;
; 13.380 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.096     ; 4.132      ;
; 13.385 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 4.136      ;
; 13.387 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.102     ; 4.119      ;
; 13.387 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[22]                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 4.122      ;
; 13.387 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[28]                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.102     ; 4.119      ;
; 13.387 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[24]                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.102     ; 4.119      ;
; 13.387 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[17]                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 4.122      ;
; 13.387 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.102     ; 4.119      ;
; 13.387 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 4.122      ;
; 13.387 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 4.122      ;
; 13.387 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[21]                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.102     ; 4.119      ;
; 13.403 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 4.119      ;
; 13.403 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|memory_ready_reg                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.096     ; 4.109      ;
; 13.555 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.077      ; 4.130      ;
; 13.555 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.077      ; 4.130      ;
; 13.555 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.077      ; 4.130      ;
; 13.555 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.077      ; 4.130      ;
; 13.569 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[7]                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.944      ;
; 13.569 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[6]                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.944      ;
; 13.569 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[4]                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.944      ;
; 13.569 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[5]                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.944      ;
; 13.569 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[3]                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.944      ;
; 13.569 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[2]                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.944      ;
; 13.569 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[1]                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.944      ;
; 13.569 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[14]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.100     ; 3.939      ;
; 13.569 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[8]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.100     ; 3.939      ;
; 13.569 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|stretch                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 3.945      ;
; 13.569 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[0]                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.944      ;
; 13.569 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[9]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.100     ; 3.939      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[1]                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 3.943      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[2]                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 3.943      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.mstr_ack                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 3.944      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[8]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.937      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[7]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.937      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[6]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.937      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[5]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.937      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[4]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.937      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[3]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.937      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[2]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.937      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[1]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.937      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[0]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.937      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[16]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.937      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[15]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.937      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.937      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[12]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.937      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[11]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.937      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[2]        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.105     ; 3.927      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[3]        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.105     ; 3.927      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.105     ; 3.927      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 3.926      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[1]        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.105     ; 3.927      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[0]        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.105     ; 3.927      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.105     ; 3.927      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[6]        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.105     ; 3.927      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.105     ; 3.927      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[7]        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.105     ; 3.927      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.105     ; 3.927      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[5]        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.105     ; 3.927      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.105     ; 3.927      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[4]        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.105     ; 3.927      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.105     ; 3.927      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.105     ; 3.927      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 3.926      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 3.926      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 3.926      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 3.926      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 3.926      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 3.926      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 3.926      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 3.926      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_reg               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 3.929      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[0]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 3.929      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[1]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 3.929      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[2]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 3.929      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[3]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 3.929      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[4]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 3.929      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[5]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 3.929      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[6]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 3.929      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.slv_ack2                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 3.943      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.stop                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 3.944      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 3.944      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.start                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 3.944      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[4]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.942      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[5]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.942      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.942      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[6]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.942      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[0]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.942      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[1]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.942      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[3]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.942      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[2]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.942      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 3.944      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|sda_int                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 3.944      ;
; 13.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.wr                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 3.944      ;
+--------+------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.683 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|dffe4                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.204      ; 0.977      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a63 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a62 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a61 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a60 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a59 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a58 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a57 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a56 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a35 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a34 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a33 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a32 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a31 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a29 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a28 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a27 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a26 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a25 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a24 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 0.989      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a55 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a54 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a53 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a52 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a51 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a50 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a49 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a48 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a47 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a46 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a45 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a44 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a43 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a42 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a41 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a40 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a39 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a38 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a37 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a36 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a23 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a22 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a21 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a20 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a19 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a18 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a17 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 0.846 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 1.111      ;
; 2.068 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[0]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.296      ; 2.448      ;
; 2.080 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.256      ; 2.420      ;
; 2.080 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.256      ; 2.420      ;
; 2.092 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.242      ; 2.418      ;
; 2.092 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[7]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.242      ; 2.418      ;
; 2.092 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[0]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.242      ; 2.418      ;
; 2.092 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[3]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.242      ; 2.418      ;
; 2.092 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[2]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.242      ; 2.418      ;
; 2.092 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[1]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.242      ; 2.418      ;
; 2.094 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[2]                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.246      ; 2.424      ;
; 2.095 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_dma_clock_del:antic_dma_clock1|dma_shiftreg_reg[7]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.243      ; 2.422      ;
; 2.097 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[0]                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.236      ; 2.417      ;
; 2.097 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[3]                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.236      ; 2.417      ;
; 2.098 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.234      ; 2.416      ;
; 2.103 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.241      ; 2.428      ;
; 2.103 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.241      ; 2.428      ;
; 2.103 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.241      ; 2.428      ;
; 2.103 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.241      ; 2.428      ;
; 2.103 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.241      ; 2.428      ;
; 2.104 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[1]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.241      ; 2.429      ;
; 2.104 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.241      ; 2.429      ;
; 2.104 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[2]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.241      ; 2.429      ;
; 2.104 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[3]                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.234      ; 2.422      ;
; 2.105 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[3]                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.236      ; 2.425      ;
; 2.105 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[2]                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.236      ; 2.425      ;
; 2.105 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[1]                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.236      ; 2.425      ;
; 2.105 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[0]                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.236      ; 2.425      ;
; 2.105 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0]                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.236      ; 2.425      ;
; 2.105 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[6]                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.238      ; 2.427      ;
; 2.105 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.239      ; 2.428      ;
; 2.105 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_freezer_reg                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.239      ; 2.428      ;
; 2.105 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.239      ; 2.428      ;
; 2.105 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[1]                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.238      ; 2.427      ;
; 2.105 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.239      ; 2.428      ;
; 2.105 ; user_io:my_user_io|but_sw[1]                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[2]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.239      ; 2.428      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                   ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 2.249 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 2.434      ;
; 2.249 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 2.434      ;
; 2.249 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.438      ;
; 2.249 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.438      ;
; 2.249 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.438      ;
; 2.249 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.438      ;
; 2.249 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.438      ;
; 2.249 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.438      ;
; 2.249 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.438      ;
; 2.249 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.438      ;
; 2.249 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.438      ;
; 2.249 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.438      ;
; 2.249 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.438      ;
; 2.249 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 2.434      ;
; 2.249 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cke_reg                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 2.445      ;
; 2.250 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 2.434      ;
; 2.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 2.439      ;
; 2.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 2.439      ;
; 2.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 2.439      ;
; 2.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 2.439      ;
; 2.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 2.439      ;
; 2.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 2.439      ;
; 2.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 2.439      ;
; 2.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 2.439      ;
; 2.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 2.439      ;
; 2.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 2.439      ;
; 2.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 2.439      ;
; 2.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 2.439      ;
; 2.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 2.439      ;
; 2.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 2.439      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 2.434      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.438      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.438      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 2.435      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 2.435      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 2.435      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 2.435      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 2.435      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 2.435      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 2.435      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 2.435      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 2.435      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 2.434      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 2.435      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 2.435      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 2.435      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.438      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 2.435      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 2.434      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 2.435      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.073      ; 2.431      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 2.434      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.438      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 2.435      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 2.435      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 2.434      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.438      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 2.433      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.438      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.073      ; 2.431      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 2.434      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.073      ; 2.431      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 2.442      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 2.442      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 2.442      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 2.442      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 2.442      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 2.442      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 2.442      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 2.442      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 2.442      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 2.442      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 2.442      ;
; 2.255 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 2.442      ;
; 2.335 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 2.493      ;
; 2.335 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 2.493      ;
; 2.335 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 2.492      ;
; 2.335 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 2.492      ;
; 2.352 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.049      ; 2.484      ;
; 2.352 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.049      ; 2.484      ;
; 2.352 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.047      ; 2.482      ;
; 2.352 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.047      ; 2.482      ;
; 2.357 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.050      ; 2.490      ;
; 2.357 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.050      ; 2.490      ;
; 2.358 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.038      ; 2.479      ;
; 2.358 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.046      ; 2.487      ;
; 2.358 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.046      ; 2.487      ;
; 2.364 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.042      ; 2.489      ;
; 2.365 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.045      ; 2.493      ;
; 2.365 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.045      ; 2.493      ;
; 2.455 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 2.613      ;
; 2.455 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.612      ;
; 2.455 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 2.614      ;
; 2.455 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 2.613      ;
; 2.456 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.616      ;
; 2.456 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.616      ;
; 2.456 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 2.615      ;
; 2.456 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 2.615      ;
; 2.456 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 2.612      ;
; 2.456 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 2.611      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                             ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cke_reg                      ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|reply_reg                    ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ;
; 4.189 ; 4.344        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ;
; 4.191 ; 4.346        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg                ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ;
; 4.194 ; 4.349        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                 ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                 ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                 ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                 ;
; 4.196 ; 4.351        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                 ;
; 4.198 ; 4.353        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                 ;
; 4.198 ; 4.353        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                ;
; 4.198 ; 4.353        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                ;
; 4.198 ; 4.353        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]                ;
; 4.198 ; 4.353        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                     ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 4.331 ; 4.400        ; 0.069          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.357 ; 4.410        ; 0.053          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.378 ; 4.378        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.378 ; 4.378        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|i                                                                                                                    ;
; 4.378 ; 4.378        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|o                                                                                                                    ;
; 4.400 ; 4.400        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.400 ; 4.400        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 4.410 ; 4.410        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.410 ; 4.410        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 4.431 ; 4.431        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.431 ; 4.431        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|i                                                                                                                    ;
; 4.431 ; 4.431        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|o                                                                                                                    ;
; 4.810 ; 8.810        ; 4.000          ; Port Rate        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                         ;
+-------+--------------+----------------+-----------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type            ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                                                                                                                     ;
+-------+--------------+----------------+-----------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.559 ; 8.789        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a1~porta_address_reg0                                                                                                                            ;
; 8.559 ; 8.789        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a23~porta_address_reg0                                                                                                                           ;
; 8.559 ; 8.789        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a6~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                              ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_we_reg                                                                                                                                    ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_we_reg       ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_address_reg0                                 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_we_reg                                       ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_address_reg0    ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_address_reg0    ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a4~porta_address_reg0                                                                                              ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a4~porta_we_reg                                                                                                    ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a10~porta_address_reg0                                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a11~porta_address_reg0                                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a13~porta_address_reg0                                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a14~porta_address_reg0                                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a3~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a4~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a5~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a7~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a8~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a9~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_address_reg0                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_we_reg                                                                                                                 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                          ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                  ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_address_reg0                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_we_reg                                                                                                                  ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_address_reg0             ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_we_reg                   ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                              ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_we_reg                                                                                                                                    ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~portb_address_reg0    ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~portb_address_reg0    ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_address_reg0                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_we_reg                                                                                                                 ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_address_reg0                                                                                                          ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_we_reg                                                                                                                ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                               ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_datain_reg0                                  ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0     ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8~porta_datain_reg0     ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a4~porta_datain_reg0                                                                                               ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                            ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                            ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_datain_reg0                                                                                                            ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                           ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                             ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_datain_reg0                                                                                                             ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_datain_reg0              ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|altsyncram_gd81:FIFOram|ram_block1a0~porta_address_reg0           ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|altsyncram_gd81:FIFOram|ram_block1a0~porta_we_reg                 ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_datain_reg0                                                                                                                               ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~portb_address_reg0                                                                                                                                    ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                    ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|gtia_palette:palette4|altsyncram:Mux18_rtl_0|altsyncram_vq01:auto_generated|ram_block1a0~porta_address_reg0                                                                                                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_address_reg0                                                                                              ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg                                                                                                    ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_address_reg0                                                                                              ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg                                                                                                    ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a4~porta_address_reg0                                                                                              ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a4~porta_we_reg                                                                                                    ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a12~porta_address_reg0                                                                                                                           ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_datain_reg0                                                                                                            ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_datain_reg0                                                                                                           ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0                       ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a1                       ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a10                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a11                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a12                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a13                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a14                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a15                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a17                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a18                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a19                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a2                       ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a20                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a21                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a22                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a23                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a24                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a25                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a26                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a27                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a28                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a29                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a3                       ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a30                      ;
+-------+--------------+----------------+-----------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                           ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                ; Clock Edge ; Target                                                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.310 ; 16.310       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.310 ; 16.310       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.315 ; 16.315       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.316 ; 16.316       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.321 ; 16.321       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.321 ; 16.321       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.330 ; 16.330       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.330 ; 16.330       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.330 ; 16.330       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.330 ; 16.330       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'clk_27'                                                                                                               ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target                                                                         ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 17.928 ; 17.928       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 17.928 ; 17.928       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 17.929 ; 17.929       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 17.929 ; 17.929       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 17.960 ; 17.960       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 17.970 ; 17.970       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 17.971 ; 17.971       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 17.972 ; 17.972       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 17.972 ; 17.972       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 19.064 ; 19.064       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 19.064 ; 19.064       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 19.066 ; 19.066       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 19.067 ; 19.067       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 19.077 ; 19.077       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 19.107 ; 19.107       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 19.107 ; 19.107       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 19.108 ; 19.108       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 19.108 ; 19.108       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 33.037 ; 37.037       ; 4.000          ; Port Rate        ; clk_27 ; Rise       ; CLOCK_27[0]                                                                    ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'SPI_SCK'                                                                                                                                        ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                                                                                  ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+
; 20.000 ; 20.230       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 20.000 ; 20.230       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_we_reg       ;
; 20.001 ; 20.231       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ;
; 20.001 ; 20.231       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_we_reg       ;
; 20.002 ; 20.232       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 20.003 ; 20.233       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ;
; 20.022 ; 20.238       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|SPI_MISO~en                                                                          ;
; 20.022 ; 20.238       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|SPI_MISO~reg0                                                                        ;
; 20.022 ; 20.238       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[0]                                                                   ;
; 20.022 ; 20.238       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[1]                                                                   ;
; 20.022 ; 20.238       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[2]                                                                   ;
; 20.022 ; 20.238       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[3]                                                                   ;
; 20.022 ; 20.238       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[4]                                                                   ;
; 20.022 ; 20.238       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[5]                                                                   ;
; 20.062 ; 20.246       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[0]                                                                           ;
; 20.062 ; 20.246       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[1]                                                                           ;
; 20.062 ; 20.246       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[2]                                                                           ;
; 20.062 ; 20.246       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transfer_end_r                                                                   ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[0]                                                                               ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[1]                                                                               ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[2]                                                                               ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[3]                                                                               ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[0]                                                                              ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[1]                                                                              ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[2]                                                                              ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[0]                                                                       ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[1]                                                                       ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[2]                                                                       ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[7]                                                                       ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_receiver_strobe_r                                                                ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[0]                                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[1]                                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[2]                                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[0]                                                                            ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[1]                                                                            ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[2]                                                                            ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[3]                                                                            ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[4]                                                                            ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[5]                                                                            ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[6]                                                                            ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[0]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[1]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[2]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[3]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[4]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[5]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[6]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[7]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_receiver_strobe_r                                                              ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_transfer_end_r                                                                 ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[0]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[10]                                                                                   ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[1]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[2]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[3]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[4]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[5]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[6]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[7]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[8]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[9]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[0]                                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[1]                                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[2]                                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[3]                                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[4]                                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|osd_enable                                                                                 ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[0]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[1]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[2]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[4]                                                                               ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[5]                                                                               ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[6]                                                                               ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[7]                                                                               ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[3]                                                                              ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[4]                                                                              ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[5]                                                                              ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[6]                                                                              ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[3]                                                                       ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[4]                                                                       ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[5]                                                                       ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[6]                                                                       ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[0]                                                                      ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[1]                                                                      ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[2]                                                                      ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[3]                                                                      ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[4]                                                                      ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[5]                                                                      ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[6]                                                                      ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[7]                                                                      ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.drive_sel_r[0]                                                       ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[0]                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[11]                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[12]                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[13]                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[15]                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[16]                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[17]                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[19]                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[1]                                                          ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                      ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                                                                                                                                ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 40.631 ; 41.641       ; 1.010          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ;
; 40.680 ; 41.690       ; 1.010          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ;
; 41.415 ; 41.645       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ;
; 41.415 ; 41.645       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ;
; 41.415 ; 41.645       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ;
; 41.415 ; 41.645       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_we_reg       ;
; 41.416 ; 41.646       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|q_a[0]                                                                                                              ;
; 41.416 ; 41.646       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pal_rom:pll_rom_pal|altsyncram:altsyncram_component|altsyncram_gfr3:auto_generated|q_a[0]                                                                                                                ;
; 41.417 ; 41.647       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 41.437 ; 41.653       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate3_state                                                                   ;
; 41.448 ; 41.664       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[0]                          ;
; 41.448 ; 41.664       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]                          ;
; 41.448 ; 41.664       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]                          ;
; 41.448 ; 41.664       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]                          ;
; 41.448 ; 41.664       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]                          ;
; 41.448 ; 41.664       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]                          ;
; 41.448 ; 41.664       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]                          ;
; 41.448 ; 41.664       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]                          ;
; 41.448 ; 41.664       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                        ;
; 41.448 ; 41.664       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                                                 ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_counter_state                                                                ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|tmp_seq_ena_state                                                                     ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; rom_loaded                                                                                                                                                                                                                            ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                           ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                 ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                                ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                                ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                                ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                                ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                                ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                                ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                                ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                 ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                 ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                 ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                 ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                 ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                 ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                 ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                                 ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                                 ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_reconfig_write_from_rom                                                                                                                                                                              ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                         ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                         ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                      ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                                              ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                                  ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                                  ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                                  ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_init_state                                                                   ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                                                       ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                                        ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|rden_a_store                                                                                                        ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                          ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[0]                                                                     ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[1]                                                                     ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[2]                                                                     ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[3]                                                                     ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[4]                                                                     ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[5]                                                                     ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[6]                                                                     ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[7]                                                                     ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[0]                                                                      ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[1]                                                                      ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[2]                                                                      ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[3]                                                                      ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[4]                                                                      ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[5]                                                                      ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[6]                                                                      ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[7]                                                                      ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                          ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                                                   ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                                                    ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0]                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5]                         ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; 2.135 ; 2.772 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 2.941 ; 3.471 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; 0.525 ; 0.947 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; 0.759 ; 1.148 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 1.472 ; 2.024 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.466 ; 2.018 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.470 ; 2.022 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.472 ; 2.024 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.472 ; 2.024 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.447 ; 2.005 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.457 ; 2.015 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.448 ; 2.006 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.448 ; 2.006 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.454 ; 2.006 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.454 ; 2.006 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.459 ; 2.011 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.459 ; 2.011 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.460 ; 2.012 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.460 ; 2.012 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.471 ; 2.023 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.471 ; 2.023 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                        ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; -1.233 ; -1.960 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 0.434  ; -0.042 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; -0.317 ; -0.755 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; -0.056 ; -0.502 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; -0.968 ; -1.526 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; -0.988 ; -1.540 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; -0.992 ; -1.544 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; -0.994 ; -1.546 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; -0.994 ; -1.546 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; -0.968 ; -1.526 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; -0.978 ; -1.536 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; -0.969 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; -0.969 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; -0.975 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; -0.975 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; -0.980 ; -1.532 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; -0.980 ; -1.532 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; -0.981 ; -1.533 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; -0.981 ; -1.533 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; -0.993 ; -1.545 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; -0.993 ; -1.545 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                             ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 5.732  ; 5.608  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 1.615  ; 1.481  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 1.534  ; 1.413  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 1.535  ; 1.414  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 1.536  ; 1.415  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 1.546  ; 1.425  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 1.539  ; 1.424  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 1.615  ; 1.481  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 1.599  ; 1.465  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 1.603  ; 1.469  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 1.603  ; 1.469  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 1.603  ; 1.469  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 1.535  ; 1.414  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 1.610  ; 1.476  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 1.533  ; 1.412  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 1.533  ; 1.412  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 1.525  ; 1.404  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 1.059  ; 1.053  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 1.610  ; 1.476  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.595  ; 1.461  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.591  ; 1.457  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.531  ; 1.416  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.531  ; 1.416  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.547  ; 1.426  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.557  ; 1.436  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.546  ; 1.425  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.546  ; 1.425  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.588  ; 1.454  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.588  ; 1.454  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.603  ; 1.469  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.603  ; 1.469  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.524  ; 1.409  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.602  ; 1.468  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.610  ; 1.476  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.532  ; 1.417  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 1.587  ; 1.453  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 1.546  ; 1.425  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 1.534  ; 1.413  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 1.532  ; 1.411  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 1.546  ; 1.425  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 10.148 ; 10.169 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 10.096 ; 10.117 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 10.148 ; 10.169 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 10.059 ; 10.086 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 10.141 ; 10.156 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 10.052 ; 10.141 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 9.555  ; 9.672  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 9.869  ; 9.928  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 9.598  ; 9.710  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 9.801  ; 9.860  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 9.869  ; 9.928  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 9.533  ; 9.630  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 9.486  ; 9.555  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 7.993  ; 8.150  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 4.078  ; 3.816  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 10.947 ; 10.975 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 10.648 ; 10.630 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 10.814 ; 10.832 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 10.947 ; 10.975 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 10.847 ; 10.906 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 10.693 ; 10.830 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 10.406 ; 10.481 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 3.681  ; 3.545  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -1.808 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -1.834 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                     ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 5.641  ; 5.511  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 1.104  ; 0.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 1.104  ; 0.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 1.105  ; 0.986  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 1.105  ; 0.986  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 1.116  ; 0.997  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 1.107  ; 0.994  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 1.183  ; 1.051  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 1.168  ; 1.036  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 1.172  ; 1.040  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 1.172  ; 1.040  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 1.171  ; 1.039  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 1.104  ; 0.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 1.178  ; 1.046  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 1.094  ; 0.975  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 1.103  ; 0.984  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 1.094  ; 0.975  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 0.650  ; 0.643  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 1.092  ; 0.979  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.164  ; 1.032  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.160  ; 1.028  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.100  ; 0.987  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.100  ; 0.987  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.117  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.127  ; 1.008  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.116  ; 0.997  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.116  ; 0.997  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.156  ; 1.024  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.156  ; 1.024  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.171  ; 1.039  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.171  ; 1.039  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.092  ; 0.979  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.170  ; 1.038  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.179  ; 1.047  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.101  ; 0.988  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 1.156  ; 1.024  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 1.116  ; 0.997  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 1.103  ; 0.984  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 1.102  ; 0.983  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 1.116  ; 0.997  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 2.726  ; 2.769  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 2.814  ; 2.888  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 2.726  ; 2.769  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 2.758  ; 2.923  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 2.831  ; 2.850  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 2.892  ; 3.117  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 2.739  ; 2.957  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 2.621  ; 2.699  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 2.700  ; 2.762  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 2.621  ; 2.699  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 2.891  ; 2.932  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 2.848  ; 2.966  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 2.685  ; 2.791  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 2.917  ; 3.180  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 3.040  ; 2.792  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 2.781  ; 2.770  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 2.798  ; 2.770  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 2.870  ; 2.914  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 2.906  ; 2.924  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 2.839  ; 2.876  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 3.002  ; 3.031  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 2.781  ; 2.819  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 2.921  ; 2.708  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -2.192 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -2.219 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+----------------------------------------------------------+
; Propagation Delay                                        ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 5.930 ; 5.930 ; 6.564 ; 6.537 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------+
; Minimum Propagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 4.992 ; 4.875 ; 5.507 ; 5.507 ;
+------------+-------------+-------+-------+-------+-------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 5.576 ; 5.549 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 2.249 ; 2.171 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.264 ; 2.178 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.260 ; 2.174 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.278 ; 2.192 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.278 ; 2.192 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.250 ; 2.175 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.260 ; 2.185 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.249 ; 2.174 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.249 ; 2.174 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.257 ; 2.171 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.257 ; 2.171 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.272 ; 2.186 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.272 ; 2.186 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.271 ; 2.185 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.271 ; 2.185 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.279 ; 2.193 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.279 ; 2.193 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                     ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 4.569 ; 4.569 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 0.932 ; 0.875 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 0.940 ; 0.883 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 0.936 ; 0.879 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 0.954 ; 0.897 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 0.954 ; 0.897 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 0.952 ; 0.898 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 0.962 ; 0.908 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 0.951 ; 0.897 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 0.951 ; 0.897 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 0.932 ; 0.875 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 0.932 ; 0.875 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 0.947 ; 0.890 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 0.947 ; 0.890 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 0.946 ; 0.889 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 0.946 ; 0.889 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 0.955 ; 0.898 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 0.955 ; 0.898 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 5.750     ; 5.750     ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 2.225     ; 2.281     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.237     ; 2.296     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.233     ; 2.292     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.251     ; 2.310     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.251     ; 2.310     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.226     ; 2.282     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.236     ; 2.292     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.225     ; 2.281     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.225     ; 2.281     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.230     ; 2.289     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.230     ; 2.289     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.245     ; 2.304     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.245     ; 2.304     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.244     ; 2.303     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.244     ; 2.303     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.252     ; 2.311     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.252     ; 2.311     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 4.738     ; 4.855     ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 0.906     ; 1.080     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 0.914     ; 1.088     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 0.910     ; 1.084     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 0.928     ; 1.102     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 0.928     ; 1.102     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 0.929     ; 1.115     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 0.939     ; 1.125     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 0.928     ; 1.114     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 0.928     ; 1.114     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 0.906     ; 1.080     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 0.906     ; 1.080     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 0.921     ; 1.095     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 0.921     ; 1.095     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 0.920     ; 1.094     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 0.920     ; 1.094     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 0.929     ; 1.103     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 0.929     ; 1.103     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                ;
+------------------------------------------------------------------------+--------+-------+----------+---------+---------------------+
; Clock                                                                  ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------------------------------------------------------------+--------+-------+----------+---------+---------------------+
; Worst-case Slack                                                       ; -1.595 ; 0.107 ; 2.219    ; 0.683   ; 4.093               ;
;  SPI_SCK                                                               ; 13.788 ; 0.142 ; N/A      ; N/A     ; 20.000              ;
;  clk_27                                                                ; 33.983 ; 0.187 ; N/A      ; N/A     ; 17.784              ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.942  ; 0.187 ; 2.219    ; 2.249   ; 4.093               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -0.801 ; 0.107 ; 8.628    ; 0.683   ; 8.378               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.595 ; 1.849 ; N/A      ; N/A     ; 4.167               ;
;  pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A    ; N/A   ; N/A      ; N/A     ; 16.275              ;
;  reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 36.629 ; 0.186 ; N/A      ; N/A     ; 40.596              ;
; Design-wide TNS                                                        ; -3.101 ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
;  SPI_SCK                                                               ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  clk_27                                                                ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000  ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -1.506 ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.595 ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A    ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
+------------------------------------------------------------------------+--------+-------+----------+---------+---------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; 4.668 ; 5.103 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 6.732 ; 6.713 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; 1.131 ; 1.427 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; 1.606 ; 1.934 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 3.027 ; 3.140 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 3.021 ; 3.134 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 3.025 ; 3.138 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 3.027 ; 3.140 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 3.027 ; 3.140 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.964 ; 3.081 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.974 ; 3.091 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.964 ; 3.081 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.965 ; 3.082 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 3.008 ; 3.121 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 3.008 ; 3.121 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 3.010 ; 3.123 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 3.010 ; 3.123 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 3.011 ; 3.124 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 3.011 ; 3.124 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 3.023 ; 3.136 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 3.023 ; 3.136 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                        ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; -1.233 ; -1.960 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 1.080  ; 0.851  ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; -0.317 ; -0.755 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; -0.056 ; -0.280 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; -0.968 ; -1.526 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; -0.988 ; -1.540 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; -0.992 ; -1.544 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; -0.994 ; -1.546 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; -0.994 ; -1.546 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; -0.968 ; -1.526 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; -0.978 ; -1.536 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; -0.969 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; -0.969 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; -0.975 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; -0.975 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; -0.980 ; -1.532 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; -0.980 ; -1.532 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; -0.981 ; -1.533 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; -0.981 ; -1.533 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; -0.993 ; -1.545 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; -0.993 ; -1.545 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                             ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 10.193 ; 9.520  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 3.319  ; 3.129  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 3.163  ; 2.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 3.164  ; 2.971  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 3.165  ; 2.972  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 3.175  ; 2.982  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 3.162  ; 2.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 3.319  ; 3.129  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 3.302  ; 3.112  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 3.307  ; 3.117  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 3.307  ; 3.117  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 3.303  ; 3.113  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 3.164  ; 2.971  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 3.310  ; 3.120  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 3.162  ; 2.969  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 3.162  ; 2.969  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 3.154  ; 2.961  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 2.450  ; 2.326  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 3.310  ; 3.120  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 3.291  ; 3.101  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 3.287  ; 3.097  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 3.147  ; 2.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 3.147  ; 2.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 3.176  ; 2.983  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 3.186  ; 2.993  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 3.176  ; 2.983  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 3.176  ; 2.983  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 3.284  ; 3.094  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 3.284  ; 3.094  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 3.302  ; 3.112  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 3.302  ; 3.112  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 3.142  ; 2.965  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 3.301  ; 3.111  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 3.310  ; 3.120  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 3.151  ; 2.974  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 3.283  ; 3.093  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 3.175  ; 2.982  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 3.163  ; 2.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 3.162  ; 2.969  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 3.175  ; 2.982  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 24.653 ; 24.297 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 24.311 ; 23.941 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 24.653 ; 24.297 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 24.375 ; 24.086 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 24.519 ; 24.243 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 24.149 ; 24.033 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 23.309 ; 22.952 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 23.516 ; 23.086 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 22.887 ; 22.581 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 23.444 ; 23.086 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 23.516 ; 23.075 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 22.669 ; 22.334 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 22.569 ; 22.364 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 19.531 ; 18.857 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 7.977  ; 7.346  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 25.769 ; 25.421 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 25.100 ; 24.776 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 25.447 ; 25.183 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 25.769 ; 25.421 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 25.305 ; 25.063 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 25.398 ; 24.954 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 24.594 ; 24.262 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 7.223  ; 6.477  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -0.884 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -1.122 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                     ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 5.641  ; 5.511  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 1.104  ; 0.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 1.104  ; 0.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 1.105  ; 0.986  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 1.105  ; 0.986  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 1.116  ; 0.997  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 1.107  ; 0.994  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 1.183  ; 1.051  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 1.168  ; 1.036  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 1.172  ; 1.040  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 1.172  ; 1.040  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 1.171  ; 1.039  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 1.104  ; 0.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 1.178  ; 1.046  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 1.094  ; 0.975  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 1.103  ; 0.984  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 1.094  ; 0.975  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 0.650  ; 0.643  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 1.092  ; 0.979  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.164  ; 1.032  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.160  ; 1.028  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.100  ; 0.987  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.100  ; 0.987  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.117  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.127  ; 1.008  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.116  ; 0.997  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.116  ; 0.997  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.156  ; 1.024  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.156  ; 1.024  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.171  ; 1.039  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.171  ; 1.039  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.092  ; 0.979  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.170  ; 1.038  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.179  ; 1.047  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.101  ; 0.988  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 1.156  ; 1.024  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 1.116  ; 0.997  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 1.103  ; 0.984  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 1.102  ; 0.983  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 1.116  ; 0.997  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 2.726  ; 2.769  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 2.814  ; 2.888  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 2.726  ; 2.769  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 2.758  ; 2.923  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 2.831  ; 2.850  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 2.892  ; 3.117  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 2.739  ; 2.957  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 2.621  ; 2.699  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 2.700  ; 2.762  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 2.621  ; 2.699  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 2.891  ; 2.932  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 2.848  ; 2.966  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 2.685  ; 2.791  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 2.917  ; 3.180  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 3.040  ; 2.792  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 2.781  ; 2.770  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 2.798  ; 2.770  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 2.870  ; 2.914  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 2.906  ; 2.924  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 2.839  ; 2.876  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 3.002  ; 3.031  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 2.781  ; 2.819  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 2.921  ; 2.708  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -2.192 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -2.219 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+--------------------------------------------------------------+
; Progagation Delay                                            ;
+------------+-------------+--------+--------+--------+--------+
; Input Port ; Output Port ; RR     ; RF     ; FR     ; FF     ;
+------------+-------------+--------+--------+--------+--------+
; CONF_DATA0 ; SPI_DO      ; 10.717 ; 10.477 ; 11.369 ; 11.369 ;
+------------+-------------+--------+--------+--------+--------+


+----------------------------------------------------------+
; Minimum Progagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 4.992 ; 4.875 ; 5.507 ; 5.507 ;
+------------+-------------+-------+-------+-------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin          ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; VGA_VS       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_HS       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_L      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_R      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[0]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[1]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nCS    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nRAS   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nCAS   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nWE    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQMH   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQML   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CLK    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CKE    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[0]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[1]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[2]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[3]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[4]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[5]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[6]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[7]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[8]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[9]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[10]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[11]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[12]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; UART_TX      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SPI_DO       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+------------------------------------------------------------------+
; Input Transition Times                                           ;
+---------------+--------------+-----------------+-----------------+
; Pin           ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+---------------+--------------+-----------------+-----------------+
; CLOCK_27[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; UART_RX       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SS4       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[2]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[3]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[4]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[5]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[6]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[7]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[8]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[9]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[10]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[11]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[12]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[13]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[14]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[15]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_DO        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SCK       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CONF_DATA0    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_DI        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SS3       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CLOCK_27[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SS2       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+---------------+--------------+-----------------+-----------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; VGA_HS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_B[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_B[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_B[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_B[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_B[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_G[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; VGA_G[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_G[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_G[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_G[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_G[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_R[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_R[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_R[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_R[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_R[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_R[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; AUDIO_L      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.08 V              ; -0.00545 V          ; 0.234 V                              ; 0.291 V                              ; 5.77e-09 s                  ; 4.44e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.01e-07 V                  ; 3.08 V             ; -0.00545 V         ; 0.234 V                             ; 0.291 V                             ; 5.77e-09 s                 ; 4.44e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_BA[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_nCS    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_nRAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_nCAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_nWE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQMH   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQML   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_CLK    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_CKE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[0]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[1]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[2]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[3]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[4]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[5]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_A[6]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_A[7]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_A[8]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_A[9]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_A[10]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[11]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_A[12]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; LED          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.08 V              ; -0.00545 V          ; 0.234 V                              ; 0.291 V                              ; 5.77e-09 s                  ; 4.44e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.01e-07 V                  ; 3.08 V             ; -0.00545 V         ; 0.234 V                             ; 0.291 V                             ; 5.77e-09 s                 ; 4.44e-09 s                 ; Yes                       ; Yes                       ;
; UART_TX      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; SPI_DO       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.08 V              ; -0.00545 V          ; 0.234 V                              ; 0.291 V                              ; 5.77e-09 s                  ; 4.44e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.01e-07 V                  ; 3.08 V             ; -0.00545 V         ; 0.234 V                             ; 0.291 V                             ; 5.77e-09 s                 ; 4.44e-09 s                 ; Yes                       ; Yes                       ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; VGA_HS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; VGA_B[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_B[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_B[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_B[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_B[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_B[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_G[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; VGA_G[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_G[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_G[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_G[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_G[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_R[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_R[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_R[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_R[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_R[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_R[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; AUDIO_L      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; AUDIO_R      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.48 V              ; -0.0164 V           ; 0.353 V                              ; 0.315 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.48 V             ; -0.0164 V          ; 0.353 V                             ; 0.315 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; SDRAM_BA[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_BA[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_nCS    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_nRAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_nCAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_nWE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_DQMH   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQML   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_CLK    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_CKE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; SDRAM_A[0]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_A[1]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_A[2]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_A[3]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_A[4]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; SDRAM_A[5]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_A[6]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_A[7]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_A[8]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_A[9]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_A[10]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_A[11]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_A[12]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; LED          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.48 V              ; -0.0164 V           ; 0.353 V                              ; 0.315 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.48 V             ; -0.0164 V          ; 0.353 V                             ; 0.315 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; UART_TX      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; SPI_DO       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.48 V              ; -0.0164 V           ; 0.353 V                              ; 0.315 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.48 V             ; -0.0164 V          ; 0.353 V                             ; 0.315 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                             ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+----------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths   ; FR Paths ; RF Paths ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+----------+----------+
; clk_27                                                                ; clk_27                                                                ; 85         ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2600       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 124        ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 16         ; 0        ; 0        ; 0        ;
; clk_27                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 36         ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 243442746  ; 20       ; 1        ; 817      ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0        ; 0        ; 0        ;
; SPI_SCK                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 52         ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0          ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; false path ; 0        ; 0        ; 0        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 1489       ; 4        ; 20       ; 1        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; SPI_SCK                                                               ; false path ; 0        ; 0        ; 0        ;
; SPI_SCK                                                               ; SPI_SCK                                                               ; 8003       ; 6        ; 147      ; 57       ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                              ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+----------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths   ; FR Paths ; RF Paths ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+----------+----------+
; clk_27                                                                ; clk_27                                                                ; 85         ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2600       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 124        ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 16         ; 0        ; 0        ; 0        ;
; clk_27                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 36         ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 243442746  ; 20       ; 1        ; 817      ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0        ; 0        ; 0        ;
; SPI_SCK                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 52         ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0          ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; false path ; 0        ; 0        ; 0        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 1489       ; 4        ; 20       ; 1        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; SPI_SCK                                                               ; false path ; 0        ; 0        ; 0        ;
; SPI_SCK                                                               ; SPI_SCK                                                               ; 8003       ; 6        ; 147      ; 57       ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                                            ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+------------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths   ; FR Paths ; RF Paths   ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+------------+----------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; clk_27                                                                ; false path ; 0        ; 0          ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 141        ; 0        ; 0          ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 14353      ; 0        ; 0          ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; SPI_SCK                                                               ; 0          ; 0        ; false path ; 0        ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                                             ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+------------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths   ; FR Paths ; RF Paths   ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+------------+----------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; clk_27                                                                ; false path ; 0        ; 0          ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 141        ; 0        ; 0          ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 14353      ; 0        ; 0          ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; SPI_SCK                                                               ; 0          ; 0        ; false path ; 0        ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 4     ; 4    ;
; Unconstrained Input Port Paths  ; 186   ; 186  ;
; Unconstrained Output Ports      ; 2     ; 2    ;
; Unconstrained Output Port Paths ; 5     ; 5    ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Fri Jun 14 21:19:01 2024
Info: Command: quartus_sta atari800core -c atari800core
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'atari800core.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 27 -multiply_by 100 -duty_cycle 50.00 -name {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]} {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 27 -multiply_by 50 -duty_cycle 50.00 -name {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]} {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 27 -multiply_by 100 -phase -100.00 -duty_cycle 50.00 -name {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]} {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 200 -multiply_by 227 -duty_cycle 50.00 -name {pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]} {pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 9 -multiply_by 4 -duty_cycle 50.00 -name {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]} {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -1.595
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.595        -1.595 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    -0.801        -1.506 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.942         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    13.788         0.000 SPI_SCK 
    Info (332119):    33.983         0.000 clk_27 
    Info (332119):    36.629         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case hold slack is 0.353
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.353         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.427         0.000 SPI_SCK 
    Info (332119):     0.454         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.455         0.000 clk_27 
    Info (332119):     0.455         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     2.208         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is 2.219
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     2.219         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     8.628         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case removal slack is 1.590
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     1.590         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     4.901         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 4.093
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.093         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.193         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.378         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    16.275         0.000 pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    18.278         0.000 clk_27 
    Info (332119):    20.416         0.000 SPI_SCK 
    Info (332119):    40.596         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -1.298
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.298        -1.298 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     0.176         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.979         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    14.293         0.000 SPI_SCK 
    Info (332119):    34.269         0.000 clk_27 
    Info (332119):    36.881         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case hold slack is 0.336
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.336         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.402         0.000 SPI_SCK 
    Info (332119):     0.402         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.403         0.000 clk_27 
    Info (332119):     0.403         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     2.111         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is 2.671
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     2.671         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     9.344         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case removal slack is 1.463
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     1.463         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     4.430         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 4.097
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.097         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.167         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.400         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    16.279         0.000 pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    18.274         0.000 clk_27 
    Info (332119):    20.401         0.000 SPI_SCK 
    Info (332119):    40.596         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 0.321
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.321         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     2.392         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     6.894         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    18.385         0.000 SPI_SCK 
    Info (332119):    35.701         0.000 clk_27 
    Info (332119):    39.547         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case hold slack is 0.107
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.107         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.142         0.000 SPI_SCK 
    Info (332119):     0.186         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.187         0.000 clk_27 
    Info (332119):     0.187         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.849         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is 5.668
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.668         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    13.380         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case removal slack is 0.683
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.683         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     2.249         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 4.187
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.187         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.331         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.559         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    16.300         0.000 pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.784         0.000 clk_27 
    Info (332119):    20.000         0.000 SPI_SCK 
    Info (332119):    40.631         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 562 megabytes
    Info: Processing ended: Fri Jun 14 21:19:08 2024
    Info: Elapsed time: 00:00:07
    Info: Total CPU time (on all processors): 00:00:09


