TimeQuest Timing Analyzer report for atari800core
Sun Feb  7 09:46:44 2021
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 14. Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 15. Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 16. Slow 1200mV 85C Model Setup: 'SPI_SCK'
 17. Slow 1200mV 85C Model Setup: 'clk_27'
 18. Slow 1200mV 85C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 19. Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 20. Slow 1200mV 85C Model Hold: 'SPI_SCK'
 21. Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 22. Slow 1200mV 85C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 23. Slow 1200mV 85C Model Hold: 'clk_27'
 24. Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 25. Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 26. Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 27. Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 28. Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 29. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 30. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 31. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 32. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
 33. Slow 1200mV 85C Model Minimum Pulse Width: 'clk_27'
 34. Slow 1200mV 85C Model Minimum Pulse Width: 'SPI_SCK'
 35. Slow 1200mV 85C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 36. Setup Times
 37. Hold Times
 38. Clock to Output Times
 39. Minimum Clock to Output Times
 40. Propagation Delay
 41. Minimum Propagation Delay
 42. Output Enable Times
 43. Minimum Output Enable Times
 44. Output Disable Times
 45. Minimum Output Disable Times
 46. Slow 1200mV 85C Model Metastability Report
 47. Slow 1200mV 0C Model Fmax Summary
 48. Slow 1200mV 0C Model Setup Summary
 49. Slow 1200mV 0C Model Hold Summary
 50. Slow 1200mV 0C Model Recovery Summary
 51. Slow 1200mV 0C Model Removal Summary
 52. Slow 1200mV 0C Model Minimum Pulse Width Summary
 53. Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 54. Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 55. Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 56. Slow 1200mV 0C Model Setup: 'SPI_SCK'
 57. Slow 1200mV 0C Model Setup: 'clk_27'
 58. Slow 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 59. Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 60. Slow 1200mV 0C Model Hold: 'SPI_SCK'
 61. Slow 1200mV 0C Model Hold: 'clk_27'
 62. Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 63. Slow 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 64. Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 65. Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 66. Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 67. Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 68. Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 69. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 70. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 71. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 72. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
 73. Slow 1200mV 0C Model Minimum Pulse Width: 'clk_27'
 74. Slow 1200mV 0C Model Minimum Pulse Width: 'SPI_SCK'
 75. Slow 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 76. Setup Times
 77. Hold Times
 78. Clock to Output Times
 79. Minimum Clock to Output Times
 80. Propagation Delay
 81. Minimum Propagation Delay
 82. Output Enable Times
 83. Minimum Output Enable Times
 84. Output Disable Times
 85. Minimum Output Disable Times
 86. Slow 1200mV 0C Model Metastability Report
 87. Fast 1200mV 0C Model Setup Summary
 88. Fast 1200mV 0C Model Hold Summary
 89. Fast 1200mV 0C Model Recovery Summary
 90. Fast 1200mV 0C Model Removal Summary
 91. Fast 1200mV 0C Model Minimum Pulse Width Summary
 92. Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 93. Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 94. Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 95. Fast 1200mV 0C Model Setup: 'SPI_SCK'
 96. Fast 1200mV 0C Model Setup: 'clk_27'
 97. Fast 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 98. Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 99. Fast 1200mV 0C Model Hold: 'SPI_SCK'
100. Fast 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
101. Fast 1200mV 0C Model Hold: 'clk_27'
102. Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
103. Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
104. Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
105. Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
106. Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
107. Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
108. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
109. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
110. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
111. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
112. Fast 1200mV 0C Model Minimum Pulse Width: 'clk_27'
113. Fast 1200mV 0C Model Minimum Pulse Width: 'SPI_SCK'
114. Fast 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
115. Setup Times
116. Hold Times
117. Clock to Output Times
118. Minimum Clock to Output Times
119. Propagation Delay
120. Minimum Propagation Delay
121. Output Enable Times
122. Minimum Output Enable Times
123. Output Disable Times
124. Minimum Output Disable Times
125. Fast 1200mV 0C Model Metastability Report
126. Multicorner Timing Analysis Summary
127. Setup Times
128. Hold Times
129. Clock to Output Times
130. Minimum Clock to Output Times
131. Progagation Delay
132. Minimum Progagation Delay
133. Board Trace Model Assignments
134. Input Transition Times
135. Slow Corner Signal Integrity Metrics
136. Fast Corner Signal Integrity Metrics
137. Setup Transfers
138. Hold Transfers
139. Recovery Transfers
140. Removal Transfers
141. Report TCCS
142. Report RSKM
143. Unconstrained Paths
144. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
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(including device programming or simulation files), and any 
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to the terms and conditions of the Altera Program License 
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Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; atari800core                                                      ;
; Device Family      ; Cyclone III                                                       ;
; Device Name        ; EP3C25E144C8                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Combined                                                          ;
; Rise/Fall Delays   ; Enabled                                                           ;
+--------------------+-------------------------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 12          ;
; Maximum allowed            ; 6           ;
;                            ;             ;
; Average used               ; 1.62        ;
; Maximum used               ; 6           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-6         ;  12.5%      ;
;     Processors 7-12        ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------+
; SDC File List                                        ;
+------------------+--------+--------------------------+
; SDC File Path    ; Status ; Read at                  ;
+------------------+--------+--------------------------+
; atari800core.sdc ; OK     ; Sun Feb  7 09:46:37 2021 ;
+------------------+--------+--------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+-----------------------------------------------------------------------+-----------+--------+------------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------------------------------------------------------------------+-------------------------------------------------------------------------+---------------------------------------------------------------------------+
; Clock Name                                                            ; Type      ; Period ; Frequency  ; Rise   ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase  ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                                               ; Source                                                                  ; Targets                                                                   ;
+-----------------------------------------------------------------------+-----------+--------+------------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------------------------------------------------------------------+-------------------------------------------------------------------------+---------------------------------------------------------------------------+
; clk_27                                                                ; Base      ; 37.037 ; 27.0 MHz   ; 0.000  ; 18.518 ;            ;           ;             ;        ;        ;           ;            ;          ;                                                                      ;                                                                         ; { CLOCK_27[0] }                                                           ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 8.810  ; 113.51 MHz ; 0.000  ; 4.405  ; 50.00      ; 27        ; 100         ;        ;        ;           ;            ; false    ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] } ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 17.621 ; 56.75 MHz  ; 0.000  ; 8.810  ; 50.00      ; 27        ; 50          ;        ;        ;           ;            ; false    ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] } ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 8.810  ; 113.51 MHz ; -2.447 ; 1.958  ; 50.00      ; 27        ; 100         ; -100.0 ;        ;           ;            ; false    ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] } ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; Generated ; 32.631 ; 30.65 MHz  ; 0.000  ; 16.315 ; 50.00      ; 200       ; 227         ;        ;        ;           ;            ; false    ; clk_27                                                               ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]  ; { pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] }  ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; Generated ; 83.333 ; 12.0 MHz   ; 0.000  ; 41.666 ; 50.00      ; 9         ; 4           ;        ;        ;           ;            ; false    ; clk_27                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]              ; { reconfig_pll|altpll_component|auto_generated|pll1|clk[0] }              ;
; SPI_SCK                                                               ; Base      ; 41.666 ; 24.0 MHz   ; 20.800 ; 41.666 ;            ;           ;             ;        ;        ;           ;            ;          ;                                                                      ;                                                                         ; { SPI_SCK }                                                               ;
+-----------------------------------------------------------------------+-----------+--------+------------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------------------------------------------------------------------+-------------------------------------------------------------------------+---------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                                                                   ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                            ; Note                                                          ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
; 58.01 MHz  ; 58.01 MHz       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                               ;
; 67.57 MHz  ; 67.57 MHz       ; SPI_SCK                                                               ;                                                               ;
; 98.16 MHz  ; 98.16 MHz       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ;                                                               ;
; 148.54 MHz ; 148.54 MHz      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                               ;
; 342.35 MHz ; 250.0 MHz       ; clk_27                                                                ; limit due to minimum period restriction (max I/O toggle rate) ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                            ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.593 ; -1.593        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.382  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.945  ; 0.000         ;
; SPI_SCK                                                               ; 13.455 ; 0.000         ;
; clk_27                                                                ; 34.116 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 36.573 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                            ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.398 ; 0.000         ;
; SPI_SCK                                                               ; 0.448 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.454 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 0.454 ; 0.000         ;
; clk_27                                                                ; 0.455 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 2.208 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+-----------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                        ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 3.696 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.990 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+-----------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                         ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.607 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 3.627 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                              ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.094  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 4.194  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.375  ; 0.000         ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 16.275 ; 0.000         ;
; clk_27                                                                ; 18.275 ; 0.000         ;
; SPI_SCK                                                               ; 20.415 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 40.596 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                  ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -1.593 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.958        ; -2.033     ; 1.286      ;
; 2.570  ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                             ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.929      ; 4.112      ;
; 2.571  ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                ; SDRAM_A[5]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.930      ; 4.112      ;
; 2.576  ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                             ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.925      ; 4.102      ;
; 2.576  ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                             ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.925      ; 4.102      ;
; 2.579  ; sdram_statemachine:sdram_adaptor|addr_reg[11]                               ; SDRAM_A[11]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.938      ; 4.112      ;
; 2.583  ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                ; SDRAM_A[7]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.932      ; 4.102      ;
; 2.583  ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                ; SDRAM_A[8]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.932      ; 4.102      ;
; 2.585  ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                ; SDRAM_A[9]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.934      ; 4.102      ;
; 2.588  ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                ; SDRAM_A[6]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.937      ; 4.102      ;
; 2.590  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5                 ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.898      ; 4.061      ;
; 2.590  ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                             ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.939      ; 4.102      ;
; 2.591  ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                              ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.940      ; 4.102      ;
; 2.600  ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.949      ; 4.102      ;
; 2.600  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4                 ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.898      ; 4.051      ;
; 2.601  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6                 ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.899      ; 4.051      ;
; 2.602  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7                 ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.900      ; 4.051      ;
; 2.606  ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                              ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.945      ; 4.092      ;
; 2.606  ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                              ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.945      ; 4.092      ;
; 2.607  ; sdram_statemachine:sdram_adaptor|udqm_reg                                   ; SDRAM_DQMH                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.946      ; 4.092      ;
; 2.609  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.945      ; 4.089      ;
; 2.609  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.945      ; 4.089      ;
; 2.615  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.941      ; 4.079      ;
; 2.615  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.941      ; 4.079      ;
; 2.624  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2                 ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.960      ; 4.089      ;
; 2.624  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3                 ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.960      ; 4.089      ;
; 2.629  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.955      ; 4.079      ;
; 2.629  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.955      ; 4.079      ;
; 2.630  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1                 ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.956      ; 4.079      ;
; 2.639  ; sdram_statemachine:sdram_adaptor|dq_output_reg                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.965      ; 4.079      ;
; 2.645  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9                 ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.961      ; 4.069      ;
; 2.645  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8                 ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.961      ; 4.069      ;
; 2.707  ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                              ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.882      ; 3.928      ;
; 2.717  ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                              ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.882      ; 3.918      ;
; 2.718  ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                ; SDRAM_A[3]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.883      ; 3.918      ;
; 2.718  ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                              ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.883      ; 3.918      ;
; 2.719  ; sdram_statemachine:sdram_adaptor|we_n_reg                                   ; SDRAM_nWE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.884      ; 3.918      ;
; 2.719  ; sdram_statemachine:sdram_adaptor|ldqm_reg                                   ; SDRAM_DQML                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.884      ; 3.918      ;
; 2.719  ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                              ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.884      ; 3.918      ;
; 2.728  ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                ; SDRAM_A[4]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.928      ; 3.953      ;
; 2.729  ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                ; SDRAM_A[1]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.884      ; 3.908      ;
; 2.729  ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                ; SDRAM_A[2]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.884      ; 3.908      ;
; 2.729  ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                             ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.929      ; 3.953      ;
; 2.731  ; sdram_statemachine:sdram_adaptor|addr_reg[10]                               ; SDRAM_A[10]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.886      ; 3.908      ;
; 2.731  ; sdram_statemachine:sdram_adaptor|ba_reg[0]                                  ; SDRAM_BA[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.886      ; 3.908      ;
; 2.731  ; sdram_statemachine:sdram_adaptor|cas_n_reg                                  ; SDRAM_nCAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.886      ; 3.908      ;
; 2.731  ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                ; SDRAM_A[0]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.886      ; 3.908      ;
; 2.732  ; sdram_statemachine:sdram_adaptor|ras_n_reg                                  ; SDRAM_nRAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.887      ; 3.908      ;
; 2.741  ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                  ; SDRAM_BA[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.886      ; 3.898      ;
; 2.744  ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                              ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.944      ; 3.953      ;
; 2.744  ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                              ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.944      ; 3.953      ;
; 2.749  ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                             ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.939      ; 3.943      ;
; 3.618  ; sdram_statemachine:sdram_adaptor|cke_reg                                    ; SDRAM_CKE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.877      ; 3.012      ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                 ; To Node                                                                                                  ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.382 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 17.162     ;
; 0.382 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 17.162     ;
; 0.382 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 17.162     ;
; 0.382 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 17.162     ;
; 0.382 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 17.162     ;
; 0.382 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 17.162     ;
; 0.541 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 17.002     ;
; 0.541 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 17.002     ;
; 0.541 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 17.002     ;
; 0.541 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 17.002     ;
; 0.541 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 17.002     ;
; 0.541 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 17.002     ;
; 0.664 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 16.881     ;
; 0.664 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 16.881     ;
; 0.664 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 16.881     ;
; 0.664 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 16.881     ;
; 0.664 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 16.881     ;
; 0.664 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 16.881     ;
; 0.672 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.123     ; 16.827     ;
; 0.693 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.093     ; 16.836     ;
; 0.693 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.093     ; 16.836     ;
; 0.693 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.093     ; 16.836     ;
; 0.709 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.092     ; 16.821     ;
; 0.709 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.092     ; 16.821     ;
; 0.709 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.092     ; 16.821     ;
; 0.709 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.092     ; 16.821     ;
; 0.739 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.805     ;
; 0.739 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.805     ;
; 0.739 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.805     ;
; 0.739 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.805     ;
; 0.739 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.805     ;
; 0.739 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.805     ;
; 0.751 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 16.798     ;
; 0.751 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 16.798     ;
; 0.751 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 16.798     ;
; 0.751 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 16.798     ;
; 0.753 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.791     ;
; 0.753 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.791     ;
; 0.753 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.791     ;
; 0.753 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.791     ;
; 0.753 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.791     ;
; 0.753 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.791     ;
; 0.831 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.124     ; 16.667     ;
; 0.852 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 16.676     ;
; 0.852 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 16.676     ;
; 0.852 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 16.676     ;
; 0.868 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.093     ; 16.661     ;
; 0.868 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.093     ; 16.661     ;
; 0.868 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.093     ; 16.661     ;
; 0.868 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.093     ; 16.661     ;
; 0.901 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.643     ;
; 0.901 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.643     ;
; 0.901 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.643     ;
; 0.901 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.643     ;
; 0.901 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.643     ;
; 0.901 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.643     ;
; 0.910 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 16.638     ;
; 0.910 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 16.638     ;
; 0.910 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 16.638     ;
; 0.910 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 16.638     ;
; 0.933 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.110     ; 16.579     ;
; 0.933 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.110     ; 16.579     ;
; 0.941 ; DMA_ADDR_FETCH_IOCTL[21]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 16.601     ;
; 0.941 ; DMA_ADDR_FETCH_IOCTL[21]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 16.601     ;
; 0.941 ; DMA_ADDR_FETCH_IOCTL[21]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 16.601     ;
; 0.941 ; DMA_ADDR_FETCH_IOCTL[21]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 16.601     ;
; 0.941 ; DMA_ADDR_FETCH_IOCTL[21]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 16.601     ;
; 0.941 ; DMA_ADDR_FETCH_IOCTL[21]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 16.601     ;
; 0.950 ; DMA_ADDR_FETCH_IOCTL[20]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 16.592     ;
; 0.950 ; DMA_ADDR_FETCH_IOCTL[20]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 16.592     ;
; 0.950 ; DMA_ADDR_FETCH_IOCTL[20]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 16.592     ;
; 0.950 ; DMA_ADDR_FETCH_IOCTL[20]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 16.592     ;
; 0.950 ; DMA_ADDR_FETCH_IOCTL[20]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 16.592     ;
; 0.950 ; DMA_ADDR_FETCH_IOCTL[20]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 16.592     ;
; 0.954 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.122     ; 16.546     ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.580     ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.580     ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.580     ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.580     ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.580     ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.580     ;
; 0.972 ; user_io:my_user_io|but_sw[1]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.564     ;
; 0.972 ; user_io:my_user_io|but_sw[1]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.564     ;
; 0.972 ; user_io:my_user_io|but_sw[1]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.564     ;
; 0.972 ; user_io:my_user_io|but_sw[1]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.564     ;
; 0.972 ; user_io:my_user_io|but_sw[1]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.564     ;
; 0.972 ; user_io:my_user_io|but_sw[1]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.564     ;
; 0.975 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.092     ; 16.555     ;
; 0.975 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.092     ; 16.555     ;
; 0.975 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.092     ; 16.555     ;
; 0.991 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.091     ; 16.540     ;
; 0.991 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.091     ; 16.540     ;
; 0.991 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.091     ; 16.540     ;
; 0.991 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.091     ; 16.540     ;
; 0.997 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.357      ; 16.982     ;
; 1.029 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.123     ; 16.470     ;
; 1.033 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.072     ; 16.517     ;
; 1.033 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.072     ; 16.517     ;
; 1.033 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.072     ; 16.517     ;
; 1.033 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.072     ; 16.517     ;
+-------+-----------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                 ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.945 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.405        ; -2.032     ; 1.286      ;
; 0.957 ; SDRAM_DQ[3]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.428     ; 1.241      ;
; 0.957 ; SDRAM_DQ[2]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.428     ; 1.241      ;
; 0.963 ; SDRAM_DQ[0]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.432     ; 1.231      ;
; 0.971 ; SDRAM_DQ[1]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.424     ; 1.231      ;
; 0.972 ; SDRAM_DQ[15]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.413     ; 1.241      ;
; 0.972 ; SDRAM_DQ[14]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.413     ; 1.241      ;
; 0.973 ; SDRAM_DQ[13]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.422     ; 1.231      ;
; 0.973 ; SDRAM_DQ[12]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.422     ; 1.231      ;
; 0.976 ; SDRAM_DQ[9]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.429     ; 1.221      ;
; 0.976 ; SDRAM_DQ[8]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.429     ; 1.221      ;
; 0.986 ; SDRAM_DQ[11]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.409     ; 1.231      ;
; 0.986 ; SDRAM_DQ[10]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.409     ; 1.231      ;
; 1.006 ; SDRAM_DQ[5]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.369     ; 1.251      ;
; 1.015 ; SDRAM_DQ[7]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.370     ; 1.241      ;
; 1.016 ; SDRAM_DQ[6]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.369     ; 1.241      ;
; 1.016 ; SDRAM_DQ[4]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.369     ; 1.241      ;
; 2.078 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.180     ; 6.423      ;
; 2.206 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 6.296      ;
; 2.211 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.120     ; 6.350      ;
; 2.217 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.180     ; 6.284      ;
; 2.247 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|cas_n_reg                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.119     ; 6.315      ;
; 2.258 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.119     ; 6.304      ;
; 2.267 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.169     ; 6.245      ;
; 2.282 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 6.278      ;
; 2.304 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.117     ; 6.260      ;
; 2.306 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.119     ; 6.256      ;
; 2.310 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.117     ; 6.254      ;
; 2.311 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.169     ; 6.201      ;
; 2.317 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.123     ; 6.241      ;
; 2.321 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.117     ; 6.243      ;
; 2.326 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 6.182      ;
; 2.342 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.180     ; 6.159      ;
; 2.344 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.116     ; 6.221      ;
; 2.344 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 6.216      ;
; 2.345 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 6.157      ;
; 2.350 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.120     ; 6.211      ;
; 2.351 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.117     ; 6.213      ;
; 2.361 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.119     ; 6.201      ;
; 2.369 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 6.191      ;
; 2.370 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.169     ; 6.142      ;
; 2.385 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.165     ; 6.131      ;
; 2.405 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 6.155      ;
; 2.407 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.117     ; 6.157      ;
; 2.410 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.163     ; 6.108      ;
; 2.413 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.117     ; 6.151      ;
; 2.433 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.165     ; 6.083      ;
; 2.433 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.167     ; 6.081      ;
; 2.443 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.116     ; 6.122      ;
; 2.444 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.169     ; 6.068      ;
; 2.446 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.163     ; 6.072      ;
; 2.461 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.116     ; 6.104      ;
; 2.468 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.169     ; 6.044      ;
; 2.470 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 6.032      ;
; 2.475 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.120     ; 6.086      ;
; 2.477 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|cas_n_reg                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.119     ; 6.085      ;
; 2.478 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.117     ; 6.086      ;
; 2.482 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.120     ; 6.079      ;
; 2.484 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.120     ; 6.077      ;
; 2.488 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.165     ; 6.028      ;
; 2.492 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.119     ; 6.070      ;
; 2.498 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.163     ; 6.020      ;
; 2.506 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 6.222      ;
; 2.506 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 6.222      ;
; 2.506 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 6.222      ;
; 2.506 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 6.222      ;
; 2.506 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 6.222      ;
; 2.506 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 6.222      ;
; 2.506 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 6.222      ;
; 2.506 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 6.222      ;
; 2.506 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 6.222      ;
; 2.506 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 6.222      ;
; 2.506 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 6.222      ;
; 2.506 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 6.222      ;
; 2.508 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.117     ; 6.056      ;
; 2.545 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.120     ; 6.016      ;
; 2.546 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.116     ; 6.019      ;
; 2.561 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 5.947      ;
; 2.563 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.123     ; 5.995      ;
; 2.563 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 5.997      ;
; 2.567 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.163     ; 5.951      ;
; 2.569 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.154     ; 5.958      ;
; 2.571 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 5.989      ;
; 2.580 ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[3]                         ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.211     ; 5.890      ;
; 2.588 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 5.914      ;
; 2.590 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.175     ; 5.916      ;
; 2.601 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 5.959      ;
; 2.606 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.160     ; 5.915      ;
; 2.616 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.165     ; 5.900      ;
; 2.621 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.120     ; 5.940      ;
; 2.623 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.119     ; 5.939      ;
; 2.629 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.145     ; 5.907      ;
; 2.632 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.169     ; 5.880      ;
; 2.640 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|cas_n_reg                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.119     ; 5.922      ;
; 2.660 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.167     ; 5.854      ;
; 2.684 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.120     ; 5.877      ;
; 2.690 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.169     ; 5.822      ;
; 2.707 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 6.021      ;
; 2.707 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 6.021      ;
; 2.707 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 6.021      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'SPI_SCK'                                                                                                                ;
+--------+--------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                      ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 13.455 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 7.433      ;
; 13.455 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 7.433      ;
; 13.455 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 7.433      ;
; 13.455 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 7.433      ;
; 13.455 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 7.433      ;
; 13.583 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 7.305      ;
; 13.618 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 7.270      ;
; 13.618 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 7.270      ;
; 13.618 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 7.270      ;
; 13.618 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 7.270      ;
; 13.618 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 7.270      ;
; 13.695 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 7.193      ;
; 13.695 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 7.193      ;
; 13.695 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 7.193      ;
; 13.695 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 7.193      ;
; 13.695 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 7.193      ;
; 13.746 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 7.142      ;
; 13.823 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 7.065      ;
; 13.980 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 6.908      ;
; 13.980 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 6.908      ;
; 13.980 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 6.908      ;
; 13.980 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 6.908      ;
; 13.980 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 6.908      ;
; 14.108 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 6.780      ;
; 14.741 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 6.147      ;
; 14.741 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 6.147      ;
; 14.741 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 6.147      ;
; 14.741 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 6.147      ;
; 14.741 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 6.147      ;
; 14.856 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 6.032      ;
; 14.856 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 6.032      ;
; 14.856 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 6.032      ;
; 14.856 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 6.032      ;
; 14.856 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 6.032      ;
; 14.869 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 6.019      ;
; 14.984 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 5.904      ;
; 15.154 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.017      ; 5.730      ;
; 15.154 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.017      ; 5.730      ;
; 15.154 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.017      ; 5.730      ;
; 15.154 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.017      ; 5.730      ;
; 15.154 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.017      ; 5.730      ;
; 15.214 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 5.674      ;
; 15.214 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 5.674      ;
; 15.214 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 5.674      ;
; 15.214 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 5.674      ;
; 15.214 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 5.674      ;
; 15.315 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.017      ; 5.569      ;
; 15.342 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 5.546      ;
; 15.360 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.017      ; 5.524      ;
; 15.360 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.017      ; 5.524      ;
; 15.360 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.017      ; 5.524      ;
; 15.360 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.017      ; 5.524      ;
; 15.360 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.017      ; 5.524      ;
; 15.521 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.017      ; 5.363      ;
; 15.635 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.017      ; 5.249      ;
; 15.635 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.017      ; 5.249      ;
; 15.635 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.017      ; 5.249      ;
; 15.635 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.017      ; 5.249      ;
; 15.635 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.017      ; 5.249      ;
; 15.796 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.017      ; 5.088      ;
; 15.811 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 5.077      ;
; 15.811 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 5.077      ;
; 15.811 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 5.077      ;
; 15.811 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 5.077      ;
; 15.811 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 5.077      ;
; 15.854 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.996      ;
; 15.854 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.996      ;
; 15.854 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.996      ;
; 15.854 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.996      ;
; 15.854 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.996      ;
; 15.863 ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.987      ;
; 15.863 ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.987      ;
; 15.863 ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.987      ;
; 15.863 ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.987      ;
; 15.863 ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.987      ;
; 15.972 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 4.916      ;
; 16.015 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.835      ;
; 16.024 ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.826      ;
; 16.075 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.775      ;
; 16.075 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.775      ;
; 16.075 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.775      ;
; 16.075 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.775      ;
; 16.075 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.775      ;
; 16.082 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 4.806      ;
; 16.082 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 4.806      ;
; 16.082 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 4.806      ;
; 16.082 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 4.806      ;
; 16.082 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 4.806      ;
; 16.179 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.671      ;
; 16.179 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.671      ;
; 16.179 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.671      ;
; 16.179 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.671      ;
; 16.179 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.671      ;
; 16.236 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.614      ;
; 16.243 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 4.645      ;
; 16.340 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.017     ; 4.510      ;
; 16.425 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 4.463      ;
; 16.425 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 4.463      ;
; 16.425 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 4.463      ;
; 16.425 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.021      ; 4.463      ;
+--------+--------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'clk_27'                                                                                                                                                                ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 34.116 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.843      ;
; 34.159 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.800      ;
; 34.264 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.695      ;
; 34.266 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.693      ;
; 34.297 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.662      ;
; 34.303 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.656      ;
; 34.307 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.652      ;
; 34.392 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.567      ;
; 34.397 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.562      ;
; 34.414 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.545      ;
; 34.441 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.518      ;
; 34.451 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.508      ;
; 34.456 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.503      ;
; 34.531 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.428      ;
; 34.540 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.419      ;
; 34.556 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.403      ;
; 34.587 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.372      ;
; 34.594 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.365      ;
; 34.674 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.285      ;
; 34.677 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.282      ;
; 34.687 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.272      ;
; 34.854 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.105      ;
; 34.857 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.102      ;
; 34.879 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.080      ;
; 34.879 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.080      ;
; 34.892 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.067      ;
; 34.919 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.040      ;
; 34.920 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.039      ;
; 34.929 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.030      ;
; 34.930 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.029      ;
; 34.957 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.002      ;
; 34.976 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.983      ;
; 35.001 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.958      ;
; 35.030 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.929      ;
; 35.033 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.926      ;
; 35.052 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.907      ;
; 35.056 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.903      ;
; 35.056 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.903      ;
; 35.068 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.891      ;
; 35.091 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.868      ;
; 35.107 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.852      ;
; 35.122 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.837      ;
; 35.126 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.833      ;
; 35.216 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.743      ;
; 35.218 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.741      ;
; 35.226 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.733      ;
; 35.232 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.727      ;
; 35.232 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.727      ;
; 35.256 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.703      ;
; 35.261 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.698      ;
; 35.291 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.668      ;
; 35.403 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.556      ;
; 35.416 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.543      ;
; 35.420 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.539      ;
; 35.420 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.539      ;
; 35.587 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.372      ;
; 35.679 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.280      ;
; 35.681 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.278      ;
; 35.710 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.249      ;
; 36.101 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 0.858      ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 36.573 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_we_reg ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.803     ; 6.682      ;
; 37.451 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.096      ; 8.313      ;
; 39.023 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.111      ; 6.756      ;
; 39.071 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.111      ; 6.708      ;
; 39.152 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.405     ; 4.501      ;
; 39.155 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.405     ; 4.498      ;
; 39.213 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.111      ; 6.566      ;
; 39.381 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.405     ; 4.272      ;
; 39.525 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.405     ; 4.128      ;
; 39.582 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.400     ; 4.076      ;
; 39.620 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.405     ; 4.033      ;
; 39.724 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.410     ; 3.924      ;
; 39.856 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.400     ; 3.802      ;
; 40.041 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.400     ; 3.617      ;
; 40.189 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.400     ; 3.469      ;
; 40.453 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate3_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.122     ; 1.092      ;
; 40.940 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.400     ; 2.718      ;
; 41.171 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                             ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.408     ; 2.479      ;
; 75.751 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.097     ; 7.486      ;
; 76.093 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.095     ; 7.146      ;
; 77.228 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 6.024      ;
; 77.238 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 6.014      ;
; 77.371 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 5.881      ;
; 77.584 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 5.670      ;
; 77.594 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 5.660      ;
; 77.727 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 5.527      ;
; 77.825 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                                                 ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.318      ; 5.874      ;
; 77.825 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                                                 ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.318      ; 5.874      ;
; 77.981 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                                                ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.318      ; 5.718      ;
; 77.981 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                                                ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.318      ; 5.718      ;
; 78.076 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.321      ; 5.626      ;
; 78.076 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.321      ; 5.626      ;
; 78.078 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.321      ; 5.624      ;
; 78.078 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.321      ; 5.624      ;
; 78.087 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.321      ; 5.615      ;
; 78.087 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.321      ; 5.615      ;
; 78.263 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.321      ; 5.439      ;
; 78.263 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.321      ; 5.439      ;
; 78.318 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.321      ; 5.384      ;
; 78.318 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.321      ; 5.384      ;
; 78.394 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.318      ; 5.305      ;
; 78.394 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.318      ; 5.305      ;
; 78.406 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.077     ; 4.851      ;
; 78.412 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.321      ; 5.290      ;
; 78.412 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.321      ; 5.290      ;
; 78.413 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.331      ; 5.299      ;
; 78.420 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.077     ; 4.837      ;
; 78.503 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.321      ; 5.199      ;
; 78.503 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.321      ; 5.199      ;
; 78.527 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_last_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.317      ; 5.171      ;
; 78.634 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.331      ; 5.078      ;
; 78.653 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.321      ; 5.049      ;
; 78.653 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.321      ; 5.049      ;
; 78.706 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.077     ; 4.551      ;
; 78.728 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.077     ; 4.529      ;
; 78.744 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.510      ;
; 78.744 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.510      ;
; 78.744 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.510      ;
; 78.744 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.510      ;
; 78.744 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.510      ;
; 78.744 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.510      ;
; 78.744 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.510      ;
; 78.744 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.510      ;
; 78.749 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.077     ; 4.508      ;
; 78.770 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.077     ; 4.487      ;
; 78.780 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.077     ; 4.477      ;
; 78.781 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.077     ; 4.476      ;
; 78.784 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.077     ; 4.473      ;
; 78.870 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.384      ;
; 78.870 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.384      ;
; 78.870 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.384      ;
; 78.870 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.384      ;
; 78.870 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.384      ;
; 78.870 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.384      ;
; 78.870 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.384      ;
; 78.870 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.384      ;
; 78.889 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.365      ;
; 78.889 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.365      ;
; 78.889 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.365      ;
; 78.889 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.365      ;
; 78.889 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.365      ;
; 78.889 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.365      ;
; 78.889 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.365      ;
; 78.889 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.365      ;
; 78.924 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.094     ; 4.316      ;
; 78.924 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.094     ; 4.316      ;
; 78.924 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.094     ; 4.316      ;
; 78.924 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.094     ; 4.316      ;
; 78.924 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.094     ; 4.316      ;
; 78.924 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.094     ; 4.316      ;
; 78.924 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.094     ; 4.316      ;
; 78.924 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.094     ; 4.316      ;
; 78.966 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.093     ; 4.275      ;
; 78.992 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.077     ; 4.265      ;
; 79.001 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.093     ; 4.240      ;
; 79.003 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.075     ; 4.256      ;
; 79.006 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.315      ; 4.690      ;
; 79.028 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.226      ;
; 79.028 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.226      ;
; 79.028 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.226      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                 ; To Node                                                                                                                                                                                                                                 ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.398 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[1]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.132      ;
; 0.398 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[7]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.131      ;
; 0.399 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[7]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.132      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[0]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.485      ; 1.142      ;
; 0.404 ; zpu_secbuf_addr[4]                                                                                                                                                                                        ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.475      ; 1.133      ;
; 0.404 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[3]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.137      ;
; 0.405 ; user_io:my_user_io|sd_dout[1]                                                                                                                                                                             ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.137      ;
; 0.405 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[1]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.485      ; 1.144      ;
; 0.407 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[0]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.140      ;
; 0.408 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[6]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.144      ;
; 0.411 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[4]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.147      ;
; 0.411 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[6]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.143      ;
; 0.412 ; zpu_secbuf_addr[0]                                                                                                                                                                                        ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.475      ; 1.141      ;
; 0.414 ; user_io:my_user_io|sd_dout[0]                                                                                                                                                                             ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.146      ;
; 0.414 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[3]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.150      ;
; 0.415 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[2]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.149      ;
; 0.416 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[3]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.152      ;
; 0.417 ; zpu_secbuf_d[7]                                                                                                                                                                                           ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.483      ; 1.154      ;
; 0.417 ; user_io:my_user_io|sd_dout[2]                                                                                                                                                                             ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.149      ;
; 0.417 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[7]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.151      ;
; 0.420 ; zpu_secbuf_d[2]                                                                                                                                                                                           ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.154      ;
; 0.420 ; user_io:my_user_io|sd_dout[5]                                                                                                                                                                             ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.152      ;
; 0.420 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[6]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.485      ; 1.159      ;
; 0.423 ; user_io:my_user_io|sd_dout[7]                                                                                                                                                                             ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.155      ;
; 0.423 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[6]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.156      ;
; 0.425 ; zpu_secbuf_addr[1]                                                                                                                                                                                        ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.470      ; 1.149      ;
; 0.426 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[4]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.160      ;
; 0.427 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[3]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.161      ;
; 0.430 ; user_io:my_user_io|sd_dout[6]                                                                                                                                                                             ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.162      ;
; 0.434 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[0]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[0]                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[1]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[1]                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[2]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.167      ;
; 0.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[1]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.171      ;
; 0.442 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[1]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.483      ; 1.179      ;
; 0.442 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[4]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.174      ;
; 0.443 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[4]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.179      ;
; 0.444 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[6]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.180      ;
; 0.445 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[4]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.178      ;
; 0.446 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[2]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[2]                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.758      ;
; 0.446 ; user_io:my_user_io|sd_buff_addr[0]                                                                                                                                                                        ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.471      ; 1.171      ;
; 0.447 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[6] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_address_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.474      ; 1.175      ;
; 0.447 ; zpu_secbuf_addr[5]                                                                                                                                                                                        ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.473      ; 1.174      ;
; 0.447 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[7]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.179      ;
; 0.448 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[7] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_address_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.474      ; 1.176      ;
; 0.448 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[3]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.181      ;
; 0.449 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_datain_reg0           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.483      ; 1.186      ;
; 0.449 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[5]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.181      ;
; 0.450 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[2]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.488      ; 1.192      ;
; 0.452 ; zpu_secbuf_addr[6]                                                                                                                                                                                        ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.475      ; 1.181      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[102]                                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[102]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[44]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[44]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; user_io:my_user_io|joystick_0[0]                                                                                                                                                                          ; user_io:my_user_io|joystick_0[0]                                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; user_io:my_user_io|joystick_1[0]                                                                                                                                                                          ; user_io:my_user_io|joystick_1[0]                                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[2]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[2]                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; user_io:my_user_io|status[15]                                                                                                                                                                             ; user_io:my_user_io|status[15]                                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; user_io:my_user_io|status[23]                                                                                                                                                                             ; user_io:my_user_io|status[23]                                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; user_io:my_user_io|status[0]                                                                                                                                                                              ; user_io:my_user_io|status[0]                                                                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[7]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.189      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.ready                                                                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.ready                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.command                                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.command                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|busy                                                                                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|busy                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|scl_ena                                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|scl_ena                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|scl_ena                                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|scl_ena                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; data_io:mist_data_io|abyte_cnt[1]                                                                                                                                                                         ; data_io:mist_data_io|abyte_cnt[1]                                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; data_io:mist_data_io|abyte_cnt[2]                                                                                                                                                                         ; data_io:mist_data_io|abyte_cnt[2]                                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; data_io:mist_data_io|abyte_cnt[0]                                                                                                                                                                         ; data_io:mist_data_io|abyte_cnt[0]                                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; data_io:mist_data_io|hi                                                                                                                                                                                   ; data_io:mist_data_io|hi                                                                                                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ioctl_state.IOCTL_ACK                                                                                                                                                                                     ; ioctl_state.IOCTL_ACK                                                                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[9]                                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[9]                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ioctl_state.IOCTL_UNLOAD                                                                                                                                                                                  ; ioctl_state.IOCTL_UNLOAD                                                                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[118]                                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[118]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ZPU_IN1[30]                                                                                                                                                                                               ; ZPU_IN1[30]                                                                                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'SPI_SCK'                                                                                                                                                                                              ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                  ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.448 ; osd:osd_inst|sbuf[2]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.483      ; 1.185      ;
; 0.454 ; data_io:mist_data_io|bit_cnt[1]            ; data_io:mist_data_io|bit_cnt[1]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; data_io:mist_data_io|bit_cnt[2]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|cmd[2]                  ; user_io:my_user_io|cmd[2]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|cmd[0]                  ; user_io:my_user_io|cmd[0]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|cmd[4]                  ; user_io:my_user_io|cmd[4]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|cmd[5]                  ; user_io:my_user_io|cmd[5]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|cmd[3]                  ; user_io:my_user_io|cmd[3]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|cmd[6]                  ; user_io:my_user_io|cmd[6]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|cmd[7]                  ; user_io:my_user_io|cmd[7]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.455 ; user_io:my_user_io|bit_cnt[1]              ; user_io:my_user_io|bit_cnt[1]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; user_io:my_user_io|bit_cnt[2]              ; user_io:my_user_io|bit_cnt[2]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; osd:osd_inst|osd_enable                    ; osd:osd_inst|osd_enable                                                                                 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; user_io:my_user_io|byte_cnt[0]             ; user_io:my_user_io|byte_cnt[0]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; user_io:my_user_io|cmd[1]                  ; user_io:my_user_io|cmd[1]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; user_io:my_user_io|serial_out_rptr[0]      ; user_io:my_user_io|serial_out_rptr[0]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.746      ;
; 0.456 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.486      ; 1.196      ;
; 0.456 ; osd:osd_inst|sbuf[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.481      ; 1.191      ;
; 0.457 ; osd:osd_inst|bcnt[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.475      ; 1.186      ;
; 0.465 ; osd:osd_inst|bcnt[6]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.475      ; 1.194      ;
; 0.466 ; user_io:my_user_io|spi_receiver_strobe_r   ; user_io:my_user_io|spi_receiver_strobe_r                                                                ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.758      ;
; 0.466 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[0]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.758      ;
; 0.466 ; data_io:mist_data_io|spi_receiver_strobe_r ; data_io:mist_data_io|spi_receiver_strobe_r                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.758      ;
; 0.467 ; user_io:my_user_io|bit_cnt[0]              ; user_io:my_user_io|bit_cnt[0]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.758      ;
; 0.467 ; osd:osd_inst|bcnt[8]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.472      ; 1.193      ;
; 0.476 ; osd:osd_inst|bcnt[8]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.475      ; 1.205      ;
; 0.476 ; osd:osd_inst|bcnt[0]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.472      ; 1.202      ;
; 0.484 ; osd:osd_inst|sbuf[6]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.486      ; 1.224      ;
; 0.485 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.486      ; 1.225      ;
; 0.495 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.472      ; 1.221      ;
; 0.496 ; osd:osd_inst|bcnt[3]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.475      ; 1.225      ;
; 0.503 ; osd:osd_inst|cnt[4]                        ; osd:osd_inst|cnt[4]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.794      ;
; 0.505 ; data_io:mist_data_io|sbuf[6]               ; data_io:mist_data_io|spi_byte_in[7]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.796      ;
; 0.505 ; osd:osd_inst|bcnt[7]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.472      ; 1.231      ;
; 0.508 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.486      ; 1.248      ;
; 0.511 ; data_io:mist_data_io|sbuf[1]               ; data_io:mist_data_io|spi_byte_in[2]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.802      ;
; 0.512 ; data_io:mist_data_io|sbuf[2]               ; data_io:mist_data_io|sbuf[3]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.803      ;
; 0.512 ; data_io:mist_data_io|sbuf[3]               ; data_io:mist_data_io|sbuf[4]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.803      ;
; 0.512 ; data_io:mist_data_io|sbuf[4]               ; data_io:mist_data_io|spi_byte_in[5]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.803      ;
; 0.512 ; data_io:mist_data_io|sbuf[4]               ; data_io:mist_data_io|sbuf[5]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.803      ;
; 0.512 ; data_io:mist_data_io|sbuf[5]               ; data_io:mist_data_io|sbuf[6]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.803      ;
; 0.512 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[1]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.804      ;
; 0.512 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.804      ;
; 0.513 ; data_io:mist_data_io|sbuf[3]               ; data_io:mist_data_io|spi_byte_in[4]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.804      ;
; 0.513 ; data_io:mist_data_io|sbuf[5]               ; data_io:mist_data_io|spi_byte_in[6]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.804      ;
; 0.514 ; data_io:mist_data_io|sbuf[0]               ; data_io:mist_data_io|sbuf[1]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.805      ;
; 0.514 ; data_io:mist_data_io|sbuf[1]               ; data_io:mist_data_io|sbuf[2]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.805      ;
; 0.514 ; data_io:mist_data_io|sbuf[2]               ; data_io:mist_data_io|spi_byte_in[3]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.805      ;
; 0.514 ; data_io:mist_data_io|sbuf[0]               ; data_io:mist_data_io|spi_byte_in[1]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.805      ;
; 0.518 ; user_io:my_user_io|sbuf[4]                 ; user_io:my_user_io|sbuf[5]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.810      ;
; 0.519 ; user_io:my_user_io|sbuf[4]                 ; user_io:my_user_io|spi_byte_in[5]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.811      ;
; 0.519 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|spi_byte_in[6]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.811      ;
; 0.520 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|sbuf[6]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.812      ;
; 0.521 ; user_io:my_user_io|bit_cnt[0]              ; user_io:my_user_io|bit_cnt[1]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.812      ;
; 0.524 ; user_io:my_user_io|sbuf[6]                 ; user_io:my_user_io|cmd[7]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.816      ;
; 0.527 ; osd:osd_inst|sbuf[0]                       ; osd:osd_inst|sbuf[1]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.818      ;
; 0.529 ; user_io:my_user_io|bit_cnt[1]              ; user_io:my_user_io|bit_cnt[2]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.820      ;
; 0.535 ; osd:osd_inst|sbuf[2]                       ; osd:osd_inst|sbuf[3]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.826      ;
; 0.539 ; osd:osd_inst|sbuf[2]                       ; osd:osd_inst|cmd[3]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.830      ;
; 0.542 ; user_io:my_user_io|sbuf[2]                 ; user_io:my_user_io|cmd[3]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.834      ;
; 0.543 ; user_io:my_user_io|sbuf[2]                 ; user_io:my_user_io|sbuf[3]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.835      ;
; 0.545 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|sbuf[5]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.836      ;
; 0.545 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|cmd[6]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.836      ;
; 0.545 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|cmd[5]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.836      ;
; 0.546 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|sbuf[6]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.837      ;
; 0.698 ; osd:osd_inst|bcnt[10]                      ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.472      ; 1.424      ;
; 0.714 ; osd:osd_inst|bcnt[2]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.472      ; 1.440      ;
; 0.725 ; user_io:my_user_io|sbuf[1]                 ; user_io:my_user_io|sbuf[2]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.017      ;
; 0.725 ; user_io:my_user_io|sbuf[3]                 ; user_io:my_user_io|sbuf[4]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.017      ;
; 0.732 ; osd:osd_inst|sbuf[6]                       ; osd:osd_inst|cmd[7]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.023      ;
; 0.741 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|cmd[4]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.032      ;
; 0.741 ; osd:osd_inst|bcnt[10]                      ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.475      ; 1.470      ;
; 0.742 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|sbuf[4]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.033      ;
; 0.749 ; user_io:my_user_io|serial_out_rptr[2]      ; user_io:my_user_io|serial_out_rptr[2]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.040      ;
; 0.749 ; user_io:my_user_io|serial_out_rptr[4]      ; user_io:my_user_io|serial_out_rptr[4]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.040      ;
; 0.751 ; user_io:my_user_io|serial_out_rptr[5]      ; user_io:my_user_io|serial_out_rptr[5]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.042      ;
; 0.752 ; user_io:my_user_io|serial_out_rptr[3]      ; user_io:my_user_io|serial_out_rptr[3]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.043      ;
; 0.756 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|cmd[6]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.048      ;
; 0.757 ; data_io:mist_data_io|bit_cnt[1]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.049      ;
; 0.757 ; user_io:my_user_io|sbuf[4]                 ; user_io:my_user_io|cmd[5]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.049      ;
; 0.757 ; osd:osd_inst|cnt[1]                        ; osd:osd_inst|cnt[1]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.048      ;
; 0.761 ; osd:osd_inst|cnt[2]                        ; osd:osd_inst|cnt[2]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.052      ;
; 0.762 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|bcnt[1]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.054      ;
; 0.763 ; osd:osd_inst|bcnt[6]                       ; osd:osd_inst|bcnt[6]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.055      ;
; 0.763 ; osd:osd_inst|bcnt[7]                       ; osd:osd_inst|bcnt[7]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.055      ;
; 0.763 ; osd:osd_inst|bcnt[8]                       ; osd:osd_inst|bcnt[8]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.055      ;
; 0.763 ; osd:osd_inst|bcnt[9]                       ; osd:osd_inst|bcnt[9]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.055      ;
; 0.764 ; osd:osd_inst|bcnt[3]                       ; osd:osd_inst|bcnt[3]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.056      ;
; 0.764 ; osd:osd_inst|bcnt[5]                       ; osd:osd_inst|bcnt[5]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.056      ;
; 0.764 ; user_io:my_user_io|byte_cnt[4]             ; user_io:my_user_io|byte_cnt[4]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.055      ;
; 0.765 ; osd:osd_inst|bcnt[10]                      ; osd:osd_inst|bcnt[10]                                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.057      ;
; 0.766 ; osd:osd_inst|bcnt[2]                       ; osd:osd_inst|bcnt[2]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.058      ;
; 0.766 ; osd:osd_inst|bcnt[4]                       ; osd:osd_inst|bcnt[4]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.058      ;
; 0.769 ; user_io:my_user_io|serial_out_rptr[0]      ; user_io:my_user_io|serial_out_rptr[1]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.060      ;
; 0.770 ; user_io:my_user_io|serial_out_rptr[1]      ; user_io:my_user_io|serial_out_rptr[1]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.061      ;
; 0.772 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.475      ; 1.501      ;
; 0.773 ; user_io:my_user_io|byte_cnt[3]             ; user_io:my_user_io|byte_cnt[3]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.064      ;
; 0.774 ; osd:osd_inst|cnt[3]                        ; osd:osd_inst|cnt[3]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.065      ;
; 0.774 ; osd:osd_inst|sbuf[0]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.481      ; 1.509      ;
; 0.776 ; osd:osd_inst|cnt[0]                        ; osd:osd_inst|cnt[0]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.067      ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                            ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                     ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.454 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.466 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.758      ;
; 0.628 ; sdram_statemachine:sdram_adaptor|request_sreg                 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 1.052      ;
; 0.737 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.029      ;
; 0.740 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.741 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.033      ;
; 0.742 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.034      ;
; 0.742 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.034      ;
; 0.748 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.039      ;
; 0.749 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.749 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.749 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.749 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.749 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.750 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.041      ;
; 0.752 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.043      ;
; 0.752 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.043      ;
; 0.754 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.046      ;
; 0.757 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.049      ;
; 0.758 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.050      ;
; 0.762 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.054      ;
; 0.766 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.057      ;
; 0.771 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.063      ;
; 0.771 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.063      ;
; 0.773 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.065      ;
; 0.773 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.065      ;
; 0.773 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.065      ;
; 0.775 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.067      ;
; 0.776 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.068      ;
; 0.778 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.070      ;
; 0.779 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.071      ;
; 0.780 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.072      ;
; 0.781 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.072      ;
; 0.782 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.074      ;
; 0.788 ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.080      ;
; 0.788 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.080      ;
; 0.790 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.082      ;
; 0.801 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.093      ;
; 1.089 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.381      ;
; 1.090 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.382      ;
; 1.092 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.384      ;
; 1.094 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.386      ;
; 1.094 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.386      ;
; 1.101 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.393      ;
; 1.102 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.394      ;
; 1.103 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.394      ;
; 1.103 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.394      ;
; 1.103 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.394      ;
; 1.103 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.394      ;
; 1.103 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.395      ;
; 1.103 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.395      ;
; 1.109 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.401      ;
; 1.110 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.401      ;
; 1.110 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.402      ;
; 1.110 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.401      ;
; 1.110 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.402      ;
; 1.112 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.404      ;
; 1.112 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.404      ;
; 1.113 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.404      ;
; 1.113 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.404      ;
; 1.116 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.408      ;
; 1.117 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.409      ;
; 1.118 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.410      ;
; 1.119 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.410      ;
; 1.119 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.410      ;
; 1.120 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.411      ;
; 1.122 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.413      ;
; 1.122 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.413      ;
; 1.125 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.416      ;
; 1.126 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.418      ;
; 1.126 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.418      ;
; 1.127 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.419      ;
; 1.127 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.419      ;
; 1.133 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.425      ;
; 1.134 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.426      ;
; 1.134 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.426      ;
; 1.134 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.426      ;
; 1.134 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.425      ;
; 1.136 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.428      ;
; 1.136 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.428      ;
; 1.142 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.434      ;
; 1.143 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.435      ;
; 1.143 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.435      ;
; 1.145 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.437      ;
; 1.145 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.437      ;
; 1.149 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.441      ;
; 1.152 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.444      ;
; 1.158 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.450      ;
; 1.203 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.495      ;
; 1.208 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.500      ;
; 1.223 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.515      ;
; 1.225 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.517      ;
; 1.225 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.517      ;
; 1.234 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.525      ;
; 1.234 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.525      ;
; 1.234 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.526      ;
; 1.234 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.526      ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                     ; To Node                                                                                                                                                                                                                               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.455 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; rom_loaded                                                                                                                                                                                                    ; rom_loaded                                                                                                                                                                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.466 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.758      ;
; 0.492 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.784      ;
; 0.493 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.785      ;
; 0.495 ; rom_loaded                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.786      ;
; 0.504 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                          ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                          ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.795      ;
; 0.509 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.475      ; 1.238      ;
; 0.510 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.802      ;
; 0.527 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_init_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.819      ;
; 0.544 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[6]                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.836      ;
; 0.546 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.837      ;
; 0.554 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.845      ;
; 0.554 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.846      ;
; 0.559 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.850      ;
; 0.559 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.850      ;
; 0.560 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.851      ;
; 0.593 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                               ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.475      ; 1.322      ;
; 0.652 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.944      ;
; 0.653 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.945      ;
; 0.653 ; switch_pal_ntsc:pll_switcher|pll_reconfig_write_from_rom                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.944      ;
; 0.699 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.476      ; 1.429      ;
; 0.700 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[3]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[3]                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.991      ;
; 0.701 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[7]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[7]                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.992      ;
; 0.702 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[4]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[4]                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.993      ;
; 0.702 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[1]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[1]                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.993      ;
; 0.703 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[5]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[5]                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.994      ;
; 0.703 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[0]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[0]                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.994      ;
; 0.708 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.000      ;
; 0.723 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.015      ;
; 0.731 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|tmp_seq_ena_state                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_ena_state                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.023      ;
; 0.737 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.028      ;
; 0.737 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.028      ;
; 0.737 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.028      ;
; 0.737 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.029      ;
; 0.738 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.030      ;
; 0.738 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.030      ;
; 0.739 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.740 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.740 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.741 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.741 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.741 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.033      ;
; 0.741 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.033      ;
; 0.742 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.033      ;
; 0.746 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.746 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.746 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.746 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.747 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.039      ;
; 0.747 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.038      ;
; 0.747 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.039      ;
; 0.748 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.040      ;
; 0.748 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.040      ;
; 0.749 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.041      ;
; 0.749 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.749 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.749 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.041      ;
; 0.749 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.041      ;
; 0.750 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.041      ;
; 0.750 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.041      ;
; 0.751 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.043      ;
; 0.752 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.043      ;
; 0.762 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.054      ;
; 0.762 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.054      ;
; 0.762 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.054      ;
; 0.763 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.055      ;
; 0.763 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.055      ;
; 0.763 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.055      ;
; 0.764 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.056      ;
; 0.765 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.057      ;
; 0.765 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.056      ;
; 0.765 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.057      ;
; 0.765 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.057      ;
; 0.766 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.058      ;
; 0.766 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.058      ;
; 0.767 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.058      ;
; 0.768 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.060      ;
; 0.770 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.062      ;
; 0.773 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.064      ;
; 0.773 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.065      ;
; 0.773 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.065      ;
; 0.774 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.066      ;
; 0.774 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.066      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'clk_27'                                                                                                                                                                ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 0.746      ;
; 0.751 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.042      ;
; 0.751 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.042      ;
; 0.764 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.055      ;
; 0.934 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.225      ;
; 0.952 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.243      ;
; 0.953 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.244      ;
; 1.054 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.345      ;
; 1.077 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.368      ;
; 1.088 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.379      ;
; 1.089 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.380      ;
; 1.091 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.382      ;
; 1.095 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.386      ;
; 1.096 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.387      ;
; 1.103 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.394      ;
; 1.110 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.401      ;
; 1.112 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.403      ;
; 1.119 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.410      ;
; 1.145 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.436      ;
; 1.145 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.436      ;
; 1.155 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.446      ;
; 1.190 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.481      ;
; 1.192 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.483      ;
; 1.233 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.524      ;
; 1.234 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.525      ;
; 1.234 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.525      ;
; 1.236 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.527      ;
; 1.239 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.530      ;
; 1.242 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.533      ;
; 1.243 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.534      ;
; 1.252 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.543      ;
; 1.257 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.548      ;
; 1.258 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.549      ;
; 1.261 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.552      ;
; 1.275 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.566      ;
; 1.276 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.567      ;
; 1.276 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.567      ;
; 1.277 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.568      ;
; 1.285 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.576      ;
; 1.333 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.624      ;
; 1.334 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.625      ;
; 1.335 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.626      ;
; 1.384 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.675      ;
; 1.385 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.676      ;
; 1.412 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.703      ;
; 1.413 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.704      ;
; 1.513 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.804      ;
; 1.514 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.805      ;
; 1.515 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.806      ;
; 1.515 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.806      ;
; 1.516 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.807      ;
; 1.534 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.825      ;
; 1.563 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.854      ;
; 1.564 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.855      ;
; 1.566 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.857      ;
; 1.634 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.925      ;
; 1.635 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.926      ;
; 1.676 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.967      ;
; 1.785 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 2.076      ;
; 1.786 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 2.077      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 2.208 ; sdram_statemachine:sdram_adaptor|cke_reg                                    ; SDRAM_CKE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.231      ; 2.902      ;
; 2.583 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9                 ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.318      ; 3.364      ;
; 2.583 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8                 ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.318      ; 3.364      ;
; 2.590 ; sdram_statemachine:sdram_adaptor|dq_output_reg                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.321      ; 3.374      ;
; 2.598 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1                 ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.313      ; 3.374      ;
; 2.600 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.311      ; 3.374      ;
; 2.600 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.311      ; 3.374      ;
; 2.604 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2                 ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.317      ; 3.384      ;
; 2.604 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3                 ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.317      ; 3.384      ;
; 2.613 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.298      ; 3.374      ;
; 2.613 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.298      ; 3.374      ;
; 2.617 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7                 ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.259      ; 3.339      ;
; 2.618 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6                 ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.258      ; 3.339      ;
; 2.618 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4                 ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.258      ; 3.339      ;
; 2.619 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.302      ; 3.384      ;
; 2.619 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.302      ; 3.384      ;
; 2.628 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5                 ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.258      ; 3.349      ;
; 2.893 ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                  ; SDRAM_BA[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.245      ; 3.601      ;
; 2.901 ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                             ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.295      ; 3.659      ;
; 2.903 ; sdram_statemachine:sdram_adaptor|addr_reg[10]                               ; SDRAM_A[10]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.245      ; 3.611      ;
; 2.903 ; sdram_statemachine:sdram_adaptor|ba_reg[0]                                  ; SDRAM_BA[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.245      ; 3.611      ;
; 2.903 ; sdram_statemachine:sdram_adaptor|ras_n_reg                                  ; SDRAM_nRAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.245      ; 3.611      ;
; 2.903 ; sdram_statemachine:sdram_adaptor|cas_n_reg                                  ; SDRAM_nCAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.245      ; 3.611      ;
; 2.903 ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                ; SDRAM_A[0]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.245      ; 3.611      ;
; 2.905 ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                ; SDRAM_A[1]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.243      ; 3.611      ;
; 2.905 ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                ; SDRAM_A[2]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.243      ; 3.611      ;
; 2.905 ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                              ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.301      ; 3.669      ;
; 2.905 ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                              ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.301      ; 3.669      ;
; 2.915 ; sdram_statemachine:sdram_adaptor|we_n_reg                                   ; SDRAM_nWE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.243      ; 3.621      ;
; 2.915 ; sdram_statemachine:sdram_adaptor|ldqm_reg                                   ; SDRAM_DQML                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.243      ; 3.621      ;
; 2.915 ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                              ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.243      ; 3.621      ;
; 2.916 ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                ; SDRAM_A[3]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.242      ; 3.621      ;
; 2.916 ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                              ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.242      ; 3.621      ;
; 2.916 ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                              ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.242      ; 3.621      ;
; 2.920 ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                ; SDRAM_A[4]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.286      ; 3.669      ;
; 2.920 ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                             ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.286      ; 3.669      ;
; 2.926 ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                              ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.242      ; 3.631      ;
; 3.029 ; sdram_statemachine:sdram_adaptor|udqm_reg                                   ; SDRAM_DQMH                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.303      ; 3.795      ;
; 3.030 ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                              ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.302      ; 3.795      ;
; 3.030 ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                              ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.302      ; 3.795      ;
; 3.037 ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.305      ; 3.805      ;
; 3.045 ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                              ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.297      ; 3.805      ;
; 3.047 ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                             ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.295      ; 3.805      ;
; 3.049 ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                ; SDRAM_A[6]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.293      ; 3.805      ;
; 3.051 ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                ; SDRAM_A[9]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.291      ; 3.805      ;
; 3.053 ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                ; SDRAM_A[7]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.289      ; 3.805      ;
; 3.053 ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                ; SDRAM_A[8]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.289      ; 3.805      ;
; 3.057 ; sdram_statemachine:sdram_adaptor|addr_reg[11]                               ; SDRAM_A[11]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.295      ; 3.815      ;
; 3.060 ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                             ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.282      ; 3.805      ;
; 3.060 ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                             ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.282      ; 3.805      ;
; 3.064 ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                ; SDRAM_A[5]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.288      ; 3.815      ;
; 3.066 ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                             ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.286      ; 3.815      ;
; 9.468 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -6.853       ; -1.748     ; 1.078      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                      ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 3.696 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.327     ; 4.646      ;
; 3.696 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.326     ; 4.647      ;
; 3.696 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.326     ; 4.647      ;
; 3.696 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.326     ; 4.647      ;
; 3.698 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.386     ; 4.585      ;
; 3.698 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.386     ; 4.585      ;
; 3.698 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.389     ; 4.582      ;
; 3.699 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.370     ; 4.600      ;
; 3.699 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.370     ; 4.600      ;
; 3.706 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.379     ; 4.584      ;
; 3.706 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.379     ; 4.584      ;
; 3.709 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.250     ; 4.722      ;
; 3.712 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.381     ; 4.576      ;
; 3.717 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.385     ; 4.567      ;
; 3.717 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.385     ; 4.567      ;
; 3.718 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.366     ; 4.585      ;
; 3.718 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.366     ; 4.585      ;
; 3.720 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.243     ; 4.718      ;
; 3.721 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.245     ; 4.715      ;
; 3.721 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.252     ; 4.708      ;
; 3.722 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.248     ; 4.711      ;
; 3.727 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.202     ; 4.752      ;
; 3.728 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.246     ; 4.707      ;
; 3.728 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.246     ; 4.707      ;
; 3.729 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.199     ; 4.753      ;
; 3.729 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.199     ; 4.753      ;
; 3.729 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.199     ; 4.753      ;
; 3.729 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.200     ; 4.752      ;
; 3.729 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.202     ; 4.750      ;
; 3.729 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.202     ; 4.750      ;
; 3.729 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.200     ; 4.752      ;
; 3.729 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.200     ; 4.752      ;
; 3.729 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.202     ; 4.750      ;
; 3.729 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.200     ; 4.752      ;
; 3.729 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.200     ; 4.752      ;
; 3.729 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.199     ; 4.753      ;
; 3.729 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.202     ; 4.750      ;
; 3.730 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.202     ; 4.749      ;
; 3.731 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.262     ; 4.688      ;
; 3.731 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.259     ; 4.691      ;
; 3.731 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.259     ; 4.691      ;
; 3.731 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|udqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.260     ; 4.690      ;
; 3.732 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.243     ; 4.706      ;
; 3.732 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.243     ; 4.706      ;
; 3.739 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.252     ; 4.690      ;
; 3.739 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.252     ; 4.690      ;
; 3.745 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.254     ; 4.682      ;
; 3.750 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.258     ; 4.673      ;
; 3.750 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.258     ; 4.673      ;
; 3.751 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.239     ; 4.691      ;
; 3.751 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.239     ; 4.691      ;
; 3.931 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 4.499      ;
; 3.931 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 4.499      ;
; 3.931 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 4.499      ;
; 3.931 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.216     ; 4.498      ;
; 3.933 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.278     ; 4.434      ;
; 3.933 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.275     ; 4.437      ;
; 3.933 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.275     ; 4.437      ;
; 3.934 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.259     ; 4.452      ;
; 3.934 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.259     ; 4.452      ;
; 3.941 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.268     ; 4.436      ;
; 3.941 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.268     ; 4.436      ;
; 3.947 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.270     ; 4.428      ;
; 3.952 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.274     ; 4.419      ;
; 3.952 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.274     ; 4.419      ;
; 3.953 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.255     ; 4.437      ;
; 3.953 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.255     ; 4.437      ;
; 4.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.207     ; 4.353      ;
; 4.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 4.357      ;
; 4.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 4.357      ;
; 4.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 4.357      ;
; 4.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 4.357      ;
; 4.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 4.357      ;
; 4.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 4.357      ;
; 4.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 4.357      ;
; 4.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 4.357      ;
; 4.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 4.357      ;
; 4.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.207     ; 4.353      ;
; 4.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.207     ; 4.353      ;
; 4.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.207     ; 4.353      ;
; 4.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 4.357      ;
; 4.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 4.357      ;
; 4.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 4.357      ;
; 4.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 4.357      ;
; 4.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 4.357      ;
; 4.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 4.357      ;
; 4.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 4.357      ;
; 4.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.207     ; 4.353      ;
; 4.251 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.207     ; 4.353      ;
; 4.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.191     ; 4.355      ;
; 4.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.191     ; 4.355      ;
; 4.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.191     ; 4.355      ;
; 4.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.191     ; 4.355      ;
; 4.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.191     ; 4.355      ;
; 4.268 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.182     ; 4.361      ;
; 4.268 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.182     ; 4.361      ;
; 4.268 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.182     ; 4.361      ;
; 4.268 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.182     ; 4.361      ;
; 4.268 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.182     ; 4.361      ;
; 4.268 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.182     ; 4.361      ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                         ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 8.990 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 8.446      ;
; 8.990 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.195     ; 8.437      ;
; 8.990 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.195     ; 8.437      ;
; 8.990 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.195     ; 8.437      ;
; 9.027 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.182     ; 8.413      ;
; 9.027 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.182     ; 8.413      ;
; 9.027 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.182     ; 8.413      ;
; 9.027 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.182     ; 8.413      ;
; 9.027 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[20]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.182     ; 8.413      ;
; 9.037 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 8.401      ;
; 9.037 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 8.401      ;
; 9.037 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_32BIT_WRITE_ENABLE_reg                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 8.401      ;
; 9.040 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.191     ; 8.391      ;
; 9.040 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.191     ; 8.391      ;
; 9.082 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 8.355      ;
; 9.082 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 8.355      ;
; 9.082 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 8.355      ;
; 9.082 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 8.355      ;
; 9.393 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.108     ; 8.121      ;
; 9.393 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.108     ; 8.121      ;
; 9.393 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.108     ; 8.121      ;
; 9.412 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 8.130      ;
; 9.443 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.104     ; 8.075      ;
; 9.443 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.104     ; 8.075      ;
; 9.449 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.076     ; 8.097      ;
; 9.449 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.076     ; 8.097      ;
; 9.449 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.076     ; 8.097      ;
; 9.449 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.076     ; 8.097      ;
; 9.449 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[20]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.076     ; 8.097      ;
; 9.456 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.280      ; 8.446      ;
; 9.458 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.273      ; 8.437      ;
; 9.459 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 8.085      ;
; 9.459 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 8.085      ;
; 9.459 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_32BIT_WRITE_ENABLE_reg                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 8.085      ;
; 9.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[3]                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.188     ; 7.935      ;
; 9.502 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.206     ; 7.914      ;
; 9.502 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[13]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.206     ; 7.914      ;
; 9.502 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[8]                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.206     ; 7.914      ;
; 9.502 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.206     ; 7.914      ;
; 9.502 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[12]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.206     ; 7.914      ;
; 9.502 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[14]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.206     ; 7.914      ;
; 9.502 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[15]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.206     ; 7.914      ;
; 9.502 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.206     ; 7.914      ;
; 9.504 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 8.039      ;
; 9.504 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 8.039      ;
; 9.504 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 8.039      ;
; 9.504 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 8.039      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.187     ; 7.924      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[16] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[12] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_safe_reg                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.178     ; 7.933      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.178     ; 7.933      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[1]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[2]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[3]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[4]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[5]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[6]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[7]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[8]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[9]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[10]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[11]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[12]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[13]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[14]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[15]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[16]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[17]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[18]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[19]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[20]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[21]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[22]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[23]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[24]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[25]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[26]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[27]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[26]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.935      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.927      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.927      ;
; 9.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[10]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.177     ; 7.934      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.607 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|dffe4                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 2.249      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a39 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a38 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a37 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a36 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a35 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a34 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a33 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a32 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a27 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a26 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a25 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a24 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 2.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.410      ; 3.578      ;
; 3.148 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[0]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.678      ; 4.038      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a63 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a62 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a61 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a60 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a59 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a58 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a57 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a56 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a55 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a54 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a53 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a52 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a51 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a50 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a49 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a48 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a47 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a46 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a45 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a44 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a43 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a42 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a41 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a40 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a31 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a29 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a28 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a23 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a22 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a21 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a20 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a19 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a18 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a17 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.419      ; 3.901      ;
; 3.601 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[2]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.692      ; 4.505      ;
; 3.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; paddle_mode_reg                                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.209      ; 4.051      ;
; 3.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[6]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.680      ; 4.522      ;
; 3.633 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[26]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.203      ; 4.048      ;
; 3.633 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[18]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.203      ; 4.048      ;
; 3.633 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[29]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.203      ; 4.048      ;
; 3.633 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[30]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.203      ; 4.048      ;
; 3.633 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[20]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.203      ; 4.048      ;
; 3.633 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[3]                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.204      ; 4.049      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[14]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 4.052      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[13]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.204      ; 4.051      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[14]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.204      ; 4.051      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[15]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.204      ; 4.051      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[16]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.204      ; 4.051      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[17]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.204      ; 4.051      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[15]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 4.052      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[16]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 4.052      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[18]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.204      ; 4.051      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[15]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 4.052      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[19]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.204      ; 4.051      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[17]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 4.052      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[16]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 4.052      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[20]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.204      ; 4.051      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[18]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 4.052      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[17]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 4.052      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[19]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 4.052      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[21]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.204      ; 4.051      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[18]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 4.052      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[20]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 4.052      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[22]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.204      ; 4.051      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[19]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 4.052      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[21]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 4.052      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[23]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.204      ; 4.051      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[20]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 4.052      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                  ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 3.627 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 4.048      ;
; 3.627 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 4.048      ;
; 3.627 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 4.048      ;
; 3.627 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 4.048      ;
; 3.627 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 4.048      ;
; 3.629 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cke_reg                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.196      ; 4.056      ;
; 3.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.207      ; 4.068      ;
; 3.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.207      ; 4.068      ;
; 3.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.207      ; 4.068      ;
; 3.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.207      ; 4.068      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.203      ; 4.066      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.203      ; 4.066      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.203      ; 4.066      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.203      ; 4.066      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.203      ; 4.066      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.203      ; 4.066      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.203      ; 4.066      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.203      ; 4.066      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.203      ; 4.066      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.203      ; 4.066      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.203      ; 4.066      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.203      ; 4.066      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.203      ; 4.066      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 4.063      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 4.063      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 4.063      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 4.063      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 4.063      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 4.063      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 4.063      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 4.063      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 4.063      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 4.063      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 4.063      ;
; 3.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 4.063      ;
; 3.633 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.199      ; 4.063      ;
; 3.633 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.199      ; 4.063      ;
; 3.633 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.199      ; 4.063      ;
; 3.633 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.199      ; 4.063      ;
; 3.633 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.203      ; 4.067      ;
; 3.633 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.199      ; 4.063      ;
; 3.633 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.199      ; 4.063      ;
; 3.633 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.199      ; 4.063      ;
; 3.633 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.199      ; 4.063      ;
; 3.633 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.199      ; 4.063      ;
; 3.633 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.199      ; 4.063      ;
; 3.633 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.199      ; 4.063      ;
; 3.639 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 4.063      ;
; 3.639 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 4.063      ;
; 3.639 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 4.063      ;
; 3.639 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 4.063      ;
; 3.639 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 4.063      ;
; 3.651 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 4.059      ;
; 3.651 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 4.063      ;
; 3.651 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 4.063      ;
; 3.651 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 4.063      ;
; 3.651 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 4.063      ;
; 3.651 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 4.063      ;
; 3.651 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 4.063      ;
; 3.651 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 4.063      ;
; 3.651 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 4.063      ;
; 3.651 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 4.063      ;
; 3.651 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 4.059      ;
; 3.651 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 4.059      ;
; 3.651 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 4.059      ;
; 3.651 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 4.063      ;
; 3.651 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 4.063      ;
; 3.651 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 4.063      ;
; 3.651 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 4.063      ;
; 3.651 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 4.063      ;
; 3.651 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 4.063      ;
; 3.651 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 4.063      ;
; 3.651 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 4.059      ;
; 3.651 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 4.059      ;
; 3.838 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 4.176      ;
; 3.838 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 4.176      ;
; 3.838 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 4.175      ;
; 3.839 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 4.175      ;
; 3.866 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.113      ; 4.142      ;
; 3.866 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.113      ; 4.142      ;
; 3.868 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.132      ; 4.163      ;
; 3.868 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.132      ; 4.163      ;
; 3.875 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.117      ; 4.155      ;
; 3.881 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.118      ; 4.162      ;
; 3.881 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.118      ; 4.162      ;
; 3.886 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 4.177      ;
; 3.886 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 4.177      ;
; 3.887 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.112      ; 4.162      ;
; 3.887 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.112      ; 4.162      ;
; 3.888 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.108      ; 4.159      ;
; 4.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.191      ; 4.531      ;
; 4.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.191      ; 4.531      ;
; 4.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 4.530      ;
; 4.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 4.529      ;
; 4.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 4.529      ;
; 4.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.187      ; 4.527      ;
; 4.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[1]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 4.529      ;
; 4.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 4.529      ;
; 4.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[3]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 4.530      ;
; 4.196 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 4.530      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                            ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cke_reg                      ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|reply_reg                    ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ;
; 4.201 ; 4.359        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                ;
; 4.201 ; 4.359        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                ;
; 4.201 ; 4.359        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]                ;
; 4.201 ; 4.359        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]                ;
; 4.201 ; 4.359        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                 ;
; 4.201 ; 4.359        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ;
; 4.201 ; 4.359        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ;
; 4.201 ; 4.359        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ;
; 4.201 ; 4.359        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ;
; 4.201 ; 4.359        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]                ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]                ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                 ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                 ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                 ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                 ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[11]                 ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[5]                  ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[7]                  ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[8]                  ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 4.194 ; 4.194        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.194 ; 4.194        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|o                                                                                                                    ;
; 4.224 ; 4.368        ; 0.144          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.313 ; 4.313        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|i                                                                                                                    ;
; 4.316 ; 4.440        ; 0.124          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.329 ; 8.810        ; 4.481          ; Port Rate        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.368 ; 4.368        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.368 ; 4.368        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 4.440 ; 4.440        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.440 ; 4.440        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 4.493 ; 4.493        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|i                                                                                                                    ;
; 4.612 ; 4.612        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.612 ; 4.612        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|o                                                                                                                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.375 ; 8.776        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0] ;
; 8.375 ; 8.776        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1] ;
; 8.375 ; 8.776        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2] ;
; 8.375 ; 8.776        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3] ;
; 8.375 ; 8.776        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4] ;
; 8.375 ; 8.776        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]      ;
; 8.375 ; 8.776        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]      ;
; 8.375 ; 8.776        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]      ;
; 8.375 ; 8.776        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]      ;
; 8.375 ; 8.776        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]      ;
; 8.375 ; 8.776        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]      ;
; 8.375 ; 8.776        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]      ;
; 8.375 ; 8.776        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]      ;
; 8.375 ; 8.776        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]      ;
; 8.375 ; 8.776        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]      ;
; 8.375 ; 8.776        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]      ;
; 8.375 ; 8.776        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]       ;
; 8.375 ; 8.776        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]       ;
; 8.375 ; 8.776        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]       ;
; 8.375 ; 8.776        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]       ;
; 8.375 ; 8.776        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]       ;
; 8.424 ; 8.825        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0] ;
; 8.424 ; 8.825        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1] ;
; 8.424 ; 8.825        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2] ;
; 8.424 ; 8.825        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3] ;
; 8.424 ; 8.825        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4] ;
; 8.424 ; 8.825        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]      ;
; 8.424 ; 8.825        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]      ;
; 8.424 ; 8.825        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]      ;
; 8.424 ; 8.825        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]      ;
; 8.424 ; 8.825        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]      ;
; 8.424 ; 8.825        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]      ;
; 8.424 ; 8.825        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]      ;
; 8.424 ; 8.825        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]      ;
; 8.424 ; 8.825        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]      ;
; 8.424 ; 8.825        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]      ;
; 8.424 ; 8.825        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]      ;
; 8.424 ; 8.825        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]       ;
; 8.424 ; 8.825        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]       ;
; 8.424 ; 8.825        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]       ;
; 8.424 ; 8.825        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]       ;
; 8.424 ; 8.825        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]       ;
; 8.472 ; 8.692        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                                                          ;
; 8.475 ; 8.695        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[5]                                          ;
; 8.478 ; 8.698        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[1]                                          ;
; 8.478 ; 8.698        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[10]                                                                                                      ;
; 8.478 ; 8.698        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[31]                                                                                                      ;
; 8.478 ; 8.698        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_add                                                                                        ;
; 8.478 ; 8.698        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_add_sp                                                                                     ;
; 8.478 ; 8.698        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_load                                                                                       ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[4]                                                     ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[5]                                                     ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[10]                                                                     ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[11]                                                                     ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theOpcode[6]                                  ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_direction_reg[4]                                                   ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_direction_reg[5]                                                   ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; user_io:my_user_io|joystick_1[1]                                                                                                                          ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; user_io:my_user_io|joystick_1[2]                                                                                                                          ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; user_io:my_user_io|joystick_1[3]                                                                                                                          ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; user_io:my_user_io|joystick_1[4]                                                                                                                          ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; user_io:my_user_io|joystick_1[5]                                                                                                                          ;
; 8.483 ; 8.703        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[3]                                          ;
; 8.483 ; 8.703        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[4]                                          ;
; 8.483 ; 8.703        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[6]                                          ;
; 8.483 ; 8.703        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[7]                                          ;
; 8.484 ; 8.704        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[16]                                   ;
; 8.484 ; 8.704        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[20]                                   ;
; 8.484 ; 8.704        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[12]                                                                                                      ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                                                  ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                                  ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                                  ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                                  ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                                  ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                                                   ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[2]                                          ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[3]                                          ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[5]                                          ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                                                                                      ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                                                                                        ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                        ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                                                           ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[3]                                                                                                           ;
; 8.487 ; 8.707        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gractl_reg[1]                                                          ;
; 8.488 ; 8.708        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[0]                                                           ;
; 8.488 ; 8.708        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[1]                                                           ;
; 8.488 ; 8.708        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[6]                                                           ;
; 8.488 ; 8.708        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]                                                          ;
; 8.489 ; 8.709        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|rom_bank[13]                            ;
; 8.489 ; 8.709        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[6]                                                                                                         ;
; 8.490 ; 8.710        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                    ;
; 8.490 ; 8.710        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[10]                                   ;
; 8.490 ; 8.710        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[15]                                   ;
; 8.490 ; 8.710        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[21]                                   ;
; 8.490 ; 8.710        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26]                                   ;
; 8.491 ; 8.711        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[4]                                          ;
; 8.491 ; 8.711        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[6]                                          ;
; 8.491 ; 8.711        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                   ;
; 8.492 ; 8.712        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[0]                                          ;
; 8.492 ; 8.712        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                                          ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                          ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                ; Clock Edge ; Target                                                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; 16.275 ; 16.275       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.279 ; 16.279       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.279 ; 16.279       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.298 ; 16.298       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.298 ; 16.298       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.298 ; 16.298       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.298 ; 16.298       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.351 ; 16.351       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.351 ; 16.351       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.355 ; 16.355       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'clk_27'                                                                                                              ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target                                                                         ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.362 ; 18.362       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.362 ; 18.362       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 18.366 ; 18.366       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.366 ; 18.366       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.400 ; 18.400       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.410 ; 18.410       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.410 ; 18.410       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.434 ; 18.434       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.438 ; 18.438       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.598 ; 18.598       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.602 ; 18.602       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.626 ; 18.626       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.626 ; 18.626       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.637 ; 18.637       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.668 ; 18.668       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.668 ; 18.668       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.672 ; 18.672       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.672 ; 18.672       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 33.037 ; 37.037       ; 4.000          ; Port Rate        ; clk_27 ; Rise       ; CLOCK_27[0]                                                                    ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'SPI_SCK'                                                                                                                                       ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                                                                                  ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+
; 20.415 ; 20.650       ; 0.235          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 20.415 ; 20.650       ; 0.235          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_we_reg       ;
; 20.416 ; 20.651       ; 0.235          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ;
; 20.416 ; 20.651       ; 0.235          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_we_reg       ;
; 20.417 ; 20.652       ; 0.235          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 20.418 ; 20.653       ; 0.235          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ;
; 20.498 ; 20.718       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|SPI_MISO~en                                                                          ;
; 20.498 ; 20.718       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|SPI_MISO~reg0                                                                        ;
; 20.499 ; 20.719       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[0]                                                                   ;
; 20.499 ; 20.719       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[1]                                                                   ;
; 20.499 ; 20.719       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[2]                                                                   ;
; 20.499 ; 20.719       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[3]                                                                   ;
; 20.499 ; 20.719       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[4]                                                                   ;
; 20.499 ; 20.719       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[5]                                                                   ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[0]                                                                                    ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[10]                                                                                   ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[1]                                                                                    ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[2]                                                                                    ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[3]                                                                                    ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[4]                                                                                    ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[5]                                                                                    ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[6]                                                                                    ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[7]                                                                                    ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[8]                                                                                    ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[9]                                                                                    ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[0]                                                                                     ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[1]                                                                                     ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[2]                                                                                     ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[3]                                                                                     ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[4]                                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[0]                                                                         ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[1]                                                                         ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[2]                                                                         ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_transfer_end_r                                                                 ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[17]                                                         ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[1]                                                          ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[25]                                                         ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[9]                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|osd_enable                                                                                 ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[0]                                                                                    ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[1]                                                                                    ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[0]                                                                           ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[1]                                                                           ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[2]                                                                           ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[0]                                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[1]                                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[2]                                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[3]                                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[4]                                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[5]                                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[6]                                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[7]                                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[8]                                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[9]                                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[0]                                                                               ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[1]                                                                               ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[2]                                                                               ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[4]                                                                               ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[0]                                                                              ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[0]                                                                       ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[1]                                                                       ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[2]                                                                       ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[3]                                                                       ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[4]                                                                       ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[0]                                                                      ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[1]                                                                      ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[2]                                                                      ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[3]                                                                      ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[4]                                                                      ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[5]                                                                      ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[6]                                                                      ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[7]                                                                      ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transfer_end_r                                                                   ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.drive_sel_r[0]                                                       ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[0]                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[10]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[11]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[12]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[13]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[14]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[15]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[16]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[18]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[19]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[20]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[21]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[22]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[23]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[24]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[26]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[27]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[28]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[29]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[2]                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[30]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[31]                                                         ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[3]                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[4]                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[5]                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[6]                                                          ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                             ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                                                                                                        ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 40.596 ; 41.626       ; 1.030          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                 ;
; 40.674 ; 41.704       ; 1.030          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                   ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                         ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                        ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                        ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                        ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                        ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                        ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                        ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                        ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                         ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                         ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                         ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                         ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                         ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                         ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                         ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                         ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                         ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[0]                                             ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[1]                                             ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[2]                                             ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[3]                                             ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[4]                                             ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[5]                                             ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[6]                                             ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[7]                                             ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[0]                                              ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[1]                                              ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[2]                                              ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[3]                                              ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[4]                                              ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[5]                                              ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[6]                                              ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[7]                                              ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[0]  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                               ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                         ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                              ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; rom_loaded                                                                                                                                                                                                    ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_reconfig_write_from_rom                                                                                                                                                      ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                      ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                          ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                          ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                          ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                    ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|rden_a_store                                                                                ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                           ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                           ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                            ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1] ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; 5.835 ; 6.478 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 7.815 ; 8.168 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; 0.706 ; 1.029 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; 2.062 ; 2.375 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 3.027 ; 3.140 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 3.021 ; 3.134 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 3.013 ; 3.126 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 3.027 ; 3.140 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 3.027 ; 3.140 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.964 ; 3.081 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.974 ; 3.091 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.964 ; 3.081 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.965 ; 3.082 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 3.008 ; 3.121 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 3.008 ; 3.121 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.998 ; 3.111 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.998 ; 3.111 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 3.011 ; 3.124 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 3.011 ; 3.124 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 3.012 ; 3.125 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 3.012 ; 3.125 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                        ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; -3.374 ; -3.822 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 0.560  ; 0.370  ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; -0.386 ; -0.709 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; -0.551 ; -0.710 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; -1.948 ; -2.065 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; -2.009 ; -2.122 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; -2.000 ; -2.113 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; -2.014 ; -2.127 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; -2.014 ; -2.127 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; -1.948 ; -2.065 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; -1.958 ; -2.075 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; -1.949 ; -2.066 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; -1.950 ; -2.067 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; -1.995 ; -2.108 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; -1.995 ; -2.108 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; -1.985 ; -2.098 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; -1.985 ; -2.098 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; -1.999 ; -2.112 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; -1.999 ; -2.112 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; -1.999 ; -2.112 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; -1.999 ; -2.112 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                             ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 9.763  ; 9.220  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 3.296  ; 3.052  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 3.136  ; 2.890  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 3.138  ; 2.892  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 3.138  ; 2.892  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 3.149  ; 2.903  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 3.139  ; 2.908  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 3.296  ; 3.052  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 3.279  ; 3.035  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 3.284  ; 3.040  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 3.284  ; 3.040  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 3.282  ; 3.038  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 3.136  ; 2.890  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 3.288  ; 3.044  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 3.136  ; 2.890  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 3.136  ; 2.890  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 3.126  ; 2.880  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 2.249  ; 2.160  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 3.297  ; 3.053  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 3.267  ; 3.023  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 3.276  ; 3.032  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 3.123  ; 2.892  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 3.123  ; 2.892  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 3.150  ; 2.904  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 3.160  ; 2.914  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 3.149  ; 2.903  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 3.148  ; 2.902  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 3.261  ; 3.017  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 3.261  ; 3.017  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 3.291  ; 3.047  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 3.291  ; 3.047  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 3.118  ; 2.887  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 3.277  ; 3.033  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 3.297  ; 3.053  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 3.138  ; 2.907  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 3.260  ; 3.016  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 3.148  ; 2.902  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 3.136  ; 2.890  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 3.135  ; 2.889  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 3.148  ; 2.902  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 24.639 ; 24.303 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 24.333 ; 24.023 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 24.105 ; 23.925 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 24.639 ; 24.303 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 23.978 ; 23.732 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 23.847 ; 23.404 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 23.206 ; 22.830 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 22.855 ; 22.541 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 22.449 ; 22.056 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 22.356 ; 21.977 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 22.855 ; 22.541 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 22.402 ; 22.019 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 21.487 ; 21.098 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 19.326 ; 18.780 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 7.314  ; 6.731  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 25.451 ; 25.112 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 24.945 ; 24.642 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 25.451 ; 25.112 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 25.052 ; 24.713 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 25.003 ; 24.607 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 24.917 ; 24.530 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 25.003 ; 24.635 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 6.819  ; 6.115  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -1.171 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -1.382 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                     ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 9.577  ; 9.038  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 2.257  ; 2.016  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 2.257  ; 2.016  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 2.259  ; 2.018  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 2.259  ; 2.018  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 2.270  ; 2.029  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 2.258  ; 2.033  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 2.415  ; 2.177  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 2.400  ; 2.162  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 2.404  ; 2.166  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 2.404  ; 2.166  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 2.402  ; 2.164  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 2.257  ; 2.016  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 2.408  ; 2.170  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 2.247  ; 2.006  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 2.257  ; 2.016  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 2.247  ; 2.006  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 1.411  ; 1.321  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 2.239  ; 2.014  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.388  ; 2.150  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.396  ; 2.158  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.243  ; 2.018  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.243  ; 2.018  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.270  ; 2.029  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.280  ; 2.039  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.270  ; 2.029  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.269  ; 2.028  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.381  ; 2.143  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.381  ; 2.143  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.411  ; 2.173  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.411  ; 2.173  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.239  ; 2.014  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.398  ; 2.160  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.417  ; 2.179  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.258  ; 2.033  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 2.380  ; 2.142  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 2.269  ; 2.028  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 2.257  ; 2.016  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 2.257  ; 2.016  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 2.269  ; 2.028  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 6.315  ; 5.881  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 6.909  ; 6.544  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 6.315  ; 5.881  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 6.826  ; 6.473  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 6.937  ; 6.666  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 6.993  ; 6.429  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 6.431  ; 6.189  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 6.518  ; 5.841  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 6.626  ; 6.275  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 6.673  ; 6.001  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 6.518  ; 5.841  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 7.097  ; 6.695  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 6.577  ; 6.033  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 7.322  ; 6.609  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 5.959  ; 5.339  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 6.641  ; 6.311  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 6.641  ; 6.357  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 7.063  ; 6.483  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 6.968  ; 6.311  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 7.529  ; 7.112  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 7.241  ; 6.689  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 7.448  ; 6.842  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 5.207  ; 4.547  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -1.959 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -2.166 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+----------------------------------------------------------+
; Propagation Delay                                        ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 9.445 ; 9.205 ; 9.854 ; 9.854 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------+
; Minimum Propagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 8.692 ; 8.692 ; 9.083 ; 9.112 ;
+------------+-------------+-------+-------+-------+-------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 8.158 ; 8.158 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 3.143 ; 3.039 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 3.149 ; 3.045 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 3.158 ; 3.054 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 3.164 ; 3.060 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 3.164 ; 3.060 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 3.188 ; 3.085 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 3.198 ; 3.095 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 3.187 ; 3.084 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 3.186 ; 3.083 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 3.143 ; 3.039 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 3.143 ; 3.039 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 3.173 ; 3.069 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 3.173 ; 3.069 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 3.159 ; 3.055 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 3.159 ; 3.055 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 3.179 ; 3.075 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 3.179 ; 3.075 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                     ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 7.453 ; 7.482 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 1.767 ; 1.696 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.774 ; 1.703 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.782 ; 1.711 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.788 ; 1.717 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.788 ; 1.717 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.784 ; 1.731 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.794 ; 1.741 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.784 ; 1.731 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.783 ; 1.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.767 ; 1.696 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.767 ; 1.696 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.797 ; 1.726 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.797 ; 1.726 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.784 ; 1.713 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.784 ; 1.713 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.803 ; 1.732 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.803 ; 1.732 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 7.799     ; 8.039     ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 2.878     ; 3.222     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.884     ; 3.228     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.893     ; 3.237     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.899     ; 3.243     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.899     ; 3.243     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.904     ; 3.267     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.914     ; 3.277     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.903     ; 3.266     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.902     ; 3.265     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.878     ; 3.222     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.878     ; 3.222     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.908     ; 3.252     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.908     ; 3.252     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.894     ; 3.238     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.894     ; 3.238     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.914     ; 3.258     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.914     ; 3.258     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 7.338     ; 7.338     ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 1.743     ; 1.843     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.750     ; 1.850     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.758     ; 1.858     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.764     ; 1.864     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.764     ; 1.864     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.761     ; 1.860     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.771     ; 1.870     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.761     ; 1.860     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.760     ; 1.859     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.743     ; 1.843     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.743     ; 1.843     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.773     ; 1.873     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.773     ; 1.873     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.760     ; 1.860     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.760     ; 1.860     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.779     ; 1.879     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.779     ; 1.879     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                                                                    ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                            ; Note                                                          ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
; 62.23 MHz  ; 62.23 MHz       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                               ;
; 72.53 MHz  ; 72.53 MHz       ; SPI_SCK                                                               ;                                                               ;
; 103.25 MHz ; 100.0 MHz       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; limit due to minimum period restriction (tmin)                ;
; 160.13 MHz ; 160.13 MHz      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                               ;
; 376.22 MHz ; 250.0 MHz       ; clk_27                                                                ; limit due to minimum period restriction (max I/O toggle rate) ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                             ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.296 ; -1.296        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.979  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.551  ; 0.000         ;
; SPI_SCK                                                               ; 13.962 ; 0.000         ;
; clk_27                                                                ; 34.379 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 36.824 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                             ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.383 ; 0.000         ;
; SPI_SCK                                                               ; 0.402 ; 0.000         ;
; clk_27                                                                ; 0.402 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.402 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 0.402 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 2.111 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+-----------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                                         ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.091 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 9.705 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+-----------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                                          ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.457 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 3.257 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                               ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.097  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 4.167  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.403  ; 0.000         ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 16.280 ; 0.000         ;
; clk_27                                                                ; 18.271 ; 0.000         ;
; SPI_SCK                                                               ; 20.400 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 40.596 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                   ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -1.296 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.958        ; -1.816     ; 1.221      ;
; 2.855  ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                ; SDRAM_A[5]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.992      ; 3.890      ;
; 2.856  ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                             ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.993      ; 3.890      ;
; 2.863  ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                             ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.990      ; 3.880      ;
; 2.863  ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                             ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.990      ; 3.880      ;
; 2.864  ; sdram_statemachine:sdram_adaptor|addr_reg[11]                               ; SDRAM_A[11]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.001      ; 3.890      ;
; 2.867  ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                ; SDRAM_A[7]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.994      ; 3.880      ;
; 2.867  ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                ; SDRAM_A[8]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.994      ; 3.880      ;
; 2.871  ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                ; SDRAM_A[9]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.998      ; 3.880      ;
; 2.872  ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                ; SDRAM_A[6]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.999      ; 3.880      ;
; 2.873  ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                             ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.000      ; 3.880      ;
; 2.875  ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                              ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.002      ; 3.880      ;
; 2.883  ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.010      ; 3.880      ;
; 2.890  ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                              ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.007      ; 3.870      ;
; 2.890  ; sdram_statemachine:sdram_adaptor|udqm_reg                                   ; SDRAM_DQMH                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.007      ; 3.870      ;
; 2.890  ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                              ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.007      ; 3.870      ;
; 2.988  ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                              ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.951      ; 3.716      ;
; 2.998  ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                              ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.951      ; 3.706      ;
; 2.998  ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                              ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.951      ; 3.706      ;
; 2.998  ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                              ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.951      ; 3.706      ;
; 2.999  ; sdram_statemachine:sdram_adaptor|we_n_reg                                   ; SDRAM_nWE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.952      ; 3.706      ;
; 2.999  ; sdram_statemachine:sdram_adaptor|ldqm_reg                                   ; SDRAM_DQML                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.952      ; 3.706      ;
; 2.999  ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                ; SDRAM_A[3]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.952      ; 3.706      ;
; 3.009  ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                ; SDRAM_A[2]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.952      ; 3.696      ;
; 3.010  ; sdram_statemachine:sdram_adaptor|addr_reg[10]                               ; SDRAM_A[10]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.953      ; 3.696      ;
; 3.010  ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                ; SDRAM_A[1]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.953      ; 3.696      ;
; 3.011  ; sdram_statemachine:sdram_adaptor|cas_n_reg                                  ; SDRAM_nCAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.954      ; 3.696      ;
; 3.011  ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                ; SDRAM_A[0]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.954      ; 3.696      ;
; 3.012  ; sdram_statemachine:sdram_adaptor|ba_reg[0]                                  ; SDRAM_BA[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.955      ; 3.696      ;
; 3.012  ; sdram_statemachine:sdram_adaptor|ras_n_reg                                  ; SDRAM_nRAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.955      ; 3.696      ;
; 3.012  ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                ; SDRAM_A[4]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.990      ; 3.731      ;
; 3.015  ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                             ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.993      ; 3.731      ;
; 3.020  ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                  ; SDRAM_BA[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.953      ; 3.686      ;
; 3.027  ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                              ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.005      ; 3.731      ;
; 3.027  ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                              ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.005      ; 3.731      ;
; 3.032  ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                             ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.000      ; 3.721      ;
; 3.216  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5                 ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.965      ; 3.502      ;
; 3.226  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6                 ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.965      ; 3.492      ;
; 3.226  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4                 ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.965      ; 3.492      ;
; 3.226  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7                 ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.965      ; 3.492      ;
; 3.239  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.007      ; 3.521      ;
; 3.239  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.007      ; 3.521      ;
; 3.246  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.004      ; 3.511      ;
; 3.246  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.004      ; 3.511      ;
; 3.251  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2                 ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.019      ; 3.521      ;
; 3.251  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3                 ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.019      ; 3.521      ;
; 3.256  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.014      ; 3.511      ;
; 3.256  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.014      ; 3.511      ;
; 3.258  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1                 ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.016      ; 3.511      ;
; 3.266  ; sdram_statemachine:sdram_adaptor|dq_output_reg                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.024      ; 3.511      ;
; 3.273  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9                 ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.021      ; 3.501      ;
; 3.273  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8                 ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.021      ; 3.501      ;
; 3.724  ; sdram_statemachine:sdram_adaptor|cke_reg                                    ; SDRAM_CKE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.944      ; 2.973      ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.979 ; SDRAM_DQ[3]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.440     ; 1.213      ;
; 0.979 ; SDRAM_DQ[2]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.440     ; 1.213      ;
; 0.985 ; SDRAM_DQ[0]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.444     ; 1.203      ;
; 0.991 ; SDRAM_DQ[15]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.428     ; 1.213      ;
; 0.991 ; SDRAM_DQ[14]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.428     ; 1.213      ;
; 0.992 ; SDRAM_DQ[1]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.437     ; 1.203      ;
; 0.995 ; SDRAM_DQ[13]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.434     ; 1.203      ;
; 0.995 ; SDRAM_DQ[12]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.434     ; 1.203      ;
; 0.998 ; SDRAM_DQ[9]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.441     ; 1.193      ;
; 0.998 ; SDRAM_DQ[8]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.441     ; 1.193      ;
; 1.004 ; SDRAM_DQ[11]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.425     ; 1.203      ;
; 1.004 ; SDRAM_DQ[10]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.425     ; 1.203      ;
; 1.021 ; SDRAM_DQ[5]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.388     ; 1.223      ;
; 1.031 ; SDRAM_DQ[7]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.388     ; 1.213      ;
; 1.031 ; SDRAM_DQ[6]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.388     ; 1.213      ;
; 1.031 ; SDRAM_DQ[4]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.388     ; 1.213      ;
; 1.240 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.405        ; -1.816     ; 1.222      ;
; 2.565 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.160     ; 5.961      ;
; 2.622 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|cas_n_reg                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 5.957      ;
; 2.652 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 5.928      ;
; 2.652 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.160     ; 5.874      ;
; 2.654 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 5.925      ;
; 2.664 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.155     ; 5.867      ;
; 2.669 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 5.910      ;
; 2.689 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 5.892      ;
; 2.700 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 5.834      ;
; 2.710 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.159     ; 5.817      ;
; 2.733 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 5.801      ;
; 2.752 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 5.782      ;
; 2.755 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 5.825      ;
; 2.756 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.109     ; 5.821      ;
; 2.764 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.160     ; 5.762      ;
; 2.766 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.145     ; 5.775      ;
; 2.781 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 5.753      ;
; 2.784 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 5.796      ;
; 2.786 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 5.795      ;
; 2.792 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 5.788      ;
; 2.803 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.109     ; 5.774      ;
; 2.810 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.159     ; 5.717      ;
; 2.817 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 5.761      ;
; 2.817 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.149     ; 5.720      ;
; 2.825 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 5.755      ;
; 2.826 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 5.753      ;
; 2.834 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 5.747      ;
; 2.839 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 5.741      ;
; 2.849 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 5.731      ;
; 2.850 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.149     ; 5.687      ;
; 2.855 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.883      ;
; 2.855 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.883      ;
; 2.855 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.883      ;
; 2.855 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.883      ;
; 2.855 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.883      ;
; 2.855 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.883      ;
; 2.855 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.883      ;
; 2.855 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.883      ;
; 2.855 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.883      ;
; 2.855 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.883      ;
; 2.855 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.883      ;
; 2.855 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.883      ;
; 2.856 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|cas_n_reg                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 5.723      ;
; 2.859 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 5.722      ;
; 2.863 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.145     ; 5.678      ;
; 2.869 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.149     ; 5.668      ;
; 2.872 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 5.707      ;
; 2.872 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 5.708      ;
; 2.880 ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[3]                         ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.187     ; 5.619      ;
; 2.894 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.148     ; 5.644      ;
; 2.913 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 5.666      ;
; 2.915 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 5.664      ;
; 2.921 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.153     ; 5.612      ;
; 2.922 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.159     ; 5.605      ;
; 2.926 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 5.614      ;
; 2.931 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 5.650      ;
; 2.936 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.145     ; 5.605      ;
; 2.937 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 5.641      ;
; 2.938 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 5.641      ;
; 2.944 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 5.635      ;
; 2.947 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 5.631      ;
; 2.969 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.155     ; 5.562      ;
; 2.977 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.156     ; 5.553      ;
; 3.000 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|cas_n_reg                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 5.578      ;
; 3.003 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 5.576      ;
; 3.004 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 5.577      ;
; 3.013 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.109     ; 5.564      ;
; 3.017 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 5.562      ;
; 3.024 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.148     ; 5.514      ;
; 3.026 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.712      ;
; 3.026 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.712      ;
; 3.026 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.712      ;
; 3.026 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.712      ;
; 3.026 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.712      ;
; 3.026 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.712      ;
; 3.026 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.712      ;
; 3.026 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.712      ;
; 3.026 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.712      ;
; 3.026 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.712      ;
; 3.026 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.712      ;
; 3.026 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.712      ;
; 3.035 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 5.509      ;
; 3.038 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.150     ; 5.498      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                 ;
+-------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                 ; To Node                                                                                                                ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.551 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 16.001     ;
; 1.551 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 16.001     ;
; 1.551 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 16.001     ;
; 1.551 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 16.001     ;
; 1.551 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 16.001     ;
; 1.551 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 16.001     ;
; 1.669 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 15.883     ;
; 1.669 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 15.883     ;
; 1.669 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 15.883     ;
; 1.669 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 15.883     ;
; 1.669 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 15.883     ;
; 1.669 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 15.883     ;
; 1.778 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 15.776     ;
; 1.778 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 15.776     ;
; 1.778 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 15.776     ;
; 1.778 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 15.776     ;
; 1.778 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 15.776     ;
; 1.778 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 15.776     ;
; 1.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 15.705     ;
; 1.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 15.705     ;
; 1.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 15.705     ;
; 1.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 15.705     ;
; 1.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 15.705     ;
; 1.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 15.705     ;
; 1.871 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 15.681     ;
; 1.871 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 15.681     ;
; 1.871 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 15.681     ;
; 1.871 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 15.681     ;
; 1.871 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 15.681     ;
; 1.871 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 15.681     ;
; 1.904 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.066     ; 15.653     ;
; 1.904 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.066     ; 15.653     ;
; 1.904 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.066     ; 15.653     ;
; 1.904 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.066     ; 15.653     ;
; 1.911 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.108     ; 15.604     ;
; 1.919 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 15.634     ;
; 1.919 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 15.634     ;
; 1.919 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 15.634     ;
; 1.919 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 15.634     ;
; 1.919 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 15.634     ;
; 1.919 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 15.634     ;
; 1.926 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 15.616     ;
; 1.926 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 15.616     ;
; 1.926 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 15.616     ;
; 1.937 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 15.606     ;
; 1.937 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 15.606     ;
; 1.937 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 15.606     ;
; 1.937 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 15.606     ;
; 1.944 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.358      ; 16.037     ;
; 1.956 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[14]                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 15.587     ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 15.572     ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 15.572     ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 15.572     ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 15.572     ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 15.572     ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 15.572     ;
; 2.003 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[12]                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 15.545     ;
; 2.022 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.066     ; 15.535     ;
; 2.022 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.066     ; 15.535     ;
; 2.022 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.066     ; 15.535     ;
; 2.022 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.066     ; 15.535     ;
; 2.029 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.108     ; 15.486     ;
; 2.044 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 15.498     ;
; 2.044 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 15.498     ;
; 2.044 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 15.498     ;
; 2.044 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.358      ; 15.937     ;
; 2.055 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 15.488     ;
; 2.055 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 15.488     ;
; 2.055 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 15.488     ;
; 2.055 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 15.488     ;
; 2.074 ; ioctl_state.IOCTL_IDLE                                                                                    ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[14]                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 15.469     ;
; 2.121 ; ioctl_state.IOCTL_IDLE                                                                                    ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[12]                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 15.427     ;
; 2.131 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.064     ; 15.428     ;
; 2.131 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.064     ; 15.428     ;
; 2.131 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.064     ; 15.428     ;
; 2.131 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.064     ; 15.428     ;
; 2.138 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 15.379     ;
; 2.146 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 15.379     ;
; 2.146 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 15.379     ;
; 2.148 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 15.368     ;
; 2.151 ; user_io:my_user_io|but_sw[1]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.083     ; 15.389     ;
; 2.151 ; user_io:my_user_io|but_sw[1]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.083     ; 15.389     ;
; 2.151 ; user_io:my_user_io|but_sw[1]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.083     ; 15.389     ;
; 2.151 ; user_io:my_user_io|but_sw[1]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.083     ; 15.389     ;
; 2.151 ; user_io:my_user_io|but_sw[1]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.083     ; 15.389     ;
; 2.151 ; user_io:my_user_io|but_sw[1]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.083     ; 15.389     ;
; 2.153 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 15.391     ;
; 2.153 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 15.391     ;
; 2.153 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 15.391     ;
; 2.156 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 15.378     ;
; 2.164 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 15.381     ;
; 2.164 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 15.381     ;
; 2.164 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 15.381     ;
; 2.164 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 15.381     ;
; 2.167 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 15.376     ;
; 2.167 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 15.376     ;
; 2.167 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 15.376     ;
; 2.176 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 15.357     ;
; 2.178 ; DMA_ADDR_FETCH_IOCTL[21]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.072     ; 15.373     ;
; 2.178 ; DMA_ADDR_FETCH_IOCTL[21]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.072     ; 15.373     ;
+-------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'SPI_SCK'                                                                                                                 ;
+--------+--------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                      ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 13.962 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.936      ;
; 13.962 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.936      ;
; 13.962 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.936      ;
; 13.962 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.936      ;
; 13.962 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.936      ;
; 14.104 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.794      ;
; 14.107 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.791      ;
; 14.107 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.791      ;
; 14.107 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.791      ;
; 14.107 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.791      ;
; 14.107 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.791      ;
; 14.170 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.728      ;
; 14.170 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.728      ;
; 14.170 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.728      ;
; 14.170 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.728      ;
; 14.170 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.728      ;
; 14.249 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.649      ;
; 14.312 ; user_io:my_user_io|byte_cnt[8] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.586      ;
; 14.422 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.476      ;
; 14.422 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.476      ;
; 14.422 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.476      ;
; 14.422 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.476      ;
; 14.422 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.476      ;
; 14.564 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 6.334      ;
; 15.182 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 5.716      ;
; 15.182 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 5.716      ;
; 15.182 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 5.716      ;
; 15.182 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 5.716      ;
; 15.182 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 5.716      ;
; 15.287 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 5.611      ;
; 15.287 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 5.611      ;
; 15.287 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 5.611      ;
; 15.287 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 5.611      ;
; 15.287 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 5.611      ;
; 15.324 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 5.574      ;
; 15.427 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.025      ; 5.466      ;
; 15.427 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.025      ; 5.466      ;
; 15.427 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.025      ; 5.466      ;
; 15.427 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.025      ; 5.466      ;
; 15.427 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.025      ; 5.466      ;
; 15.429 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 5.469      ;
; 15.581 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.025      ; 5.312      ;
; 15.603 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 5.295      ;
; 15.603 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 5.295      ;
; 15.603 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 5.295      ;
; 15.603 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 5.295      ;
; 15.603 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 5.295      ;
; 15.629 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.025      ; 5.264      ;
; 15.629 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.025      ; 5.264      ;
; 15.629 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.025      ; 5.264      ;
; 15.629 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.025      ; 5.264      ;
; 15.629 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.025      ; 5.264      ;
; 15.745 ; user_io:my_user_io|byte_cnt[9] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 5.153      ;
; 15.783 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.025      ; 5.110      ;
; 15.883 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.025      ; 5.010      ;
; 15.883 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.025      ; 5.010      ;
; 15.883 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.025      ; 5.010      ;
; 15.883 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.025      ; 5.010      ;
; 15.883 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.025      ; 5.010      ;
; 16.037 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.025      ; 4.856      ;
; 16.111 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.751      ;
; 16.111 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.751      ;
; 16.111 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.751      ;
; 16.111 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.751      ;
; 16.111 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.751      ;
; 16.119 ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.743      ;
; 16.119 ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.743      ;
; 16.119 ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.743      ;
; 16.119 ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.743      ;
; 16.119 ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.743      ;
; 16.147 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 4.751      ;
; 16.147 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 4.751      ;
; 16.147 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 4.751      ;
; 16.147 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 4.751      ;
; 16.147 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 4.751      ;
; 16.265 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.597      ;
; 16.273 ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.589      ;
; 16.286 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.576      ;
; 16.286 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.576      ;
; 16.286 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.576      ;
; 16.286 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.576      ;
; 16.286 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.576      ;
; 16.301 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 4.597      ;
; 16.386 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 4.512      ;
; 16.386 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 4.512      ;
; 16.386 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 4.512      ;
; 16.386 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 4.512      ;
; 16.386 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 4.512      ;
; 16.399 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.463      ;
; 16.399 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.463      ;
; 16.399 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.463      ;
; 16.399 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.463      ;
; 16.399 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.463      ;
; 16.440 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.422      ;
; 16.540 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 4.358      ;
; 16.553 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.006     ; 4.309      ;
; 16.703 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 4.195      ;
; 16.703 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 4.195      ;
; 16.703 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 4.195      ;
; 16.703 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.030      ; 4.195      ;
+--------+--------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'clk_27'                                                                                                                                                                 ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 34.379 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 2.588      ;
; 34.467 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 2.500      ;
; 34.507 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 2.460      ;
; 34.508 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 2.459      ;
; 34.563 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 2.404      ;
; 34.592 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 2.375      ;
; 34.596 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 2.371      ;
; 34.616 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 2.351      ;
; 34.636 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 2.331      ;
; 34.654 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 2.313      ;
; 34.688 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 2.279      ;
; 34.721 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 2.246      ;
; 34.724 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 2.243      ;
; 34.745 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 2.222      ;
; 34.757 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 2.210      ;
; 34.768 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 2.199      ;
; 34.814 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 2.153      ;
; 34.820 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 2.147      ;
; 34.862 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 2.105      ;
; 34.894 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 2.073      ;
; 34.905 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 2.062      ;
; 35.071 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.896      ;
; 35.072 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.895      ;
; 35.075 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.892      ;
; 35.082 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.885      ;
; 35.108 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.859      ;
; 35.132 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.835      ;
; 35.132 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.835      ;
; 35.141 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.826      ;
; 35.141 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.826      ;
; 35.164 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.803      ;
; 35.173 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.794      ;
; 35.207 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.760      ;
; 35.231 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.736      ;
; 35.247 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.720      ;
; 35.248 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.719      ;
; 35.251 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.716      ;
; 35.252 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.715      ;
; 35.264 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.703      ;
; 35.287 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.680      ;
; 35.290 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.677      ;
; 35.292 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.675      ;
; 35.299 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.668      ;
; 35.388 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.579      ;
; 35.397 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.570      ;
; 35.404 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.563      ;
; 35.407 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.560      ;
; 35.408 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.559      ;
; 35.437 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.530      ;
; 35.441 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.526      ;
; 35.463 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.504      ;
; 35.555 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.412      ;
; 35.577 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.390      ;
; 35.580 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.387      ;
; 35.581 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.386      ;
; 35.725 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.242      ;
; 35.815 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.152      ;
; 35.816 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.151      ;
; 35.841 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 1.126      ;
; 36.197 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.072     ; 0.770      ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 36.824 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_we_reg ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.734     ; 6.222      ;
; 37.707 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.610      ; 7.572      ;
; 39.202 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.383     ; 4.195      ;
; 39.205 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.383     ; 4.192      ;
; 39.227 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.621      ; 6.063      ;
; 39.269 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.621      ; 6.021      ;
; 39.389 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.621      ; 5.901      ;
; 39.420 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.383     ; 3.977      ;
; 39.529 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.378     ; 3.873      ;
; 39.553 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.383     ; 3.844      ;
; 39.622 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.383     ; 3.775      ;
; 39.644 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.388     ; 3.748      ;
; 39.796 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.378     ; 3.606      ;
; 39.969 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.378     ; 3.433      ;
; 40.108 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.378     ; 3.294      ;
; 40.546 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate3_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.119     ; 1.003      ;
; 40.811 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.378     ; 2.591      ;
; 41.077 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                             ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.386     ; 2.317      ;
; 76.335 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 6.915      ;
; 76.639 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.083     ; 6.613      ;
; 77.690 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.074     ; 5.571      ;
; 77.699 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.074     ; 5.562      ;
; 77.826 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.074     ; 5.435      ;
; 78.035 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.072     ; 5.228      ;
; 78.044 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.072     ; 5.219      ;
; 78.171 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.072     ; 5.092      ;
; 78.270 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                                                 ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.281      ; 5.383      ;
; 78.270 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                                                 ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.281      ; 5.383      ;
; 78.353 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.284      ; 5.303      ;
; 78.353 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.284      ; 5.303      ;
; 78.367 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.284      ; 5.289      ;
; 78.367 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.284      ; 5.289      ;
; 78.368 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.284      ; 5.288      ;
; 78.368 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.284      ; 5.288      ;
; 78.375 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                                                ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.281      ; 5.278      ;
; 78.375 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                                                ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.281      ; 5.278      ;
; 78.543 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.284      ; 5.113      ;
; 78.543 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.284      ; 5.113      ;
; 78.579 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.291      ; 5.084      ;
; 78.586 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.284      ; 5.070      ;
; 78.586 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.284      ; 5.070      ;
; 78.608 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.069     ; 4.658      ;
; 78.663 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.282      ; 4.991      ;
; 78.663 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.282      ; 4.991      ;
; 78.677 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.069     ; 4.589      ;
; 78.678 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.284      ; 4.978      ;
; 78.678 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.284      ; 4.978      ;
; 78.685 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_last_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.280      ; 4.967      ;
; 78.760 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.284      ; 4.896      ;
; 78.760 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.284      ; 4.896      ;
; 78.776 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.291      ; 4.887      ;
; 78.880 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.069     ; 4.386      ;
; 78.897 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.284      ; 4.759      ;
; 78.897 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.284      ; 4.759      ;
; 78.906 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.069     ; 4.360      ;
; 78.955 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.069     ; 4.311      ;
; 78.959 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.069     ; 4.307      ;
; 78.984 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.069     ; 4.282      ;
; 79.024 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.069     ; 4.242      ;
; 79.079 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.069     ; 4.187      ;
; 79.115 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.149      ;
; 79.115 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.149      ;
; 79.115 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.149      ;
; 79.115 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.149      ;
; 79.115 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.149      ;
; 79.115 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.149      ;
; 79.115 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.149      ;
; 79.115 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.149      ;
; 79.151 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.278      ; 4.499      ;
; 79.191 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.069     ; 4.075      ;
; 79.199 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.081     ; 4.055      ;
; 79.206 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 4.047      ;
; 79.206 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 4.047      ;
; 79.206 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 4.047      ;
; 79.206 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 4.047      ;
; 79.206 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 4.047      ;
; 79.206 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 4.047      ;
; 79.206 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 4.047      ;
; 79.206 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 4.047      ;
; 79.227 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.069     ; 4.039      ;
; 79.240 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.024      ;
; 79.240 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.024      ;
; 79.240 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.024      ;
; 79.240 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.024      ;
; 79.240 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.024      ;
; 79.240 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.024      ;
; 79.240 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.024      ;
; 79.240 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.024      ;
; 79.253 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.069     ; 4.013      ;
; 79.283 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.081     ; 3.971      ;
; 79.295 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.081     ; 3.959      ;
; 79.300 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 3.964      ;
; 79.300 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 3.964      ;
; 79.300 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 3.964      ;
; 79.300 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 3.964      ;
; 79.300 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 3.964      ;
; 79.300 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 3.964      ;
; 79.300 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 3.964      ;
; 79.300 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 3.964      ;
; 79.300 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 3.964      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                            ; To Node                                                                                                                                                                                                                                 ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.383 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 0.669      ;
; 0.383 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[0]                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[0]                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 0.669      ;
; 0.383 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[1]                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[1]                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 0.669      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[1]                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.428      ; 1.042      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[0]                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.429      ; 1.043      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[6]                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.427      ; 1.041      ;
; 0.388 ; user_io:my_user_io|sd_dout[1]                                                                                                        ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.421      ; 1.039      ;
; 0.389 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[4]                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.427      ; 1.046      ;
; 0.389 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[6]                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.422      ; 1.041      ;
; 0.393 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[3]                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.426      ; 1.049      ;
; 0.394 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[3]                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.426      ; 1.050      ;
; 0.395 ; user_io:my_user_io|sd_dout[0]                                                                                                        ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.421      ; 1.046      ;
; 0.397 ; zpu_secbuf_d[2]                                                                                                                      ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.424      ; 1.051      ;
; 0.398 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[2]                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[2]                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 0.684      ;
; 0.398 ; user_io:my_user_io|sd_dout[2]                                                                                                        ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.421      ; 1.049      ;
; 0.400 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[6]                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.428      ; 1.058      ;
; 0.401 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[44]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[44]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; user_io:my_user_io|status[15]                                                                                                        ; user_io:my_user_io|status[15]                                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; user_io:my_user_io|status[23]                                                                                                        ; user_io:my_user_io|status[23]                                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; user_io:my_user_io|status[0]                                                                                                         ; user_io:my_user_io|status[0]                                                                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21]                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13]                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29]                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; zpu_secbuf_addr[1]                                                                                                                   ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.413      ; 1.044      ;
; 0.401 ; user_io:my_user_io|sd_dout[5]                                                                                                        ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.421      ; 1.052      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.ready                                                           ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.ready                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.command                                                         ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.command                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|busy                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|busy                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|scl_ena                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|scl_ena                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; data_io:mist_data_io|abyte_cnt[1]                                                                                                    ; data_io:mist_data_io|abyte_cnt[1]                                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; data_io:mist_data_io|abyte_cnt[2]                                                                                                    ; data_io:mist_data_io|abyte_cnt[2]                                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; data_io:mist_data_io|abyte_cnt[0]                                                                                                    ; data_io:mist_data_io|abyte_cnt[0]                                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; data_io:mist_data_io|ioctl_download                                                                                                  ; data_io:mist_data_io|ioctl_download                                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; data_io:mist_data_io|hi                                                                                                              ; data_io:mist_data_io|hi                                                                                                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; data_io:mist_data_io|wr_int                                                                                                          ; data_io:mist_data_io|wr_int                                                                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[9]                                                                                        ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[9]                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                   ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[118]                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[118]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                   ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ZPU_IN1[30]                                                                                                                          ; ZPU_IN1[30]                                                                                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[30]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[30]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ZPU_IN1[31]                                                                                                                          ; ZPU_IN1[31]                                                                                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[22]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[22]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|sd_ack                                                                                                            ; user_io:my_user_io|sd_ack                                                                                                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[46]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[46]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[52]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[52]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[38]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[38]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[54]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[54]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreRead ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreRead                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Dreg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Dreg                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleEnd     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleEnd                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[0]                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[0]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[1]                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[1]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[2]                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[2]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[3]                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[3]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[41]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[41]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                        ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[364]                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[364]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[5]                                                                                        ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[5]                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[60]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[60]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                        ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[61]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[61]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'SPI_SCK'                                                                                                                                                                                               ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                  ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.402 ; data_io:mist_data_io|bit_cnt[1]            ; data_io:mist_data_io|bit_cnt[1]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; data_io:mist_data_io|bit_cnt[2]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|cmd[2]                  ; user_io:my_user_io|cmd[2]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|cmd[0]                  ; user_io:my_user_io|cmd[0]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|cmd[4]                  ; user_io:my_user_io|cmd[4]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|cmd[5]                  ; user_io:my_user_io|cmd[5]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|cmd[3]                  ; user_io:my_user_io|cmd[3]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|cmd[6]                  ; user_io:my_user_io|cmd[6]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|cmd[7]                  ; user_io:my_user_io|cmd[7]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|cmd[1]                  ; user_io:my_user_io|cmd[1]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; user_io:my_user_io|bit_cnt[1]              ; user_io:my_user_io|bit_cnt[1]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; user_io:my_user_io|bit_cnt[2]              ; user_io:my_user_io|bit_cnt[2]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; osd:osd_inst|osd_enable                    ; osd:osd_inst|osd_enable                                                                                 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; user_io:my_user_io|byte_cnt[0]             ; user_io:my_user_io|byte_cnt[0]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.669      ;
; 0.406 ; user_io:my_user_io|serial_out_rptr[0]      ; user_io:my_user_io|serial_out_rptr[0]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.068      ; 0.669      ;
; 0.417 ; user_io:my_user_io|spi_receiver_strobe_r   ; user_io:my_user_io|spi_receiver_strobe_r                                                                ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.684      ;
; 0.417 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[0]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.684      ;
; 0.417 ; data_io:mist_data_io|spi_receiver_strobe_r ; data_io:mist_data_io|spi_receiver_strobe_r                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.684      ;
; 0.418 ; user_io:my_user_io|bit_cnt[0]              ; user_io:my_user_io|bit_cnt[0]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.684      ;
; 0.420 ; osd:osd_inst|sbuf[2]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.428      ; 1.078      ;
; 0.429 ; osd:osd_inst|sbuf[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.425      ; 1.084      ;
; 0.430 ; osd:osd_inst|bcnt[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.419      ; 1.079      ;
; 0.436 ; osd:osd_inst|bcnt[6]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.419      ; 1.085      ;
; 0.438 ; osd:osd_inst|bcnt[8]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.417      ; 1.085      ;
; 0.439 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.430      ; 1.099      ;
; 0.447 ; osd:osd_inst|bcnt[8]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.419      ; 1.096      ;
; 0.447 ; osd:osd_inst|bcnt[0]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.417      ; 1.094      ;
; 0.463 ; osd:osd_inst|bcnt[3]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.419      ; 1.112      ;
; 0.463 ; osd:osd_inst|sbuf[6]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.430      ; 1.123      ;
; 0.463 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.417      ; 1.110      ;
; 0.464 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.430      ; 1.124      ;
; 0.466 ; osd:osd_inst|cnt[4]                        ; osd:osd_inst|cnt[4]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.732      ;
; 0.471 ; osd:osd_inst|bcnt[7]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.417      ; 1.118      ;
; 0.472 ; data_io:mist_data_io|sbuf[6]               ; data_io:mist_data_io|spi_byte_in[7]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.739      ;
; 0.474 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.741      ;
; 0.475 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[1]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.742      ;
; 0.476 ; data_io:mist_data_io|sbuf[1]               ; data_io:mist_data_io|spi_byte_in[2]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.743      ;
; 0.477 ; data_io:mist_data_io|sbuf[2]               ; data_io:mist_data_io|sbuf[3]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.744      ;
; 0.478 ; data_io:mist_data_io|sbuf[3]               ; data_io:mist_data_io|spi_byte_in[4]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.745      ;
; 0.478 ; data_io:mist_data_io|sbuf[4]               ; data_io:mist_data_io|spi_byte_in[5]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.745      ;
; 0.478 ; data_io:mist_data_io|sbuf[4]               ; data_io:mist_data_io|sbuf[5]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.745      ;
; 0.478 ; data_io:mist_data_io|sbuf[5]               ; data_io:mist_data_io|spi_byte_in[6]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.745      ;
; 0.478 ; data_io:mist_data_io|sbuf[2]               ; data_io:mist_data_io|spi_byte_in[3]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.745      ;
; 0.478 ; data_io:mist_data_io|sbuf[5]               ; data_io:mist_data_io|sbuf[6]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.745      ;
; 0.479 ; data_io:mist_data_io|sbuf[3]               ; data_io:mist_data_io|sbuf[4]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.746      ;
; 0.479 ; data_io:mist_data_io|sbuf[0]               ; data_io:mist_data_io|spi_byte_in[1]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.746      ;
; 0.480 ; data_io:mist_data_io|sbuf[0]               ; data_io:mist_data_io|sbuf[1]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.747      ;
; 0.480 ; data_io:mist_data_io|sbuf[1]               ; data_io:mist_data_io|sbuf[2]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.747      ;
; 0.480 ; user_io:my_user_io|bit_cnt[0]              ; user_io:my_user_io|bit_cnt[1]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.746      ;
; 0.485 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|sbuf[6]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.752      ;
; 0.486 ; user_io:my_user_io|sbuf[4]                 ; user_io:my_user_io|spi_byte_in[5]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.753      ;
; 0.486 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|spi_byte_in[6]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.753      ;
; 0.486 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.430      ; 1.146      ;
; 0.487 ; user_io:my_user_io|sbuf[4]                 ; user_io:my_user_io|sbuf[5]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.754      ;
; 0.489 ; user_io:my_user_io|sbuf[6]                 ; user_io:my_user_io|cmd[7]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.756      ;
; 0.491 ; user_io:my_user_io|bit_cnt[1]              ; user_io:my_user_io|bit_cnt[2]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.757      ;
; 0.492 ; osd:osd_inst|sbuf[0]                       ; osd:osd_inst|sbuf[1]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.758      ;
; 0.498 ; osd:osd_inst|sbuf[2]                       ; osd:osd_inst|sbuf[3]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.765      ;
; 0.502 ; osd:osd_inst|sbuf[2]                       ; osd:osd_inst|cmd[3]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.769      ;
; 0.504 ; user_io:my_user_io|sbuf[2]                 ; user_io:my_user_io|cmd[3]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.771      ;
; 0.506 ; user_io:my_user_io|sbuf[2]                 ; user_io:my_user_io|sbuf[3]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.773      ;
; 0.506 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|sbuf[6]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.773      ;
; 0.508 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|cmd[6]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.775      ;
; 0.508 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|cmd[5]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.775      ;
; 0.509 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|sbuf[5]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.776      ;
; 0.644 ; osd:osd_inst|bcnt[10]                      ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.417      ; 1.291      ;
; 0.656 ; osd:osd_inst|bcnt[2]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.417      ; 1.303      ;
; 0.667 ; user_io:my_user_io|sbuf[1]                 ; user_io:my_user_io|sbuf[2]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.934      ;
; 0.669 ; user_io:my_user_io|sbuf[3]                 ; user_io:my_user_io|sbuf[4]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.936      ;
; 0.674 ; osd:osd_inst|sbuf[6]                       ; osd:osd_inst|cmd[7]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.941      ;
; 0.679 ; osd:osd_inst|bcnt[10]                      ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.419      ; 1.328      ;
; 0.685 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|sbuf[4]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.952      ;
; 0.686 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|cmd[4]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.953      ;
; 0.701 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|cmd[6]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.968      ;
; 0.701 ; user_io:my_user_io|serial_out_rptr[2]      ; user_io:my_user_io|serial_out_rptr[2]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.068      ; 0.964      ;
; 0.701 ; user_io:my_user_io|serial_out_rptr[5]      ; user_io:my_user_io|serial_out_rptr[5]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.068      ; 0.964      ;
; 0.702 ; user_io:my_user_io|serial_out_rptr[4]      ; user_io:my_user_io|serial_out_rptr[4]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.068      ; 0.965      ;
; 0.703 ; user_io:my_user_io|sbuf[4]                 ; user_io:my_user_io|cmd[5]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.970      ;
; 0.703 ; user_io:my_user_io|serial_out_rptr[3]      ; user_io:my_user_io|serial_out_rptr[3]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.068      ; 0.966      ;
; 0.704 ; data_io:mist_data_io|bit_cnt[1]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.971      ;
; 0.706 ; osd:osd_inst|cnt[1]                        ; osd:osd_inst|cnt[1]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.972      ;
; 0.708 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|bcnt[1]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.974      ;
; 0.708 ; user_io:my_user_io|byte_cnt[4]             ; user_io:my_user_io|byte_cnt[4]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.974      ;
; 0.709 ; osd:osd_inst|bcnt[8]                       ; osd:osd_inst|bcnt[8]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.975      ;
; 0.709 ; osd:osd_inst|bcnt[9]                       ; osd:osd_inst|bcnt[9]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.975      ;
; 0.709 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.419      ; 1.358      ;
; 0.710 ; osd:osd_inst|cnt[2]                        ; osd:osd_inst|cnt[2]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.976      ;
; 0.710 ; osd:osd_inst|bcnt[6]                       ; osd:osd_inst|bcnt[6]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.976      ;
; 0.710 ; osd:osd_inst|bcnt[7]                       ; osd:osd_inst|bcnt[7]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.976      ;
; 0.710 ; osd:osd_inst|bcnt[10]                      ; osd:osd_inst|bcnt[10]                                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.976      ;
; 0.710 ; osd:osd_inst|sbuf[0]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.425      ; 1.365      ;
; 0.711 ; osd:osd_inst|bcnt[3]                       ; osd:osd_inst|bcnt[3]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.977      ;
; 0.711 ; osd:osd_inst|bcnt[5]                       ; osd:osd_inst|bcnt[5]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.977      ;
; 0.714 ; osd:osd_inst|bcnt[2]                       ; osd:osd_inst|bcnt[2]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.980      ;
; 0.714 ; osd:osd_inst|bcnt[4]                       ; osd:osd_inst|bcnt[4]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.980      ;
; 0.719 ; user_io:my_user_io|byte_cnt[3]             ; user_io:my_user_io|byte_cnt[3]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.985      ;
; 0.720 ; osd:osd_inst|cnt[3]                        ; osd:osd_inst|cnt[3]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.986      ;
; 0.721 ; user_io:my_user_io|bit_cnt[0]              ; user_io:my_user_io|bit_cnt[2]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.987      ;
; 0.723 ; user_io:my_user_io|byte_cnt[5]             ; user_io:my_user_io|byte_cnt[5]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.989      ;
; 0.723 ; user_io:my_user_io|serial_out_rptr[1]      ; user_io:my_user_io|serial_out_rptr[1]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.068      ; 0.986      ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'clk_27'                                                                                                                                                                 ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 0.669      ;
; 0.700 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 0.967      ;
; 0.700 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 0.967      ;
; 0.709 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 0.976      ;
; 0.878 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.145      ;
; 0.891 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.158      ;
; 0.894 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.161      ;
; 0.962 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.229      ;
; 1.009 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.276      ;
; 1.016 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.283      ;
; 1.017 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.284      ;
; 1.021 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.288      ;
; 1.023 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.290      ;
; 1.024 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.291      ;
; 1.026 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.293      ;
; 1.031 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.298      ;
; 1.032 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.299      ;
; 1.033 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.300      ;
; 1.059 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.326      ;
; 1.062 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.329      ;
; 1.064 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.331      ;
; 1.115 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.382      ;
; 1.117 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.384      ;
; 1.117 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.384      ;
; 1.139 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.406      ;
; 1.143 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.410      ;
; 1.154 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.421      ;
; 1.156 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.423      ;
; 1.157 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.424      ;
; 1.159 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.426      ;
; 1.162 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.429      ;
; 1.165 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.432      ;
; 1.178 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.445      ;
; 1.179 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.446      ;
; 1.200 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.467      ;
; 1.201 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.468      ;
; 1.202 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.469      ;
; 1.202 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.469      ;
; 1.203 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.470      ;
; 1.246 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.513      ;
; 1.247 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.514      ;
; 1.248 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.515      ;
; 1.295 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.562      ;
; 1.296 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.563      ;
; 1.325 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.592      ;
; 1.326 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.593      ;
; 1.402 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.669      ;
; 1.415 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.682      ;
; 1.416 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.683      ;
; 1.417 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.684      ;
; 1.417 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.684      ;
; 1.418 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.685      ;
; 1.464 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.731      ;
; 1.465 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.732      ;
; 1.467 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.734      ;
; 1.512 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.779      ;
; 1.513 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.780      ;
; 1.534 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.801      ;
; 1.627 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.894      ;
; 1.627 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.072      ; 1.894      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                             ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                     ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.402 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.417 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.684      ;
; 0.590 ; sdram_statemachine:sdram_adaptor|request_sreg                 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 0.974      ;
; 0.685 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.952      ;
; 0.687 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.954      ;
; 0.688 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.955      ;
; 0.688 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.955      ;
; 0.691 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.958      ;
; 0.691 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.958      ;
; 0.691 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.958      ;
; 0.693 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.960      ;
; 0.695 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.962      ;
; 0.695 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.962      ;
; 0.696 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.963      ;
; 0.697 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.964      ;
; 0.698 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.965      ;
; 0.698 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.965      ;
; 0.699 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.966      ;
; 0.700 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.967      ;
; 0.704 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.970      ;
; 0.707 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.974      ;
; 0.708 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.974      ;
; 0.708 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.974      ;
; 0.710 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.977      ;
; 0.715 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.981      ;
; 0.716 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.982      ;
; 0.719 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.985      ;
; 0.719 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.985      ;
; 0.719 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.985      ;
; 0.722 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.989      ;
; 0.723 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.989      ;
; 0.724 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.991      ;
; 0.724 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.990      ;
; 0.728 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.995      ;
; 0.729 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.996      ;
; 0.729 ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.996      ;
; 0.729 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.995      ;
; 0.733 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.000      ;
; 0.736 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.002      ;
; 0.751 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.018      ;
; 0.976 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.243      ;
; 1.006 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.273      ;
; 1.007 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.274      ;
; 1.008 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.275      ;
; 1.009 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.276      ;
; 1.009 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.276      ;
; 1.012 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.279      ;
; 1.012 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.279      ;
; 1.014 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.281      ;
; 1.015 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.282      ;
; 1.016 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.283      ;
; 1.018 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.285      ;
; 1.019 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.286      ;
; 1.019 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.286      ;
; 1.020 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.287      ;
; 1.021 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.288      ;
; 1.022 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.289      ;
; 1.022 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.289      ;
; 1.024 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.290      ;
; 1.025 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.291      ;
; 1.025 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.292      ;
; 1.025 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.292      ;
; 1.027 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.294      ;
; 1.029 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.295      ;
; 1.029 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.295      ;
; 1.029 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.296      ;
; 1.031 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.298      ;
; 1.031 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.298      ;
; 1.033 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.300      ;
; 1.034 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.301      ;
; 1.034 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.301      ;
; 1.036 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.302      ;
; 1.037 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.303      ;
; 1.039 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.305      ;
; 1.039 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.305      ;
; 1.040 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.306      ;
; 1.041 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.307      ;
; 1.041 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.307      ;
; 1.042 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.309      ;
; 1.044 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.311      ;
; 1.044 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.310      ;
; 1.046 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.313      ;
; 1.047 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.314      ;
; 1.050 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.317      ;
; 1.051 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.317      ;
; 1.056 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.322      ;
; 1.056 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.322      ;
; 1.057 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.323      ;
; 1.062 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.329      ;
; 1.067 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.334      ;
; 1.101 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.368      ;
; 1.107 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.374      ;
; 1.107 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.374      ;
; 1.108 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.375      ;
; 1.112 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.379      ;
; 1.114 ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                 ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.242      ; 1.551      ;
; 1.115 ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                 ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.242      ; 1.552      ;
; 1.116 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.383      ;
; 1.119 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.386      ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                     ; To Node                                                                                                                                                                                                                               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.402 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; rom_loaded                                                                                                                                                                                                    ; rom_loaded                                                                                                                                                                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.417 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.684      ;
; 0.455 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.721      ;
; 0.457 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.724      ;
; 0.459 ; rom_loaded                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.725      ;
; 0.470 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.737      ;
; 0.471 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                          ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.737      ;
; 0.472 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                          ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.738      ;
; 0.486 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.420      ; 1.136      ;
; 0.493 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_init_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.760      ;
; 0.509 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.775      ;
; 0.511 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[6]                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.777      ;
; 0.516 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.782      ;
; 0.518 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.784      ;
; 0.519 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.785      ;
; 0.520 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.786      ;
; 0.522 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.788      ;
; 0.585 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                               ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.420      ; 1.235      ;
; 0.608 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.875      ;
; 0.608 ; switch_pal_ntsc:pll_switcher|pll_reconfig_write_from_rom                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.874      ;
; 0.609 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.876      ;
; 0.644 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.421      ; 1.295      ;
; 0.646 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[3]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[3]                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.912      ;
; 0.648 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[7]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[7]                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.914      ;
; 0.648 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[1]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[1]                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.914      ;
; 0.649 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[5]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[5]                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.915      ;
; 0.649 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[4]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[4]                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.915      ;
; 0.649 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[0]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[0]                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.915      ;
; 0.650 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|tmp_seq_ena_state                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_ena_state                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.917      ;
; 0.654 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.921      ;
; 0.669 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.936      ;
; 0.684 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.950      ;
; 0.684 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.950      ;
; 0.685 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.951      ;
; 0.685 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.952      ;
; 0.686 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.953      ;
; 0.686 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.953      ;
; 0.688 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.954      ;
; 0.688 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.955      ;
; 0.688 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.955      ;
; 0.689 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.956      ;
; 0.689 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.954      ;
; 0.690 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.956      ;
; 0.690 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.957      ;
; 0.691 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.957      ;
; 0.691 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.957      ;
; 0.691 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.958      ;
; 0.694 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.960      ;
; 0.694 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.960      ;
; 0.694 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.960      ;
; 0.695 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.961      ;
; 0.696 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.963      ;
; 0.696 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.963      ;
; 0.696 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.962      ;
; 0.696 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.962      ;
; 0.697 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.964      ;
; 0.697 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.963      ;
; 0.698 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.964      ;
; 0.698 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.964      ;
; 0.698 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.964      ;
; 0.698 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.964      ;
; 0.698 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.965      ;
; 0.700 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.966      ;
; 0.700 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.966      ;
; 0.701 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.968      ;
; 0.706 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.973      ;
; 0.708 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.974      ;
; 0.708 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.975      ;
; 0.708 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.975      ;
; 0.709 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.975      ;
; 0.709 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.976      ;
; 0.709 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.976      ;
; 0.709 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.976      ;
; 0.712 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.979      ;
; 0.712 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.979      ;
; 0.714 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.980      ;
; 0.714 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.980      ;
; 0.714 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.980      ;
; 0.715 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.982      ;
; 0.715 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.981      ;
; 0.717 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.984      ;
; 0.718 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.984      ;
; 0.719 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.986      ;
; 0.722 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.988      ;
; 0.724 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.990      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 2.111 ; sdram_statemachine:sdram_adaptor|cke_reg                                    ; SDRAM_CKE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.256      ; 2.830      ;
; 2.225 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9                 ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.334      ; 3.022      ;
; 2.225 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8                 ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.334      ; 3.022      ;
; 2.232 ; sdram_statemachine:sdram_adaptor|dq_output_reg                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.337      ; 3.032      ;
; 2.239 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1                 ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.330      ; 3.032      ;
; 2.242 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.327      ; 3.032      ;
; 2.242 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.327      ; 3.032      ;
; 2.246 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2                 ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.333      ; 3.042      ;
; 2.246 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3                 ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.333      ; 3.042      ;
; 2.248 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6                 ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.281      ; 2.992      ;
; 2.248 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4                 ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.281      ; 2.992      ;
; 2.248 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7                 ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.281      ; 2.992      ;
; 2.251 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.318      ; 3.032      ;
; 2.251 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.318      ; 3.032      ;
; 2.258 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.321      ; 3.042      ;
; 2.258 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5                 ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.281      ; 3.002      ;
; 2.258 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.321      ; 3.042      ;
; 2.716 ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                  ; SDRAM_BA[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.270      ; 3.449      ;
; 2.720 ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                             ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.314      ; 3.497      ;
; 2.724 ; sdram_statemachine:sdram_adaptor|ba_reg[0]                                  ; SDRAM_BA[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.272      ; 3.459      ;
; 2.724 ; sdram_statemachine:sdram_adaptor|ras_n_reg                                  ; SDRAM_nRAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.272      ; 3.459      ;
; 2.724 ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                              ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.320      ; 3.507      ;
; 2.724 ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                              ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.320      ; 3.507      ;
; 2.725 ; sdram_statemachine:sdram_adaptor|cas_n_reg                                  ; SDRAM_nCAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.271      ; 3.459      ;
; 2.725 ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                ; SDRAM_A[0]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.271      ; 3.459      ;
; 2.726 ; sdram_statemachine:sdram_adaptor|addr_reg[10]                               ; SDRAM_A[10]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.270      ; 3.459      ;
; 2.726 ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                ; SDRAM_A[1]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.270      ; 3.459      ;
; 2.727 ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                ; SDRAM_A[2]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.269      ; 3.459      ;
; 2.736 ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                             ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.308      ; 3.507      ;
; 2.737 ; sdram_statemachine:sdram_adaptor|we_n_reg                                   ; SDRAM_nWE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.269      ; 3.469      ;
; 2.737 ; sdram_statemachine:sdram_adaptor|ldqm_reg                                   ; SDRAM_DQML                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.269      ; 3.469      ;
; 2.737 ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                ; SDRAM_A[3]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.269      ; 3.469      ;
; 2.738 ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                ; SDRAM_A[4]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.306      ; 3.507      ;
; 2.738 ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                              ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.268      ; 3.469      ;
; 2.738 ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                              ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.268      ; 3.469      ;
; 2.738 ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                              ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.268      ; 3.469      ;
; 2.748 ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                              ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.268      ; 3.479      ;
; 2.848 ; sdram_statemachine:sdram_adaptor|udqm_reg                                   ; SDRAM_DQMH                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.322      ; 3.633      ;
; 2.849 ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                              ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.321      ; 3.633      ;
; 2.849 ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                              ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.321      ; 3.633      ;
; 2.856 ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.324      ; 3.643      ;
; 2.863 ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                              ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.317      ; 3.643      ;
; 2.866 ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                ; SDRAM_A[6]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.314      ; 3.643      ;
; 2.866 ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                             ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.314      ; 3.643      ;
; 2.867 ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                ; SDRAM_A[9]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.313      ; 3.643      ;
; 2.871 ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                ; SDRAM_A[7]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.309      ; 3.643      ;
; 2.871 ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                ; SDRAM_A[8]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.309      ; 3.643      ;
; 2.874 ; sdram_statemachine:sdram_adaptor|addr_reg[11]                               ; SDRAM_A[11]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.316      ; 3.653      ;
; 2.875 ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                             ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.305      ; 3.643      ;
; 2.875 ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                             ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.305      ; 3.643      ;
; 2.882 ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                ; SDRAM_A[5]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.308      ; 3.653      ;
; 2.882 ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                             ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.308      ; 3.653      ;
; 9.187 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -6.853       ; -1.566     ; 0.970      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                 ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                      ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 4.091 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.297     ; 4.287      ;
; 4.091 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.297     ; 4.287      ;
; 4.091 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.297     ; 4.287      ;
; 4.091 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.297     ; 4.287      ;
; 4.112 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.337     ; 4.226      ;
; 4.112 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.337     ; 4.226      ;
; 4.115 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.350     ; 4.210      ;
; 4.115 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.350     ; 4.210      ;
; 4.115 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.353     ; 4.207      ;
; 4.121 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.343     ; 4.211      ;
; 4.121 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.343     ; 4.211      ;
; 4.123 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.346     ; 4.206      ;
; 4.127 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 4.378      ;
; 4.128 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.177     ; 4.381      ;
; 4.128 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.177     ; 4.381      ;
; 4.128 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.177     ; 4.381      ;
; 4.128 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.177     ; 4.381      ;
; 4.128 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 4.379      ;
; 4.128 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 4.377      ;
; 4.128 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.180     ; 4.378      ;
; 4.128 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.178     ; 4.380      ;
; 4.128 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.178     ; 4.380      ;
; 4.128 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.180     ; 4.378      ;
; 4.128 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 4.379      ;
; 4.128 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.178     ; 4.380      ;
; 4.128 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.178     ; 4.380      ;
; 4.128 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 4.379      ;
; 4.129 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.334     ; 4.212      ;
; 4.129 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.334     ; 4.212      ;
; 4.129 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.349     ; 4.197      ;
; 4.129 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.349     ; 4.197      ;
; 4.132 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.223     ; 4.331      ;
; 4.141 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 4.330      ;
; 4.142 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.217     ; 4.327      ;
; 4.142 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.222     ; 4.322      ;
; 4.142 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.225     ; 4.319      ;
; 4.149 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.217     ; 4.320      ;
; 4.149 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.217     ; 4.320      ;
; 4.149 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.218     ; 4.319      ;
; 4.149 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.218     ; 4.319      ;
; 4.151 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|udqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.231     ; 4.304      ;
; 4.152 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.233     ; 4.301      ;
; 4.152 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.230     ; 4.304      ;
; 4.152 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.230     ; 4.304      ;
; 4.158 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.223     ; 4.305      ;
; 4.158 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.223     ; 4.305      ;
; 4.160 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.226     ; 4.300      ;
; 4.166 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.229     ; 4.291      ;
; 4.166 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.229     ; 4.291      ;
; 4.166 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.214     ; 4.306      ;
; 4.166 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.214     ; 4.306      ;
; 4.315 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 4.145      ;
; 4.315 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 4.145      ;
; 4.315 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 4.145      ;
; 4.315 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 4.145      ;
; 4.336 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.230     ; 4.084      ;
; 4.336 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.230     ; 4.084      ;
; 4.339 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.246     ; 4.065      ;
; 4.339 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.243     ; 4.068      ;
; 4.339 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.243     ; 4.068      ;
; 4.345 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.236     ; 4.069      ;
; 4.345 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.236     ; 4.069      ;
; 4.347 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.239     ; 4.064      ;
; 4.353 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.242     ; 4.055      ;
; 4.353 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.242     ; 4.055      ;
; 4.353 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.227     ; 4.070      ;
; 4.353 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.227     ; 4.070      ;
; 4.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.183     ; 3.993      ;
; 4.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 3.997      ;
; 4.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 3.997      ;
; 4.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 3.997      ;
; 4.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 3.997      ;
; 4.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 3.997      ;
; 4.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 3.997      ;
; 4.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 3.997      ;
; 4.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 3.997      ;
; 4.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 3.997      ;
; 4.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.183     ; 3.993      ;
; 4.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.183     ; 3.993      ;
; 4.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.183     ; 3.993      ;
; 4.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 3.997      ;
; 4.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 3.997      ;
; 4.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 3.997      ;
; 4.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 3.997      ;
; 4.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 3.997      ;
; 4.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 3.997      ;
; 4.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 3.997      ;
; 4.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.183     ; 3.993      ;
; 4.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.183     ; 3.993      ;
; 4.645 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.168     ; 3.999      ;
; 4.645 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.168     ; 3.999      ;
; 4.645 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.168     ; 3.999      ;
; 4.645 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.168     ; 3.999      ;
; 4.645 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.168     ; 3.999      ;
; 4.649 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.161     ; 4.002      ;
; 4.649 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.161     ; 4.002      ;
; 4.649 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.161     ; 4.002      ;
; 4.649 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.161     ; 4.002      ;
; 4.649 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.161     ; 4.002      ;
; 4.649 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.161     ; 4.002      ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                           ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 9.705  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.166     ; 7.752      ;
; 9.705  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.175     ; 7.743      ;
; 9.705  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.175     ; 7.743      ;
; 9.705  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.175     ; 7.743      ;
; 9.744  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.161     ; 7.718      ;
; 9.744  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.161     ; 7.718      ;
; 9.744  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.161     ; 7.718      ;
; 9.744  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.161     ; 7.718      ;
; 9.744  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[20]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.161     ; 7.718      ;
; 9.746  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.713      ;
; 9.746  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.713      ;
; 9.746  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_32BIT_WRITE_ENABLE_reg                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.713      ;
; 9.754  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.168     ; 7.701      ;
; 9.754  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.168     ; 7.701      ;
; 9.795  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.663      ;
; 9.795  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.663      ;
; 9.795  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.663      ;
; 9.795  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.663      ;
; 10.073 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 7.451      ;
; 10.073 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 7.451      ;
; 10.073 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 7.451      ;
; 10.089 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 7.460      ;
; 10.122 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.092     ; 7.409      ;
; 10.122 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.092     ; 7.409      ;
; 10.128 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 7.426      ;
; 10.128 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 7.426      ;
; 10.128 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 7.426      ;
; 10.128 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 7.426      ;
; 10.128 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[20]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 7.426      ;
; 10.130 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.072     ; 7.421      ;
; 10.130 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.072     ; 7.421      ;
; 10.130 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_32BIT_WRITE_ENABLE_reg                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.072     ; 7.421      ;
; 10.153 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.282      ; 7.752      ;
; 10.155 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.275      ; 7.743      ;
; 10.179 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 7.371      ;
; 10.179 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 7.371      ;
; 10.179 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 7.371      ;
; 10.179 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 7.371      ;
; 10.197 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[3]                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.262      ;
; 10.197 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.182     ; 7.244      ;
; 10.197 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[13]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.182     ; 7.244      ;
; 10.197 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[8]                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.182     ; 7.244      ;
; 10.197 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.182     ; 7.244      ;
; 10.197 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[12]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.182     ; 7.244      ;
; 10.197 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[14]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.182     ; 7.244      ;
; 10.197 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[15]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.182     ; 7.244      ;
; 10.197 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.182     ; 7.244      ;
; 10.203 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.239      ; 7.659      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.157     ; 7.261      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.157     ; 7.261      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.157     ; 7.261      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.157     ; 7.261      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.157     ; 7.261      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.157     ; 7.261      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.157     ; 7.261      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.157     ; 7.261      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.157     ; 7.261      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[12] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.157     ; 7.261      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.157     ; 7.261      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[26]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.157     ; 7.261      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.166     ; 7.252      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.254      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.254      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[10]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.157     ; 7.261      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[28]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.157     ; 7.261      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[24]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[31]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.157     ; 7.261      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[21]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[8]                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[9]                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.157     ; 7.261      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[12]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.157     ; 7.261      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[6]                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[6]                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[6]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[6]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[7]                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[7]                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[7]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[7]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[5]                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.157     ; 7.261      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[5]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[5]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[3]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[3]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[3]                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[17]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[17]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[15]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[15]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[20]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[20]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[23]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[23]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.157     ; 7.261      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[23]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.157     ; 7.261      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[11]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
; 10.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[11]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 7.262      ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.457 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|dffe4                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.382      ; 2.029      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a39 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a38 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a37 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a36 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a35 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a34 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a33 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a32 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a27 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a26 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a25 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a24 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 3.220      ;
; 2.800 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[0]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.634      ; 3.629      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a63 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a62 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a61 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a60 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a59 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a58 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a57 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a56 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a55 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a54 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a53 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a52 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a51 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a50 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a49 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a48 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a47 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a46 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a45 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a44 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a43 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a42 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a41 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a40 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a31 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a29 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a28 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a23 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a22 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a21 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a20 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a19 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a18 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a17 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 2.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 3.526      ;
; 3.192 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[2]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.649      ; 4.036      ;
; 3.221 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[6]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.634      ; 4.050      ;
; 3.258 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; paddle_mode_reg                                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.188      ; 3.641      ;
; 3.264 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 3.652      ;
; 3.264 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[9]                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 3.652      ;
; 3.264 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 3.653      ;
; 3.264 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 3.652      ;
; 3.264 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 3.652      ;
; 3.264 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 3.653      ;
; 3.264 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 3.652      ;
; 3.264 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[82]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 3.652      ;
; 3.264 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 3.652      ;
; 3.264 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 3.653      ;
; 3.264 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 3.653      ;
; 3.264 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[44]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 3.653      ;
; 3.264 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[363]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 3.652      ;
; 3.264 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[10]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.192      ; 3.651      ;
; 3.264 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[11]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.192      ; 3.651      ;
; 3.264 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[13]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 3.646      ;
; 3.264 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[15]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.192      ; 3.651      ;
; 3.264 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[20]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 3.646      ;
; 3.264 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[1]                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.192      ; 3.651      ;
; 3.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 3.653      ;
; 3.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 3.653      ;
; 3.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 3.653      ;
; 3.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 3.653      ;
; 3.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 3.653      ;
; 3.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 3.653      ;
; 3.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 3.653      ;
; 3.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 3.653      ;
; 3.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 3.653      ;
; 3.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 3.653      ;
; 3.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 3.653      ;
; 3.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[102]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 3.653      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                   ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 3.257 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.640      ;
; 3.257 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.640      ;
; 3.257 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.640      ;
; 3.257 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.640      ;
; 3.257 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.640      ;
; 3.258 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cke_reg                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 3.646      ;
; 3.261 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.654      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.654      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.654      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.654      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.654      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.654      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.654      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.654      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.654      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.654      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.654      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.654      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.654      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.654      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.262 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.651      ;
; 3.263 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 3.658      ;
; 3.263 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 3.658      ;
; 3.263 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 3.658      ;
; 3.263 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 3.658      ;
; 3.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.650      ;
; 3.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.650      ;
; 3.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.650      ;
; 3.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.650      ;
; 3.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.650      ;
; 3.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 3.649      ;
; 3.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.653      ;
; 3.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.653      ;
; 3.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.653      ;
; 3.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.653      ;
; 3.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.653      ;
; 3.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.653      ;
; 3.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.653      ;
; 3.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.653      ;
; 3.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.653      ;
; 3.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 3.649      ;
; 3.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 3.649      ;
; 3.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 3.649      ;
; 3.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.653      ;
; 3.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.653      ;
; 3.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.653      ;
; 3.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.653      ;
; 3.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.653      ;
; 3.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.653      ;
; 3.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.653      ;
; 3.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 3.649      ;
; 3.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 3.649      ;
; 3.451 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 3.752      ;
; 3.451 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 3.752      ;
; 3.452 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 3.753      ;
; 3.452 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 3.753      ;
; 3.468 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.099      ; 3.715      ;
; 3.468 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.099      ; 3.715      ;
; 3.472 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.114      ; 3.734      ;
; 3.472 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.114      ; 3.734      ;
; 3.475 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.102      ; 3.725      ;
; 3.483 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.104      ; 3.735      ;
; 3.483 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.104      ; 3.735      ;
; 3.485 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.111      ; 3.744      ;
; 3.485 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.111      ; 3.744      ;
; 3.487 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 3.729      ;
; 3.489 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 3.734      ;
; 3.489 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 3.734      ;
; 3.786 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.084      ;
; 3.786 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.084      ;
; 3.786 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 4.082      ;
; 3.786 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 4.080      ;
; 3.786 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 4.081      ;
; 3.786 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 4.081      ;
; 3.786 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.083      ;
; 3.786 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 4.082      ;
; 3.787 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.085      ;
; 3.787 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.085      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                             ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cke_reg                      ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|reply_reg                    ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[4]                  ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[5]                  ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[7]                  ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[8]                  ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|udqm_reg                     ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[11]                 ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[6]                  ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[9]                  ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[0]                  ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[10]                 ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[1]                  ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[2]                  ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[3]                  ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                     ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 4.167 ; 4.167        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.167 ; 4.167        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|o                                                                                                                    ;
; 4.244 ; 4.370        ; 0.126          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.286 ; 4.286        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|i                                                                                                                    ;
; 4.329 ; 8.810        ; 4.481          ; Port Rate        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.330 ; 4.439        ; 0.109          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.370 ; 4.370        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.370 ; 4.370        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 4.439 ; 4.439        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.439 ; 4.439        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 4.521 ; 4.521        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|i                                                                                                                    ;
; 4.640 ; 4.640        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.640 ; 4.640        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|o                                                                                                                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                         ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0] ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1] ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2] ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3] ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4] ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]      ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]      ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]      ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]      ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]      ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]      ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]      ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]      ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]      ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]      ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]      ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]       ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]       ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]       ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]       ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]       ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0] ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1] ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2] ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3] ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4] ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]      ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]      ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]      ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]      ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]      ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]      ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]      ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]      ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]      ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]      ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]      ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]       ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]       ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]       ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]       ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]       ;
; 8.444 ; 8.660        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                    ;
; 8.444 ; 8.660        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[10]                                   ;
; 8.444 ; 8.660        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[15]                                   ;
; 8.444 ; 8.660        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[21]                                   ;
; 8.444 ; 8.660        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26]                                   ;
; 8.446 ; 8.662        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                                                          ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[2]                                          ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[3]                                          ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[16]                                   ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[20]                                   ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; user_io:my_user_io|joystick_1[1]                                                                                                                          ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; user_io:my_user_io|joystick_1[2]                                                                                                                          ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; user_io:my_user_io|joystick_1[3]                                                                                                                          ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; user_io:my_user_io|joystick_1[4]                                                                                                                          ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; user_io:my_user_io|joystick_1[5]                                                                                                                          ;
; 8.449 ; 8.665        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[10]                                                                     ;
; 8.449 ; 8.665        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[11]                                                                     ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[5]                                          ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                   ;
; 8.451 ; 8.667        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[3]                                          ;
; 8.451 ; 8.667        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[4]                                          ;
; 8.451 ; 8.667        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[6]                                          ;
; 8.451 ; 8.667        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[7]                                          ;
; 8.451 ; 8.667        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]                                   ;
; 8.451 ; 8.667        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40]                                   ;
; 8.451 ; 8.667        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41]                                   ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[1]                                          ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_control_reg[2]                                                     ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[4]                                          ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[6]                                          ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22]                                   ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[3]                                    ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theOpcode[6]                                  ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]                                                          ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[1]                                          ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                                                  ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                                  ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                                  ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                                  ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                                  ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                                                   ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[4]                                                     ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[5]                                                     ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[5]                                          ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[0]                                          ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[7]                                          ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; user_io:my_user_io|status[5]                                                                                                                              ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                                                                                        ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                        ;
; 8.456 ; 8.672        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|rom_bank[13]                            ;
; 8.456 ; 8.672        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[13]                                   ;
; 8.456 ; 8.672        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19]                                   ;
; 8.456 ; 8.672        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28]                                   ;
; 8.456 ; 8.672        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                   ;
; 8.456 ; 8.672        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[33]                                   ;
; 8.456 ; 8.672        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                   ;
; 8.456 ; 8.672        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39]                                   ;
; 8.456 ; 8.672        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theOpcode[7]                                  ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                           ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                ; Clock Edge ; Target                                                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; 16.280 ; 16.280       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.280 ; 16.280       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.283 ; 16.283       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.294 ; 16.294       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.294 ; 16.294       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.294 ; 16.294       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.294 ; 16.294       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.335 ; 16.335       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.335 ; 16.335       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.335 ; 16.335       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.335 ; 16.335       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.347 ; 16.347       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.350 ; 16.350       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.350 ; 16.350       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'clk_27'                                                                                                               ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target                                                                         ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+
; 18.271 ; 18.455       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.271 ; 18.455       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.271 ; 18.455       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.271 ; 18.455       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.271 ; 18.455       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.271 ; 18.455       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.271 ; 18.455       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.271 ; 18.455       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.271 ; 18.455       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.344 ; 18.344       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.344 ; 18.344       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 18.351 ; 18.351       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.351 ; 18.351       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.361 ; 18.577       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.361 ; 18.577       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.361 ; 18.577       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.361 ; 18.577       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.361 ; 18.577       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.361 ; 18.577       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.361 ; 18.577       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.361 ; 18.577       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.361 ; 18.577       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.400 ; 18.400       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.404 ; 18.404       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.404 ; 18.404       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.404 ; 18.404       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.404 ; 18.404       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.404 ; 18.404       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.404 ; 18.404       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.404 ; 18.404       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.404 ; 18.404       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.404 ; 18.404       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.423 ; 18.423       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.430 ; 18.430       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.606 ; 18.606       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.613 ; 18.613       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.631 ; 18.631       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.631 ; 18.631       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.631 ; 18.631       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.631 ; 18.631       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.631 ; 18.631       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.631 ; 18.631       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.631 ; 18.631       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.631 ; 18.631       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.631 ; 18.631       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.633 ; 18.633       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.633 ; 18.633       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.637 ; 18.637       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.684 ; 18.684       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.684 ; 18.684       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.691 ; 18.691       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.691 ; 18.691       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 33.037 ; 37.037       ; 4.000          ; Port Rate        ; clk_27 ; Rise       ; CLOCK_27[0]                                                                    ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'SPI_SCK'                                                                                                                                        ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                                                                                  ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+
; 20.400 ; 20.630       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ;
; 20.400 ; 20.630       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_we_reg       ;
; 20.402 ; 20.632       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ;
; 20.403 ; 20.633       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 20.403 ; 20.633       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_we_reg       ;
; 20.405 ; 20.635       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 20.507 ; 20.723       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|SPI_MISO~reg0                                                                        ;
; 20.507 ; 20.723       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[0]                                                                   ;
; 20.507 ; 20.723       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[1]                                                                   ;
; 20.507 ; 20.723       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[2]                                                                   ;
; 20.507 ; 20.723       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[3]                                                                   ;
; 20.507 ; 20.723       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[4]                                                                   ;
; 20.507 ; 20.723       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[5]                                                                   ;
; 20.508 ; 20.724       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|SPI_MISO~en                                                                          ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[0]                                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[1]                                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[2]                                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_transfer_end_r                                                                 ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[0]                                                                                    ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[10]                                                                                   ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[1]                                                                                    ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[2]                                                                                    ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[3]                                                                                    ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[4]                                                                                    ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[5]                                                                                    ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[6]                                                                                    ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[7]                                                                                    ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[8]                                                                                    ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[9]                                                                                    ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[3]                                                                                     ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[4]                                                                                     ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[5]                                                                                     ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[6]                                                                                     ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[7]                                                                                     ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[0]                                                                                     ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[1]                                                                                     ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[2]                                                                                     ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[3]                                                                                     ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[4]                                                                                     ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[2]                                                                                    ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[3]                                                                                    ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[4]                                                                                    ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[5]                                                                                    ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[6]                                                                                    ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[0]                                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[1]                                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[2]                                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[3]                                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[4]                                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[5]                                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[6]                                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[7]                                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[8]                                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[9]                                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[0]                                                                      ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[1]                                                                      ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[2]                                                                      ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[3]                                                                      ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[4]                                                                      ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[5]                                                                      ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[6]                                                                      ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[7]                                                                      ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.drive_sel_r[0]                                                       ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[0]                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[10]                                                         ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[11]                                                         ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[12]                                                         ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[15]                                                         ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[16]                                                         ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[18]                                                         ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[19]                                                         ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[20]                                                         ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[23]                                                         ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[24]                                                         ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[26]                                                         ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[27]                                                         ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[28]                                                         ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[2]                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[31]                                                         ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[3]                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[4]                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[7]                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[8]                                                          ;
; 20.554 ; 20.738       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[0]                                                                            ;
; 20.554 ; 20.738       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[1]                                                                            ;
; 20.554 ; 20.738       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[2]                                                                            ;
; 20.554 ; 20.738       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[3]                                                                            ;
; 20.554 ; 20.738       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[4]                                                                            ;
; 20.554 ; 20.738       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[5]                                                                            ;
; 20.554 ; 20.738       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[6]                                                                            ;
; 20.554 ; 20.738       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[0]                                                                     ;
; 20.554 ; 20.738       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[1]                                                                     ;
; 20.554 ; 20.738       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[2]                                                                     ;
; 20.554 ; 20.738       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[3]                                                                     ;
; 20.554 ; 20.738       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[4]                                                                     ;
; 20.554 ; 20.738       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[5]                                                                     ;
; 20.554 ; 20.738       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[6]                                                                     ;
; 20.554 ; 20.738       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[7]                                                                     ;
; 20.554 ; 20.738       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_receiver_strobe_r                                                              ;
; 20.554 ; 20.738       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|osd_enable                                                                                 ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                                                                                                        ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 40.596 ; 41.606       ; 1.010          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                 ;
; 40.713 ; 41.723       ; 1.010          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                 ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                        ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                        ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                        ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                        ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                        ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                        ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                        ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                         ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                         ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[0]                                             ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[0]                                              ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0] ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6] ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0] ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1] ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2] ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3] ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4] ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5] ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6] ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7] ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; rom_loaded                                                                                                                                                                                                    ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                   ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                         ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                         ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                         ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                         ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                         ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                         ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                         ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                         ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_reconfig_write_from_rom                                                                                                                                                      ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                      ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                          ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                          ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                          ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[1]                                             ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[2]                                             ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[3]                                             ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[4]                                             ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[5]                                             ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[6]                                             ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[7]                                             ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[1]                                              ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[2]                                              ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[3]                                              ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[4]                                              ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[5]                                              ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[6]                                              ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[7]                                              ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                    ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[0]  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                               ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                         ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                              ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|rden_a_store                                                                                ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                           ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                           ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                            ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1] ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; 5.242 ; 5.933 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 7.263 ; 7.879 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; 0.669 ; 1.115 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; 1.873 ; 2.385 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 2.636 ; 2.749 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.630 ; 2.743 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.623 ; 2.736 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.636 ; 2.749 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.636 ; 2.749 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.580 ; 2.697 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.590 ; 2.707 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.580 ; 2.697 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.580 ; 2.697 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.617 ; 2.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.617 ; 2.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.611 ; 2.724 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.611 ; 2.724 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.620 ; 2.733 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.620 ; 2.733 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.624 ; 2.737 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.624 ; 2.737 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                        ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; -3.046 ; -3.396 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 0.452  ; 0.154  ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; -0.383 ; -0.805 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; -0.530 ; -0.805 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; -1.684 ; -1.802 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; -1.737 ; -1.851 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; -1.729 ; -1.843 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; -1.742 ; -1.856 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; -1.742 ; -1.856 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; -1.684 ; -1.802 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; -1.694 ; -1.812 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; -1.684 ; -1.802 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; -1.684 ; -1.802 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; -1.724 ; -1.838 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; -1.724 ; -1.838 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; -1.717 ; -1.831 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; -1.717 ; -1.831 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; -1.727 ; -1.841 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; -1.727 ; -1.841 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; -1.730 ; -1.844 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; -1.730 ; -1.844 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                             ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 9.426  ; 8.772  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 3.319  ; 3.129  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 3.163  ; 2.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 3.164  ; 2.971  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 3.165  ; 2.972  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 3.175  ; 2.982  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 3.162  ; 2.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 3.319  ; 3.129  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 3.302  ; 3.112  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 3.307  ; 3.117  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 3.307  ; 3.117  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 3.303  ; 3.113  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 3.164  ; 2.971  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 3.310  ; 3.120  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 3.162  ; 2.969  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 3.162  ; 2.969  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 3.154  ; 2.961  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 2.450  ; 2.326  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 3.318  ; 3.128  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 3.291  ; 3.101  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 3.299  ; 3.109  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 3.147  ; 2.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 3.147  ; 2.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 3.176  ; 2.983  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 3.186  ; 2.993  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 3.176  ; 2.983  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 3.176  ; 2.983  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 3.284  ; 3.094  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 3.284  ; 3.094  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 3.311  ; 3.121  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 3.311  ; 3.121  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 3.142  ; 2.965  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 3.301  ; 3.111  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 3.318  ; 3.128  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 3.159  ; 2.982  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 3.284  ; 3.094  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 3.175  ; 2.982  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 3.163  ; 2.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 3.162  ; 2.969  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 3.175  ; 2.982  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 23.327 ; 22.848 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 23.043 ; 22.604 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 22.712 ; 22.489 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 23.327 ; 22.848 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 22.666 ; 22.326 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 22.649 ; 21.937 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 22.014 ; 21.341 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 21.735 ; 21.303 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 21.408 ; 20.869 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 21.374 ; 20.830 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 21.735 ; 21.303 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 21.339 ; 20.857 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 20.543 ; 19.947 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 18.351 ; 17.631 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 7.411  ; 6.665  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 24.017 ; 23.563 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 23.552 ; 23.104 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 24.017 ; 23.563 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 23.638 ; 23.176 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 23.615 ; 23.114 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 23.666 ; 22.929 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 23.612 ; 23.132 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 6.969  ; 6.058  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -0.884 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -1.122 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                     ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 9.257  ; 8.612  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 2.393  ; 2.207  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 2.396  ; 2.207  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 2.397  ; 2.208  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 2.398  ; 2.209  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 2.408  ; 2.219  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 2.393  ; 2.220  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 2.550  ; 2.364  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 2.534  ; 2.348  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 2.539  ; 2.353  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 2.539  ; 2.353  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 2.535  ; 2.349  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 2.397  ; 2.208  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 2.542  ; 2.356  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 2.387  ; 2.198  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 2.395  ; 2.206  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 2.387  ; 2.198  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 1.717  ; 1.593  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 2.375  ; 2.202  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.524  ; 2.338  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.531  ; 2.345  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.379  ; 2.206  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.379  ; 2.206  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.409  ; 2.220  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.419  ; 2.230  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.409  ; 2.220  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.409  ; 2.220  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.517  ; 2.331  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.517  ; 2.331  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.543  ; 2.357  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.543  ; 2.357  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.375  ; 2.202  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.534  ; 2.348  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.550  ; 2.364  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.391  ; 2.218  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 2.516  ; 2.330  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 2.408  ; 2.219  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 2.396  ; 2.207  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 2.395  ; 2.206  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 2.408  ; 2.219  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 6.358  ; 5.717  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 6.779  ; 6.234  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 6.391  ; 5.717  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 6.694  ; 6.253  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 6.754  ; 6.390  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 7.117  ; 6.134  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 6.358  ; 6.006  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 6.414  ; 5.650  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 6.522  ; 6.080  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 6.790  ; 5.766  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 6.414  ; 5.650  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 6.971  ; 6.473  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 6.458  ; 5.822  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 7.406  ; 6.331  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 6.154  ; 5.430  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 6.491  ; 6.064  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 6.491  ; 6.116  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 7.056  ; 6.250  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 7.090  ; 6.064  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 7.320  ; 6.791  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 7.348  ; 6.381  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 7.373  ; 6.519  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 5.465  ; 4.674  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -1.570 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -1.805 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+----------------------------------------------------------+
; Propagation Delay                                        ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 8.454 ; 8.383 ; 8.786 ; 8.786 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------+
; Minimum Propagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 8.069 ; 7.933 ; 8.254 ; 8.254 ;
+------------+-------------+-------+-------+-------+-------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 7.439 ; 7.439 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 2.825 ; 2.761 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.832 ; 2.768 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.840 ; 2.776 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.847 ; 2.783 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.847 ; 2.783 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.872 ; 2.808 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.882 ; 2.818 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.872 ; 2.808 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.872 ; 2.808 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.825 ; 2.761 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.825 ; 2.761 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.852 ; 2.788 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.852 ; 2.788 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.842 ; 2.778 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.842 ; 2.778 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.859 ; 2.795 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.859 ; 2.795 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                     ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 6.960 ; 6.960 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 1.769 ; 1.707 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.776 ; 1.714 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.783 ; 1.721 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.790 ; 1.728 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.790 ; 1.728 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.792 ; 1.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.802 ; 1.740 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.792 ; 1.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.792 ; 1.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.769 ; 1.707 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.769 ; 1.707 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.795 ; 1.733 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.795 ; 1.733 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.786 ; 1.724 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.786 ; 1.724 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.802 ; 1.740 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.802 ; 1.740 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 7.109     ; 7.180     ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 2.766     ; 2.901     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.773     ; 2.908     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.781     ; 2.916     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.788     ; 2.923     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.788     ; 2.923     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.785     ; 2.948     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.795     ; 2.958     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.785     ; 2.948     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.785     ; 2.948     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.766     ; 2.901     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.766     ; 2.901     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.793     ; 2.928     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.793     ; 2.928     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.783     ; 2.918     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.783     ; 2.918     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.800     ; 2.935     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.800     ; 2.935     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 6.710     ; 6.846     ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 1.780     ; 1.978     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.787     ; 1.985     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.794     ; 1.992     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.801     ; 1.999     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.801     ; 1.999     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.803     ; 1.996     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.813     ; 2.006     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.803     ; 1.996     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.803     ; 1.996     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.780     ; 1.978     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.780     ; 1.978     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.806     ; 2.004     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.806     ; 2.004     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.797     ; 1.995     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.797     ; 1.995     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.813     ; 2.011     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.813     ; 2.011     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                             ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0.323  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.393  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 7.016  ; 0.000         ;
; SPI_SCK                                                               ; 18.226 ; 0.000         ;
; clk_27                                                                ; 35.770 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 39.814 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                             ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.135 ; 0.000         ;
; SPI_SCK                                                               ; 0.153 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 0.160 ; 0.000         ;
; clk_27                                                                ; 0.186 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.187 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.850 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                                          ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 6.422  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 13.615 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                                          ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.687 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.630 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                               ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.186  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 4.331  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.559  ; 0.000         ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 16.300 ; 0.000         ;
; clk_27                                                                ; 17.784 ; 0.000         ;
; SPI_SCK                                                               ; 20.000 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 40.631 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.323 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.958        ; -0.963     ; 0.510      ;
; 2.999 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.140      ; 2.894      ;
; 2.999 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.140      ; 2.894      ;
; 3.006 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.137      ; 2.884      ;
; 3.006 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.137      ; 2.884      ;
; 3.006 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2                 ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.147      ; 2.894      ;
; 3.006 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3                 ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.147      ; 2.894      ;
; 3.013 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.144      ; 2.884      ;
; 3.013 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.144      ; 2.884      ;
; 3.017 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1                 ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.148      ; 2.884      ;
; 3.020 ; sdram_statemachine:sdram_adaptor|dq_output_reg                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.151      ; 2.884      ;
; 3.024 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5                 ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.118      ; 2.847      ;
; 3.027 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9                 ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.148      ; 2.874      ;
; 3.027 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8                 ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.148      ; 2.874      ;
; 3.034 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4                 ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.118      ; 2.837      ;
; 3.035 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6                 ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.119      ; 2.837      ;
; 3.035 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7                 ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.119      ; 2.837      ;
; 3.700 ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                             ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.132      ; 2.185      ;
; 3.701 ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                ; SDRAM_A[5]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.133      ; 2.185      ;
; 3.706 ; sdram_statemachine:sdram_adaptor|addr_reg[11]                               ; SDRAM_A[11]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.138      ; 2.185      ;
; 3.707 ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                             ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.129      ; 2.175      ;
; 3.707 ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                             ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.129      ; 2.175      ;
; 3.713 ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                ; SDRAM_A[7]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.135      ; 2.175      ;
; 3.713 ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                ; SDRAM_A[8]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.135      ; 2.175      ;
; 3.713 ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                ; SDRAM_A[9]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.135      ; 2.175      ;
; 3.714 ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                             ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.136      ; 2.175      ;
; 3.717 ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                ; SDRAM_A[6]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.139      ; 2.175      ;
; 3.718 ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                              ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.140      ; 2.175      ;
; 3.721 ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.143      ; 2.175      ;
; 3.728 ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                              ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.140      ; 2.165      ;
; 3.728 ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                              ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.140      ; 2.165      ;
; 3.729 ; sdram_statemachine:sdram_adaptor|udqm_reg                                   ; SDRAM_DQMH                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.141      ; 2.165      ;
; 3.759 ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                              ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.110      ; 2.104      ;
; 3.769 ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                              ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.110      ; 2.094      ;
; 3.770 ; sdram_statemachine:sdram_adaptor|we_n_reg                                   ; SDRAM_nWE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.111      ; 2.094      ;
; 3.770 ; sdram_statemachine:sdram_adaptor|ldqm_reg                                   ; SDRAM_DQML                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.111      ; 2.094      ;
; 3.770 ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                ; SDRAM_A[3]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.111      ; 2.094      ;
; 3.770 ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                              ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.111      ; 2.094      ;
; 3.770 ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                              ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.111      ; 2.094      ;
; 3.777 ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                ; SDRAM_A[4]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.131      ; 2.107      ;
; 3.778 ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                             ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.132      ; 2.107      ;
; 3.780 ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                ; SDRAM_A[2]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.111      ; 2.084      ;
; 3.781 ; sdram_statemachine:sdram_adaptor|addr_reg[10]                               ; SDRAM_A[10]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.112      ; 2.084      ;
; 3.781 ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                ; SDRAM_A[1]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.112      ; 2.084      ;
; 3.782 ; sdram_statemachine:sdram_adaptor|cas_n_reg                                  ; SDRAM_nCAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.113      ; 2.084      ;
; 3.782 ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                ; SDRAM_A[0]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.113      ; 2.084      ;
; 3.783 ; sdram_statemachine:sdram_adaptor|ba_reg[0]                                  ; SDRAM_BA[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.114      ; 2.084      ;
; 3.784 ; sdram_statemachine:sdram_adaptor|ras_n_reg                                  ; SDRAM_nRAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.115      ; 2.084      ;
; 3.785 ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                              ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.139      ; 2.107      ;
; 3.785 ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                              ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.139      ; 2.107      ;
; 3.791 ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                  ; SDRAM_BA[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.112      ; 2.074      ;
; 3.792 ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                             ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.136      ; 2.097      ;
; 4.257 ; sdram_statemachine:sdram_adaptor|cke_reg                                    ; SDRAM_CKE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.100      ; 1.596      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 2.393 ; SDRAM_DQ[3]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.363     ; 0.949      ;
; 2.393 ; SDRAM_DQ[2]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.363     ; 0.949      ;
; 2.399 ; SDRAM_DQ[0]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.367     ; 0.939      ;
; 2.400 ; SDRAM_DQ[15]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.356     ; 0.949      ;
; 2.400 ; SDRAM_DQ[14]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.356     ; 0.949      ;
; 2.402 ; SDRAM_DQ[5]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.335     ; 0.968      ;
; 2.402 ; SDRAM_DQ[1]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.364     ; 0.939      ;
; 2.405 ; SDRAM_DQ[13]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.361     ; 0.939      ;
; 2.405 ; SDRAM_DQ[12]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.361     ; 0.939      ;
; 2.411 ; SDRAM_DQ[9]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.365     ; 0.929      ;
; 2.411 ; SDRAM_DQ[7]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.336     ; 0.958      ;
; 2.411 ; SDRAM_DQ[6]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.336     ; 0.958      ;
; 2.411 ; SDRAM_DQ[8]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.365     ; 0.929      ;
; 2.412 ; SDRAM_DQ[11]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.354     ; 0.939      ;
; 2.412 ; SDRAM_DQ[10]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.354     ; 0.939      ;
; 2.412 ; SDRAM_DQ[4]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.335     ; 0.958      ;
; 2.861 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.405        ; -0.962     ; 0.510      ;
; 5.803 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 2.853      ;
; 5.821 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.092     ; 2.837      ;
; 5.840 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.063     ; 2.847      ;
; 5.851 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.092     ; 2.807      ;
; 5.857 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 2.799      ;
; 5.865 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.065     ; 2.820      ;
; 5.873 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.064     ; 2.813      ;
; 5.874 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.064     ; 2.812      ;
; 5.898 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.064     ; 2.788      ;
; 5.900 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.064     ; 2.786      ;
; 5.902 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.089     ; 2.759      ;
; 5.911 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.066     ; 2.773      ;
; 5.916 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|cas_n_reg                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.066     ; 2.768      ;
; 5.922 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.066     ; 2.762      ;
; 5.924 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.064     ; 2.762      ;
; 5.927 ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[3]                         ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 2.715      ;
; 5.928 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.067     ; 2.755      ;
; 5.930 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.065     ; 2.755      ;
; 5.937 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.092     ; 2.721      ;
; 5.939 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 2.717      ;
; 5.945 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.064     ; 2.741      ;
; 5.947 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.064     ; 2.739      ;
; 5.954 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.065     ; 2.731      ;
; 5.959 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.065     ; 2.726      ;
; 5.960 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.086     ; 2.704      ;
; 5.961 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.699      ;
; 5.962 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.063     ; 2.725      ;
; 5.966 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.088     ; 2.696      ;
; 5.969 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.065     ; 2.716      ;
; 5.970 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.064     ; 2.716      ;
; 5.971 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.066     ; 2.713      ;
; 5.973 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.065     ; 2.712      ;
; 5.984 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.064     ; 2.702      ;
; 5.984 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.086     ; 2.680      ;
; 5.986 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.063     ; 2.701      ;
; 5.995 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.665      ;
; 5.996 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.064     ; 2.690      ;
; 5.997 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.066     ; 2.687      ;
; 5.997 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.663      ;
; 6.007 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.063     ; 2.680      ;
; 6.010 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.064     ; 2.676      ;
; 6.012 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.087     ; 2.651      ;
; 6.013 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 2.644      ;
; 6.013 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|cas_n_reg                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.066     ; 2.671      ;
; 6.019 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.092     ; 2.639      ;
; 6.021 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.064     ; 2.665      ;
; 6.026 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.065     ; 2.659      ;
; 6.027 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 2.640      ;
; 6.027 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.067     ; 2.656      ;
; 6.027 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.064     ; 2.659      ;
; 6.037 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.080     ; 2.633      ;
; 6.038 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.065     ; 2.647      ;
; 6.041 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.065     ; 2.644      ;
; 6.043 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.092     ; 2.615      ;
; 6.046 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.087     ; 2.617      ;
; 6.048 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.087     ; 2.615      ;
; 6.055 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.605      ;
; 6.056 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.086     ; 2.608      ;
; 6.057 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.088     ; 2.605      ;
; 6.059 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.065     ; 2.626      ;
; 6.061 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.092     ; 2.597      ;
; 6.065 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.065     ; 2.620      ;
; 6.070 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.086     ; 2.594      ;
; 6.072 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.063     ; 2.615      ;
; 6.075 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.065     ; 2.610      ;
; 6.079 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 2.578      ;
; 6.082 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.593      ;
; 6.087 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.082     ; 2.569      ;
; 6.087 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.082     ; 2.569      ;
; 6.092 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.082     ; 2.564      ;
; 6.092 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.082     ; 2.564      ;
; 6.095 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.086     ; 2.569      ;
; 6.097 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.092     ; 2.561      ;
; 6.099 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.080     ; 2.571      ;
; 6.100 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|cas_n_reg                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.066     ; 2.584      ;
; 6.102 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 2.554      ;
; 6.102 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.087     ; 2.549      ;
; 6.102 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.087     ; 2.549      ;
; 6.103 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.064     ; 2.583      ;
; 6.106 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.087     ; 2.557      ;
; 6.107 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.087     ; 2.544      ;
; 6.107 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.087     ; 2.544      ;
; 6.108 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.546      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                 ;
+--------+-----------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                 ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 7.016  ; user_io:my_user_io|ps2_clk                                                                                ; user_io:my_user_io|ps2_kbd_tx_byte[6]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.048     ; 1.734      ;
; 7.016  ; user_io:my_user_io|ps2_clk                                                                                ; user_io:my_user_io|ps2_kbd_tx_byte[5]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.048     ; 1.734      ;
; 7.016  ; user_io:my_user_io|ps2_clk                                                                                ; user_io:my_user_io|ps2_kbd_tx_byte[4]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.048     ; 1.734      ;
; 7.016  ; user_io:my_user_io|ps2_clk                                                                                ; user_io:my_user_io|ps2_kbd_tx_byte[3]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.048     ; 1.734      ;
; 7.016  ; user_io:my_user_io|ps2_clk                                                                                ; user_io:my_user_io|ps2_kbd_tx_byte[2]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.048     ; 1.734      ;
; 7.016  ; user_io:my_user_io|ps2_clk                                                                                ; user_io:my_user_io|ps2_kbd_tx_byte[1]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.048     ; 1.734      ;
; 7.016  ; user_io:my_user_io|ps2_clk                                                                                ; user_io:my_user_io|ps2_kbd_tx_byte[0]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.048     ; 1.734      ;
; 7.054  ; user_io:my_user_io|ps2_clk                                                                                ; user_io:my_user_io|ps2_kbd_parity                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.048     ; 1.696      ;
; 7.265  ; user_io:my_user_io|ps2_clk                                                                                ; user_io:my_user_io|ps2_kbd_tx_state[0]                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.055     ; 1.478      ;
; 7.266  ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0]                               ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:1:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.810        ; -0.962     ; 0.510      ;
; 7.332  ; user_io:my_user_io|ps2_clk                                                                                ; user_io:my_user_io|ps2_kbd_tx_state[2]                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.055     ; 1.411      ;
; 7.333  ; user_io:my_user_io|ps2_clk                                                                                ; user_io:my_user_io|ps2_kbd_tx_state[3]                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.055     ; 1.410      ;
; 7.350  ; user_io:my_user_io|ps2_clk                                                                                ; user_io:my_user_io|ps2_kbd_tx_state[1]                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.055     ; 1.393      ;
; 7.437  ; user_io:my_user_io|ps2_clk                                                                                ; user_io:my_user_io|ps2_kbd_tx_byte[7]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.048     ; 1.313      ;
; 7.457  ; user_io:my_user_io|ps2_clk                                                                                ; user_io:my_user_io|ps2_kbd_rptr[1]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.048     ; 1.293      ;
; 7.533  ; user_io:my_user_io|ps2_clk                                                                                ; user_io:my_user_io|ps2_kbd_rptr[2]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.048     ; 1.217      ;
; 7.556  ; sdram_statemachine:sdram_adaptor|data_out_reg[2]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[2]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; 0.105      ; 1.347      ;
; 7.596  ; user_io:my_user_io|ps2_clk                                                                                ; user_io:my_user_io|ps2_kbd_r_inc                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.052     ; 1.150      ;
; 7.596  ; user_io:my_user_io|ps2_clk                                                                                ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.052     ; 1.150      ;
; 7.628  ; sdram_statemachine:sdram_adaptor|data_out_reg[4]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[4]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.083     ; 1.087      ;
; 7.674  ; sdram_statemachine:sdram_adaptor|data_out_reg[0]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[0]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; 0.099      ; 1.223      ;
; 7.676  ; sdram_statemachine:sdram_adaptor|data_out_reg[5]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[5]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.083     ; 1.039      ;
; 7.682  ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                                                       ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.098     ; 1.018      ;
; 7.699  ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                       ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.098     ; 1.001      ;
; 7.744  ; sdram_statemachine:sdram_adaptor|reply_reg                                                                ; sdram_statemachine:sdram_adaptor|reply_sreg                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.101     ; 0.953      ;
; 7.766  ; sdram_statemachine:sdram_adaptor|data_out_reg[1]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[1]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.082     ; 0.950      ;
; 7.766  ; sdram_statemachine:sdram_adaptor|data_out_reg[15]                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[15]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.095     ; 0.937      ;
; 7.792  ; sdram_statemachine:sdram_adaptor|data_out_reg[8]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[8]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.095     ; 0.911      ;
; 7.795  ; sdram_statemachine:sdram_adaptor|data_out_reg[6]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[6]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; 0.103      ; 1.106      ;
; 7.803  ; sdram_statemachine:sdram_adaptor|data_out_reg[12]                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[12]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.095     ; 0.900      ;
; 7.839  ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                       ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.098     ; 0.861      ;
; 7.842  ; sdram_statemachine:sdram_adaptor|data_out_reg[11]                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[11]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.095     ; 0.861      ;
; 7.855  ; sdram_statemachine:sdram_adaptor|data_out_reg[7]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[7]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.081     ; 0.862      ;
; 7.862  ; sdram_statemachine:sdram_adaptor|data_out_reg[13]                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[13]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.095     ; 0.841      ;
; 7.871  ; sdram_statemachine:sdram_adaptor|data_out_reg[3]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[3]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.082     ; 0.845      ;
; 7.887  ; sdram_statemachine:sdram_adaptor|data_out_reg[10]                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[10]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.095     ; 0.816      ;
; 7.890  ; sdram_statemachine:sdram_adaptor|data_out_reg[9]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[9]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.095     ; 0.813      ;
; 7.920  ; user_io:my_user_io|ps2_clk                                                                                ; user_io:my_user_io|ps2_kbd_rptr[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.052     ; 0.826      ;
; 7.986  ; sdram_statemachine:sdram_adaptor|data_out_reg[14]                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[14]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.080     ; 0.732      ;
; 8.018  ; user_io:my_user_io|ps2_clk                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_clk|ff_reg[2]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.052     ; 0.728      ;
; 8.020  ; user_io:my_user_io|ps2_clk                                                                                ; user_io:my_user_io|ps2_kbd.ps2_clkD                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.052     ; 0.726      ;
; 8.160  ; sdram_statemachine:sdram_adaptor|data_out_reg[17]                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[17]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.092     ; 0.546      ;
; 8.165  ; sdram_statemachine:sdram_adaptor|data_out_reg[27]                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[27]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.092     ; 0.541      ;
; 8.165  ; sdram_statemachine:sdram_adaptor|data_out_reg[31]                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[31]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.092     ; 0.541      ;
; 8.166  ; sdram_statemachine:sdram_adaptor|data_out_reg[24]                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[24]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.092     ; 0.540      ;
; 8.167  ; sdram_statemachine:sdram_adaptor|data_out_reg[16]                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[16]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.092     ; 0.539      ;
; 8.168  ; sdram_statemachine:sdram_adaptor|data_out_reg[29]                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[29]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.087     ; 0.543      ;
; 8.168  ; sdram_statemachine:sdram_adaptor|data_out_reg[19]                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[19]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.086     ; 0.544      ;
; 8.168  ; sdram_statemachine:sdram_adaptor|data_out_reg[23]                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[23]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.086     ; 0.544      ;
; 8.170  ; sdram_statemachine:sdram_adaptor|data_out_reg[26]                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[26]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.087     ; 0.541      ;
; 8.170  ; sdram_statemachine:sdram_adaptor|data_out_reg[18]                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[18]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.087     ; 0.541      ;
; 8.170  ; sdram_statemachine:sdram_adaptor|data_out_reg[30]                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[30]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.087     ; 0.541      ;
; 8.170  ; sdram_statemachine:sdram_adaptor|data_out_reg[20]                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[20]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.087     ; 0.541      ;
; 8.171  ; sdram_statemachine:sdram_adaptor|data_out_reg[25]                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[25]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.086     ; 0.541      ;
; 8.172  ; sdram_statemachine:sdram_adaptor|data_out_reg[28]                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[28]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.086     ; 0.540      ;
; 8.172  ; sdram_statemachine:sdram_adaptor|data_out_reg[21]                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[21]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.086     ; 0.540      ;
; 8.195  ; sdram_statemachine:sdram_adaptor|data_out_reg[22]                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[22]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.086     ; 0.517      ;
; 10.226 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.035     ; 7.347      ;
; 10.226 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.035     ; 7.347      ;
; 10.226 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.035     ; 7.347      ;
; 10.226 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.035     ; 7.347      ;
; 10.226 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.035     ; 7.347      ;
; 10.226 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.035     ; 7.347      ;
; 10.321 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.036     ; 7.251      ;
; 10.321 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.036     ; 7.251      ;
; 10.321 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.036     ; 7.251      ;
; 10.321 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.036     ; 7.251      ;
; 10.321 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.036     ; 7.251      ;
; 10.321 ; ioctl_state.IOCTL_IDLE                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.036     ; 7.251      ;
; 10.377 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.035     ; 7.196      ;
; 10.377 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.035     ; 7.196      ;
; 10.377 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.035     ; 7.196      ;
; 10.377 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.035     ; 7.196      ;
; 10.377 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.035     ; 7.196      ;
; 10.377 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.035     ; 7.196      ;
; 10.380 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.033     ; 7.195      ;
; 10.380 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.033     ; 7.195      ;
; 10.380 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.033     ; 7.195      ;
; 10.380 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.033     ; 7.195      ;
; 10.380 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.033     ; 7.195      ;
; 10.380 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.033     ; 7.195      ;
; 10.393 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.033     ; 7.182      ;
; 10.393 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.033     ; 7.182      ;
; 10.393 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.033     ; 7.182      ;
; 10.393 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.033     ; 7.182      ;
; 10.411 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.052     ; 7.145      ;
; 10.415 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.062     ; 7.131      ;
; 10.416 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[14]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.043     ; 7.149      ;
; 10.416 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.034     ; 7.158      ;
; 10.416 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.034     ; 7.158      ;
; 10.416 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.034     ; 7.158      ;
; 10.416 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.034     ; 7.158      ;
; 10.416 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.034     ; 7.158      ;
; 10.416 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.034     ; 7.158      ;
; 10.446 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[12]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.040     ; 7.122      ;
; 10.449 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 7.113      ;
; 10.449 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 7.113      ;
; 10.449 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 7.113      ;
; 10.456 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.045     ; 7.107      ;
; 10.456 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.045     ; 7.107      ;
+--------+-----------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'SPI_SCK'                                                                                                                        ;
+--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                             ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 18.226 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 3.164      ;
; 18.226 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 3.164      ;
; 18.226 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 3.164      ;
; 18.226 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 3.164      ;
; 18.226 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 3.164      ;
; 18.279 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 3.111      ;
; 18.301 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 3.089      ;
; 18.301 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 3.089      ;
; 18.301 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 3.089      ;
; 18.301 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 3.089      ;
; 18.301 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 3.089      ;
; 18.334 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 3.056      ;
; 18.334 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 3.056      ;
; 18.334 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 3.056      ;
; 18.334 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 3.056      ;
; 18.334 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 3.056      ;
; 18.372 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 3.018      ;
; 18.396 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.994      ;
; 18.456 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.934      ;
; 18.456 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.934      ;
; 18.456 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.934      ;
; 18.456 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.934      ;
; 18.456 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.934      ;
; 18.527 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.863      ;
; 18.631 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|spi_byte_out[0]    ; SPI_SCK      ; SPI_SCK     ; 20.800       ; -0.607     ; 1.549      ;
; 18.632 ; user_io:my_user_io|serial_out_rptr[2] ; user_io:my_user_io|spi_byte_out[0]    ; SPI_SCK      ; SPI_SCK     ; 20.800       ; -0.607     ; 1.548      ;
; 18.714 ; user_io:my_user_io|serial_out_rptr[1] ; user_io:my_user_io|spi_byte_out[0]    ; SPI_SCK      ; SPI_SCK     ; 20.800       ; -0.607     ; 1.466      ;
; 18.749 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.641      ;
; 18.749 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.641      ;
; 18.749 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.641      ;
; 18.749 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.641      ;
; 18.749 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.641      ;
; 18.785 ; user_io:my_user_io|serial_out_rptr[3] ; user_io:my_user_io|spi_byte_out[0]    ; SPI_SCK      ; SPI_SCK     ; 20.800       ; -0.607     ; 1.395      ;
; 18.794 ; user_io:my_user_io|serial_out_rptr[4] ; user_io:my_user_io|spi_byte_out[0]    ; SPI_SCK      ; SPI_SCK     ; 20.800       ; -0.607     ; 1.386      ;
; 18.795 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.595      ;
; 18.806 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.584      ;
; 18.806 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.584      ;
; 18.806 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.584      ;
; 18.806 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.584      ;
; 18.806 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.584      ;
; 18.852 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.538      ;
; 18.873 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.533      ; 2.513      ;
; 18.873 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.533      ; 2.513      ;
; 18.873 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.533      ; 2.513      ;
; 18.873 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.533      ; 2.513      ;
; 18.873 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.533      ; 2.513      ;
; 18.889 ; user_io:my_user_io|serial_out_rptr[5] ; user_io:my_user_io|spi_byte_out[0]    ; SPI_SCK      ; SPI_SCK     ; 20.800       ; -0.607     ; 1.291      ;
; 18.919 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.533      ; 2.467      ;
; 18.964 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.533      ; 2.422      ;
; 18.964 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.533      ; 2.422      ;
; 18.964 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.533      ; 2.422      ;
; 18.964 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.533      ; 2.422      ;
; 18.964 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.533      ; 2.422      ;
; 18.965 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.425      ;
; 18.965 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.425      ;
; 18.965 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.425      ;
; 18.965 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.425      ;
; 18.965 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.425      ;
; 19.010 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.533      ; 2.376      ;
; 19.011 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.379      ;
; 19.099 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.533      ; 2.287      ;
; 19.099 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.533      ; 2.287      ;
; 19.099 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.533      ; 2.287      ;
; 19.099 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.533      ; 2.287      ;
; 19.099 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.533      ; 2.287      ;
; 19.145 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.533      ; 2.241      ;
; 19.212 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.178      ;
; 19.212 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.178      ;
; 19.212 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.178      ;
; 19.212 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.178      ;
; 19.212 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.178      ;
; 19.258 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.132      ;
; 19.281 ; user_io:my_user_io|cmd[6]             ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.513      ; 2.085      ;
; 19.281 ; user_io:my_user_io|cmd[6]             ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.513      ; 2.085      ;
; 19.281 ; user_io:my_user_io|cmd[6]             ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.513      ; 2.085      ;
; 19.281 ; user_io:my_user_io|cmd[6]             ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.513      ; 2.085      ;
; 19.281 ; user_io:my_user_io|cmd[6]             ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.513      ; 2.085      ;
; 19.283 ; user_io:my_user_io|cmd[7]             ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.513      ; 2.083      ;
; 19.283 ; user_io:my_user_io|cmd[7]             ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.513      ; 2.083      ;
; 19.283 ; user_io:my_user_io|cmd[7]             ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.513      ; 2.083      ;
; 19.283 ; user_io:my_user_io|cmd[7]             ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.513      ; 2.083      ;
; 19.283 ; user_io:my_user_io|cmd[7]             ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.513      ; 2.083      ;
; 19.283 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.107      ;
; 19.283 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.107      ;
; 19.283 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.107      ;
; 19.283 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.107      ;
; 19.283 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.107      ;
; 19.296 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.513      ; 2.070      ;
; 19.296 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.513      ; 2.070      ;
; 19.296 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.513      ; 2.070      ;
; 19.296 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.513      ; 2.070      ;
; 19.296 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.513      ; 2.070      ;
; 19.327 ; user_io:my_user_io|cmd[6]             ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.513      ; 2.039      ;
; 19.329 ; user_io:my_user_io|cmd[7]             ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.513      ; 2.037      ;
; 19.329 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.537      ; 2.061      ;
; 19.342 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.513      ; 2.024      ;
; 19.414 ; user_io:my_user_io|cmd[5]             ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.513      ; 1.952      ;
; 19.414 ; user_io:my_user_io|cmd[5]             ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.513      ; 1.952      ;
; 19.414 ; user_io:my_user_io|cmd[5]             ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.513      ; 1.952      ;
; 19.414 ; user_io:my_user_io|cmd[5]             ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.513      ; 1.952      ;
+--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'clk_27'                                                                                                                                                                 ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 35.770 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 1.217      ;
; 35.785 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 1.202      ;
; 35.837 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 1.150      ;
; 35.842 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 1.145      ;
; 35.851 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 1.136      ;
; 35.853 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 1.134      ;
; 35.857 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 1.130      ;
; 35.898 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 1.089      ;
; 35.908 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 1.079      ;
; 35.909 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 1.078      ;
; 35.914 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 1.073      ;
; 35.918 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 1.069      ;
; 35.925 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 1.062      ;
; 35.965 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 1.022      ;
; 35.986 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 1.001      ;
; 35.986 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 1.001      ;
; 35.989 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.998      ;
; 35.990 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.997      ;
; 35.999 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.988      ;
; 36.029 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.958      ;
; 36.033 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.954      ;
; 36.082 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.905      ;
; 36.089 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.898      ;
; 36.089 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.898      ;
; 36.094 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.893      ;
; 36.095 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.892      ;
; 36.109 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.878      ;
; 36.111 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.876      ;
; 36.113 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.874      ;
; 36.115 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.872      ;
; 36.136 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.851      ;
; 36.153 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.834      ;
; 36.156 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.831      ;
; 36.161 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.826      ;
; 36.168 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.819      ;
; 36.168 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.819      ;
; 36.171 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.816      ;
; 36.177 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.810      ;
; 36.178 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.809      ;
; 36.194 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.793      ;
; 36.203 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.784      ;
; 36.236 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.751      ;
; 36.236 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.751      ;
; 36.238 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.749      ;
; 36.245 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.742      ;
; 36.247 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.740      ;
; 36.251 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.736      ;
; 36.251 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.736      ;
; 36.256 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.731      ;
; 36.257 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.730      ;
; 36.266 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.721      ;
; 36.327 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.660      ;
; 36.332 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.655      ;
; 36.333 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.654      ;
; 36.334 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.653      ;
; 36.404 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.583      ;
; 36.441 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.546      ;
; 36.442 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.545      ;
; 36.449 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.538      ;
; 36.628 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.037     ; 0.359      ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 39.814 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_we_reg ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.331     ; 2.707      ;
; 39.871 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.966      ; 3.749      ;
; 40.463 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.975      ; 3.166      ;
; 40.486 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.975      ; 3.143      ;
; 40.561 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.975      ; 3.068      ;
; 40.766 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.144     ; 1.942      ;
; 40.777 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.144     ; 1.931      ;
; 40.871 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.144     ; 1.837      ;
; 40.920 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.140     ; 1.792      ;
; 40.920 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.144     ; 1.788      ;
; 40.934 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.144     ; 1.774      ;
; 40.948 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.146     ; 1.758      ;
; 41.035 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.140     ; 1.677      ;
; 41.113 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.140     ; 1.599      ;
; 41.187 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.140     ; 1.525      ;
; 41.198 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate3_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.017     ; 0.438      ;
; 41.513 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.140     ; 1.199      ;
; 41.571 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                             ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.146     ; 1.135      ;
; 78.949 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.021     ; 5.549      ;
; 79.973 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.046     ; 3.301      ;
; 80.104 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.046     ; 3.170      ;
; 80.613 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 2.670      ;
; 80.636 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 2.647      ;
; 80.711 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 2.572      ;
; 80.760 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 2.523      ;
; 80.783 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 2.500      ;
; 80.858 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 2.425      ;
; 80.936 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                                                 ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.141      ; 2.547      ;
; 80.936 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                                                 ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.141      ; 2.547      ;
; 81.002 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.144      ; 2.484      ;
; 81.002 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.144      ; 2.484      ;
; 81.007 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.144      ; 2.479      ;
; 81.007 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.144      ; 2.479      ;
; 81.033 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                                                ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.141      ; 2.450      ;
; 81.033 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                                                ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.141      ; 2.450      ;
; 81.060 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.144      ; 2.426      ;
; 81.060 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.144      ; 2.426      ;
; 81.086 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.144      ; 2.400      ;
; 81.086 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.144      ; 2.400      ;
; 81.141 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.149      ; 2.350      ;
; 81.144 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.144      ; 2.342      ;
; 81.144 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.144      ; 2.342      ;
; 81.145 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.339      ;
; 81.145 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.339      ;
; 81.159 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.144      ; 2.327      ;
; 81.159 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.144      ; 2.327      ;
; 81.215 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_last_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.141      ; 2.268      ;
; 81.223 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.144      ; 2.263      ;
; 81.223 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.144      ; 2.263      ;
; 81.226 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.149      ; 2.265      ;
; 81.229 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.035     ; 2.056      ;
; 81.247 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.035     ; 2.038      ;
; 81.297 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.144      ; 2.189      ;
; 81.297 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.144      ; 2.189      ;
; 81.334 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.035     ; 1.951      ;
; 81.337 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.035     ; 1.948      ;
; 81.361 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.035     ; 1.924      ;
; 81.364 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.141      ; 2.119      ;
; 81.382 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.035     ; 1.903      ;
; 81.389 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 1.966      ; 3.897      ;
; 81.400 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.043     ; 1.877      ;
; 81.400 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.043     ; 1.877      ;
; 81.400 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.043     ; 1.877      ;
; 81.400 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.043     ; 1.877      ;
; 81.400 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.043     ; 1.877      ;
; 81.400 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.043     ; 1.877      ;
; 81.400 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.043     ; 1.877      ;
; 81.400 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.043     ; 1.877      ;
; 81.405 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.035     ; 1.880      ;
; 81.406 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.042     ; 1.872      ;
; 81.418 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.866      ;
; 81.418 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.866      ;
; 81.418 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.866      ;
; 81.418 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.866      ;
; 81.418 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.866      ;
; 81.418 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.866      ;
; 81.418 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.866      ;
; 81.418 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.866      ;
; 81.423 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.035     ; 1.862      ;
; 81.425 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.859      ;
; 81.425 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.859      ;
; 81.425 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.859      ;
; 81.425 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.859      ;
; 81.425 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.859      ;
; 81.425 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.859      ;
; 81.425 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.859      ;
; 81.425 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.859      ;
; 81.427 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.035     ; 1.858      ;
; 81.434 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.042     ; 1.844      ;
; 81.449 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.035     ; 1.836      ;
; 81.457 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.042     ; 1.821      ;
; 81.473 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 1.810      ;
; 81.473 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 1.810      ;
; 81.473 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 1.810      ;
; 81.473 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 1.810      ;
; 81.473 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 1.810      ;
; 81.473 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 1.810      ;
; 81.473 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 1.810      ;
; 81.473 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 1.810      ;
; 81.479 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.805      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                     ; To Node                                                                                                                                                                                                                                 ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.135 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.226      ; 0.465      ;
; 0.137 ; zpu_secbuf_addr[4]                                                                                                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.464      ;
; 0.137 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[7]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.463      ;
; 0.137 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.466      ;
; 0.138 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.467      ;
; 0.138 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.467      ;
; 0.139 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.468      ;
; 0.140 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[2]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.466      ;
; 0.140 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.466      ;
; 0.144 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.470      ;
; 0.144 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.226      ; 0.474      ;
; 0.144 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[7]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.470      ;
; 0.145 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.474      ;
; 0.146 ; zpu_secbuf_addr[1]                                                                                                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.468      ;
; 0.146 ; zpu_secbuf_d[2]                                                                                                                                                                                               ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.471      ;
; 0.146 ; user_io:my_user_io|sd_dout[2]                                                                                                                                                                                 ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.470      ;
; 0.146 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.472      ;
; 0.146 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.475      ;
; 0.146 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.471      ;
; 0.147 ; user_io:my_user_io|sd_dout[1]                                                                                                                                                                                 ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.471      ;
; 0.147 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.473      ;
; 0.148 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.474      ;
; 0.150 ; zpu_secbuf_addr[0]                                                                                                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.477      ;
; 0.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.479      ;
; 0.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.476      ;
; 0.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.226      ; 0.480      ;
; 0.151 ; zpu_secbuf_addr[5]                                                                                                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.475      ;
; 0.152 ; user_io:my_user_io|sd_dout[0]                                                                                                                                                                                 ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.476      ;
; 0.152 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[7]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.478      ;
; 0.152 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[2]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.477      ;
; 0.152 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.477      ;
; 0.153 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.482      ;
; 0.153 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[7]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.478      ;
; 0.153 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[5]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.478      ;
; 0.154 ; user_io:my_user_io|sd_dout[6]                                                                                                                                                                                 ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.478      ;
; 0.154 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.483      ;
; 0.155 ; user_io:my_user_io|sd_dout[5]                                                                                                                                                                                 ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.479      ;
; 0.156 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[6]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_address_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.481      ;
; 0.156 ; zpu_secbuf_d[7]                                                                                                                                                                                               ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.484      ;
; 0.156 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.481      ;
; 0.157 ; user_io:my_user_io|sd_dout[7]                                                                                                                                                                                 ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.481      ;
; 0.157 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.483      ;
; 0.157 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[2]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.482      ;
; 0.158 ; zpu_secbuf_addr[6]                                                                                                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.485      ;
; 0.158 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[2]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.229      ; 0.491      ;
; 0.158 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.484      ;
; 0.159 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[1]                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_datain_reg0           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.487      ;
; 0.159 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[7]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.488      ;
; 0.159 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.484      ;
; 0.160 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[7]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_address_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.485      ;
; 0.160 ; user_io:my_user_io|sd_buff_addr[0]                                                                                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.482      ;
; 0.160 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.229      ; 0.493      ;
; 0.161 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.487      ;
; 0.162 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[1]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_address_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.487      ;
; 0.162 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[7]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.491      ;
; 0.163 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[3]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_address_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.488      ;
; 0.163 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[3]                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_datain_reg0           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.491      ;
; 0.164 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[4]                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_datain_reg0           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.492      ;
; 0.165 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[0]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_address_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.490      ;
; 0.165 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[6]                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_datain_reg0           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.493      ;
; 0.165 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.490      ;
; 0.167 ; user_io:my_user_io|sd_buff_addr[7]                                                                                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.489      ;
; 0.171 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[2]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_address_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.496      ;
; 0.174 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[0]                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_datain_reg0           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.502      ;
; 0.175 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[5]                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_datain_reg0           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.503      ;
; 0.178 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[5]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_address_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.503      ;
; 0.178 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[0]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[0]                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 0.307      ;
; 0.178 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[1]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[1]                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[3]                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.504      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|cntr_tnf:cntr1|counter_reg_bit[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_address_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.505      ;
; 0.180 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[3]                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.503      ;
; 0.181 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[0]                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.506      ;
; 0.182 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[2]                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.507      ;
; 0.182 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[0]                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.505      ;
; 0.182 ; user_io:my_user_io|sd_buff_addr[8]                                                                                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.504      ;
; 0.183 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[1]                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.508      ;
; 0.183 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[2]                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.506      ;
; 0.184 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[1]                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.507      ;
; 0.184 ; user_io:my_user_io|ps2_clk                                                                                                                                                                                    ; user_io:my_user_io|ps2_clk                                                                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 0.307      ;
; 0.185 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[2]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[2]                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 0.314      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[4]                                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[4]                                                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; data_io:mist_data_io|abyte_cnt[1]                                                                                                                                                                             ; data_io:mist_data_io|abyte_cnt[1]                                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; data_io:mist_data_io|abyte_cnt[2]                                                                                                                                                                             ; data_io:mist_data_io|abyte_cnt[2]                                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; data_io:mist_data_io|abyte_cnt[0]                                                                                                                                                                             ; data_io:mist_data_io|abyte_cnt[0]                                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; data_io:mist_data_io|ioctl_download                                                                                                                                                                           ; data_io:mist_data_io|ioctl_download                                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; data_io:mist_data_io|hi                                                                                                                                                                                       ; data_io:mist_data_io|hi                                                                                                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; data_io:mist_data_io|wr_int                                                                                                                                                                                   ; data_io:mist_data_io|wr_int                                                                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ioctl_state.IOCTL_ACK                                                                                                                                                                                         ; ioctl_state.IOCTL_ACK                                                                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[9]                                                                                                                                                                 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[9]                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ioctl_state.IOCTL_UNLOAD                                                                                                                                                                                      ; ioctl_state.IOCTL_UNLOAD                                                                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[118]                                                                                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[118]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'SPI_SCK'                                                                                                                                                                                               ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                  ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.153 ; osd:osd_inst|sbuf[2]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.226      ; 0.483      ;
; 0.159 ; osd:osd_inst|bcnt[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.221      ; 0.484      ;
; 0.160 ; osd:osd_inst|bcnt[8]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.219      ; 0.483      ;
; 0.160 ; osd:osd_inst|sbuf[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.223      ; 0.487      ;
; 0.161 ; osd:osd_inst|bcnt[6]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.221      ; 0.486      ;
; 0.163 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.228      ; 0.495      ;
; 0.167 ; osd:osd_inst|bcnt[8]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.221      ; 0.492      ;
; 0.167 ; osd:osd_inst|bcnt[0]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.219      ; 0.490      ;
; 0.173 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.228      ; 0.505      ;
; 0.173 ; osd:osd_inst|sbuf[6]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.228      ; 0.505      ;
; 0.175 ; osd:osd_inst|bcnt[3]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.221      ; 0.500      ;
; 0.182 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.219      ; 0.505      ;
; 0.182 ; osd:osd_inst|bcnt[7]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.219      ; 0.505      ;
; 0.183 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.228      ; 0.515      ;
; 0.185 ; user_io:my_user_io|serial_out_rptr[0]      ; user_io:my_user_io|serial_out_rptr[0]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.307      ;
; 0.186 ; data_io:mist_data_io|bit_cnt[1]            ; data_io:mist_data_io|bit_cnt[1]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; data_io:mist_data_io|bit_cnt[2]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; user_io:my_user_io|cmd[5]                  ; user_io:my_user_io|cmd[5]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; user_io:my_user_io|cmd[3]                  ; user_io:my_user_io|cmd[3]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; user_io:my_user_io|cmd[6]                  ; user_io:my_user_io|cmd[6]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; user_io:my_user_io|cmd[7]                  ; user_io:my_user_io|cmd[7]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; user_io:my_user_io|cmd[1]                  ; user_io:my_user_io|cmd[1]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.307      ;
; 0.187 ; user_io:my_user_io|cmd[2]                  ; user_io:my_user_io|cmd[2]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|cmd[0]                  ; user_io:my_user_io|cmd[0]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|cmd[4]                  ; user_io:my_user_io|cmd[4]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|bit_cnt[1]              ; user_io:my_user_io|bit_cnt[1]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|bit_cnt[2]              ; user_io:my_user_io|bit_cnt[2]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; osd:osd_inst|osd_enable                    ; osd:osd_inst|osd_enable                                                                                 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|byte_cnt[0]             ; user_io:my_user_io|byte_cnt[0]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.307      ;
; 0.193 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[0]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; data_io:mist_data_io|spi_receiver_strobe_r ; data_io:mist_data_io|spi_receiver_strobe_r                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.314      ;
; 0.194 ; user_io:my_user_io|spi_receiver_strobe_r   ; user_io:my_user_io|spi_receiver_strobe_r                                                                ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; user_io:my_user_io|bit_cnt[0]              ; user_io:my_user_io|bit_cnt[0]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.314      ;
; 0.196 ; data_io:mist_data_io|sbuf[6]               ; data_io:mist_data_io|spi_byte_in[7]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.316      ;
; 0.197 ; data_io:mist_data_io|sbuf[2]               ; data_io:mist_data_io|sbuf[3]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.317      ;
; 0.197 ; data_io:mist_data_io|sbuf[3]               ; data_io:mist_data_io|spi_byte_in[4]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.317      ;
; 0.197 ; data_io:mist_data_io|sbuf[4]               ; data_io:mist_data_io|spi_byte_in[5]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.317      ;
; 0.197 ; data_io:mist_data_io|sbuf[1]               ; data_io:mist_data_io|spi_byte_in[2]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.317      ;
; 0.198 ; data_io:mist_data_io|sbuf[3]               ; data_io:mist_data_io|sbuf[4]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.318      ;
; 0.198 ; data_io:mist_data_io|sbuf[4]               ; data_io:mist_data_io|sbuf[5]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.318      ;
; 0.198 ; data_io:mist_data_io|sbuf[5]               ; data_io:mist_data_io|sbuf[6]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.318      ;
; 0.199 ; data_io:mist_data_io|sbuf[5]               ; data_io:mist_data_io|spi_byte_in[6]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.319      ;
; 0.200 ; data_io:mist_data_io|sbuf[0]               ; data_io:mist_data_io|sbuf[1]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.320      ;
; 0.200 ; data_io:mist_data_io|sbuf[2]               ; data_io:mist_data_io|spi_byte_in[3]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.320      ;
; 0.200 ; data_io:mist_data_io|sbuf[0]               ; data_io:mist_data_io|spi_byte_in[1]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.320      ;
; 0.201 ; user_io:my_user_io|sbuf[4]                 ; user_io:my_user_io|spi_byte_in[5]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.322      ;
; 0.201 ; user_io:my_user_io|sbuf[4]                 ; user_io:my_user_io|sbuf[5]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.322      ;
; 0.201 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|spi_byte_in[6]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.322      ;
; 0.201 ; data_io:mist_data_io|sbuf[1]               ; data_io:mist_data_io|sbuf[2]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.321      ;
; 0.202 ; osd:osd_inst|cnt[4]                        ; osd:osd_inst|cnt[4]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.322      ;
; 0.203 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|sbuf[6]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.324      ;
; 0.204 ; user_io:my_user_io|sbuf[6]                 ; user_io:my_user_io|cmd[7]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.325      ;
; 0.205 ; osd:osd_inst|sbuf[0]                       ; osd:osd_inst|sbuf[1]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.325      ;
; 0.207 ; osd:osd_inst|sbuf[2]                       ; osd:osd_inst|sbuf[3]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.328      ;
; 0.209 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[1]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.330      ;
; 0.209 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.330      ;
; 0.211 ; user_io:my_user_io|sbuf[2]                 ; user_io:my_user_io|cmd[3]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.332      ;
; 0.211 ; osd:osd_inst|sbuf[2]                       ; osd:osd_inst|cmd[3]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.332      ;
; 0.212 ; user_io:my_user_io|sbuf[2]                 ; user_io:my_user_io|sbuf[3]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.333      ;
; 0.212 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|cmd[6]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.333      ;
; 0.212 ; user_io:my_user_io|bit_cnt[0]              ; user_io:my_user_io|bit_cnt[1]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.332      ;
; 0.213 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|sbuf[5]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.334      ;
; 0.213 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|cmd[5]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.334      ;
; 0.214 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|sbuf[6]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.335      ;
; 0.218 ; user_io:my_user_io|bit_cnt[1]              ; user_io:my_user_io|bit_cnt[2]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.338      ;
; 0.265 ; osd:osd_inst|bcnt[10]                      ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.219      ; 0.588      ;
; 0.275 ; osd:osd_inst|bcnt[2]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.219      ; 0.598      ;
; 0.277 ; user_io:my_user_io|sbuf[1]                 ; user_io:my_user_io|sbuf[2]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.398      ;
; 0.278 ; user_io:my_user_io|sbuf[3]                 ; user_io:my_user_io|sbuf[4]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.399      ;
; 0.278 ; osd:osd_inst|bcnt[10]                      ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.221      ; 0.603      ;
; 0.281 ; osd:osd_inst|sbuf[6]                       ; osd:osd_inst|cmd[7]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.402      ;
; 0.287 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|cmd[4]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.408      ;
; 0.288 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|sbuf[4]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.409      ;
; 0.297 ; user_io:my_user_io|serial_out_rptr[2]      ; user_io:my_user_io|serial_out_rptr[2]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.419      ;
; 0.298 ; user_io:my_user_io|serial_out_rptr[3]      ; user_io:my_user_io|serial_out_rptr[3]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.420      ;
; 0.298 ; user_io:my_user_io|serial_out_rptr[4]      ; user_io:my_user_io|serial_out_rptr[4]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.420      ;
; 0.298 ; user_io:my_user_io|serial_out_rptr[5]      ; user_io:my_user_io|serial_out_rptr[5]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.420      ;
; 0.301 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|cmd[6]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.422      ;
; 0.302 ; data_io:mist_data_io|bit_cnt[1]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.423      ;
; 0.304 ; user_io:my_user_io|sbuf[4]                 ; user_io:my_user_io|cmd[5]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.425      ;
; 0.304 ; osd:osd_inst|cnt[1]                        ; osd:osd_inst|cnt[1]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.424      ;
; 0.304 ; user_io:my_user_io|serial_out_rptr[0]      ; user_io:my_user_io|serial_out_rptr[1]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.426      ;
; 0.304 ; user_io:my_user_io|serial_out_rptr[1]      ; user_io:my_user_io|serial_out_rptr[1]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.426      ;
; 0.305 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|bcnt[1]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.425      ;
; 0.305 ; osd:osd_inst|bcnt[8]                       ; osd:osd_inst|bcnt[8]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.425      ;
; 0.305 ; osd:osd_inst|bcnt[10]                      ; osd:osd_inst|bcnt[10]                                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.425      ;
; 0.305 ; user_io:my_user_io|byte_cnt[4]             ; user_io:my_user_io|byte_cnt[4]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.425      ;
; 0.306 ; osd:osd_inst|cnt[2]                        ; osd:osd_inst|cnt[2]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; osd:osd_inst|bcnt[3]                       ; osd:osd_inst|bcnt[3]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; osd:osd_inst|bcnt[6]                       ; osd:osd_inst|bcnt[6]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; osd:osd_inst|bcnt[7]                       ; osd:osd_inst|bcnt[7]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; osd:osd_inst|bcnt[9]                       ; osd:osd_inst|bcnt[9]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.426      ;
; 0.307 ; osd:osd_inst|bcnt[2]                       ; osd:osd_inst|bcnt[2]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.427      ;
; 0.307 ; osd:osd_inst|bcnt[4]                       ; osd:osd_inst|bcnt[4]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.427      ;
; 0.307 ; osd:osd_inst|bcnt[5]                       ; osd:osd_inst|bcnt[5]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.427      ;
; 0.308 ; osd:osd_inst|sbuf[0]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.223      ; 0.635      ;
; 0.311 ; osd:osd_inst|cnt[3]                        ; osd:osd_inst|cnt[3]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.431      ;
; 0.311 ; user_io:my_user_io|byte_cnt[3]             ; user_io:my_user_io|byte_cnt[3]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.431      ;
; 0.311 ; user_io:my_user_io|bit_cnt[0]              ; user_io:my_user_io|bit_cnt[2]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.431      ;
; 0.312 ; osd:osd_inst|cnt[0]                        ; osd:osd_inst|cnt[0]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.432      ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                     ; To Node                                                                                                                                                                                                                               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.160 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.486      ;
; 0.186 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; rom_loaded                                                                                                                                                                                                    ; rom_loaded                                                                                                                                                                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.193 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.314      ;
; 0.194 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                          ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.195 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                          ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.315      ;
; 0.197 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.317      ;
; 0.197 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.317      ;
; 0.201 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                               ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.221      ; 0.526      ;
; 0.203 ; rom_loaded                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.323      ;
; 0.205 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.325      ;
; 0.205 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_init_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.326      ;
; 0.215 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[6]                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.335      ;
; 0.217 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.337      ;
; 0.223 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.343      ;
; 0.227 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.347      ;
; 0.233 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.353      ;
; 0.233 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.353      ;
; 0.233 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.353      ;
; 0.238 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.564      ;
; 0.256 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.377      ;
; 0.257 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.378      ;
; 0.260 ; switch_pal_ntsc:pll_switcher|pll_reconfig_write_from_rom                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.380      ;
; 0.266 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[3]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[3]                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.387      ;
; 0.267 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[7]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[7]                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.388      ;
; 0.268 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[5]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[5]                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.389      ;
; 0.268 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[1]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[1]                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.389      ;
; 0.268 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[0]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[0]                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.389      ;
; 0.269 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[4]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[4]                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.389      ;
; 0.272 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.393      ;
; 0.274 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|tmp_seq_ena_state                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_ena_state                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.395      ;
; 0.279 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.400      ;
; 0.292 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.412      ;
; 0.292 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.412      ;
; 0.293 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.293 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.294 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.295 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.621      ;
; 0.296 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.622      ;
; 0.297 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.623      ;
; 0.298 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.298 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.417      ;
; 0.299 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.300 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.301 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.421      ;
; 0.302 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.628      ;
; 0.304 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.425      ;
; 0.305 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.425      ;
; 0.305 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.425      ;
; 0.306 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.307 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.427      ;
; 0.307 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.427      ;
; 0.308 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.428      ;
; 0.308 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.428      ;
; 0.308 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.428      ;
; 0.308 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.429      ;
; 0.309 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.429      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'clk_27'                                                                                                                                                                 ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.307      ;
; 0.299 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.420      ;
; 0.299 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.420      ;
; 0.305 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.426      ;
; 0.371 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.492      ;
; 0.373 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.494      ;
; 0.373 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.494      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.534      ;
; 0.428 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.549      ;
; 0.429 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.550      ;
; 0.430 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.551      ;
; 0.432 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.553      ;
; 0.432 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.553      ;
; 0.432 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.553      ;
; 0.447 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.568      ;
; 0.449 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.570      ;
; 0.450 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.571      ;
; 0.457 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.578      ;
; 0.458 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.579      ;
; 0.460 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.581      ;
; 0.472 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.593      ;
; 0.473 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.594      ;
; 0.473 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.594      ;
; 0.491 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.612      ;
; 0.492 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.613      ;
; 0.493 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.614      ;
; 0.495 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.616      ;
; 0.497 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.618      ;
; 0.507 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.628      ;
; 0.507 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.628      ;
; 0.509 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.630      ;
; 0.509 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.630      ;
; 0.509 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.630      ;
; 0.509 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.630      ;
; 0.509 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.630      ;
; 0.510 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.631      ;
; 0.513 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.634      ;
; 0.524 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.645      ;
; 0.527 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.648      ;
; 0.531 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.652      ;
; 0.532 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.653      ;
; 0.532 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.653      ;
; 0.556 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.677      ;
; 0.557 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.678      ;
; 0.568 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.689      ;
; 0.569 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.690      ;
; 0.608 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.729      ;
; 0.609 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.730      ;
; 0.609 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.730      ;
; 0.609 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.730      ;
; 0.609 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.730      ;
; 0.618 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.739      ;
; 0.633 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.754      ;
; 0.634 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.755      ;
; 0.637 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.758      ;
; 0.641 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.762      ;
; 0.642 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.763      ;
; 0.675 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.796      ;
; 0.706 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.827      ;
; 0.707 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.037      ; 0.828      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                             ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                     ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.187 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.194 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.229 ; sdram_statemachine:sdram_adaptor|request_sreg                 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 0.425      ;
; 0.293 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.414      ;
; 0.293 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.414      ;
; 0.294 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.294 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.295 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.416      ;
; 0.295 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.416      ;
; 0.295 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.416      ;
; 0.297 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.418      ;
; 0.298 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.298 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.298 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.299 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.420      ;
; 0.299 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.420      ;
; 0.299 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.420      ;
; 0.299 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.420      ;
; 0.299 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.420      ;
; 0.302 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.423      ;
; 0.303 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.424      ;
; 0.304 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.425      ;
; 0.304 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.425      ;
; 0.305 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.426      ;
; 0.308 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.429      ;
; 0.309 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.430      ;
; 0.310 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.431      ;
; 0.310 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.431      ;
; 0.310 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.431      ;
; 0.311 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.432      ;
; 0.311 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.432      ;
; 0.312 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.433      ;
; 0.313 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.434      ;
; 0.313 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.434      ;
; 0.314 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.435      ;
; 0.315 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.436      ;
; 0.315 ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.436      ;
; 0.317 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.438      ;
; 0.318 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.439      ;
; 0.325 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.445      ;
; 0.426 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.546      ;
; 0.437 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.557      ;
; 0.442 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.563      ;
; 0.443 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.564      ;
; 0.443 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.564      ;
; 0.446 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.567      ;
; 0.447 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.568      ;
; 0.448 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.569      ;
; 0.448 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.569      ;
; 0.451 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.572      ;
; 0.451 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.572      ;
; 0.452 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.573      ;
; 0.453 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.574      ;
; 0.453 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.574      ;
; 0.453 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.574      ;
; 0.453 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.574      ;
; 0.454 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.575      ;
; 0.454 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.575      ;
; 0.456 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.577      ;
; 0.456 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.577      ;
; 0.456 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.577      ;
; 0.457 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.578      ;
; 0.457 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.578      ;
; 0.457 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.578      ;
; 0.458 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.579      ;
; 0.459 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.580      ;
; 0.459 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.580      ;
; 0.460 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.581      ;
; 0.460 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.581      ;
; 0.460 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.581      ;
; 0.460 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.581      ;
; 0.461 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.582      ;
; 0.461 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.582      ;
; 0.462 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.583      ;
; 0.463 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.584      ;
; 0.463 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.584      ;
; 0.464 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.585      ;
; 0.466 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.587      ;
; 0.466 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.587      ;
; 0.467 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.588      ;
; 0.468 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.589      ;
; 0.469 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.590      ;
; 0.469 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.590      ;
; 0.470 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.591      ;
; 0.472 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.593      ;
; 0.472 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.593      ;
; 0.473 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.594      ;
; 0.475 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.596      ;
; 0.476 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.597      ;
; 0.478 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.599      ;
; 0.486 ; sdram_statemachine:sdram_adaptor|WRITE_EN_sreg                ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 0.682      ;
; 0.490 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.610      ;
; 0.500 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.620      ;
; 0.505 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.626      ;
; 0.506 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.627      ;
; 0.506 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.627      ;
; 0.509 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.630      ;
; 0.509 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.630      ;
; 0.509 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.630      ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.850 ; sdram_statemachine:sdram_adaptor|cke_reg                                    ; SDRAM_CKE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.268      ; 1.581      ;
; 2.082 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9                 ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.320      ; 1.865      ;
; 2.082 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8                 ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.320      ; 1.865      ;
; 2.090 ; sdram_statemachine:sdram_adaptor|dq_output_reg                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.322      ; 1.875      ;
; 2.093 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1                 ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.319      ; 1.875      ;
; 2.096 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.316      ; 1.875      ;
; 2.096 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.316      ; 1.875      ;
; 2.103 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.309      ; 1.875      ;
; 2.103 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.309      ; 1.875      ;
; 2.104 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2                 ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.318      ; 1.885      ;
; 2.104 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3                 ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.318      ; 1.885      ;
; 2.104 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6                 ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.291      ; 1.858      ;
; 2.104 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7                 ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.291      ; 1.858      ;
; 2.105 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4                 ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.290      ; 1.858      ;
; 2.111 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.311      ; 1.885      ;
; 2.111 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.311      ; 1.885      ;
; 2.115 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5                 ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.290      ; 1.868      ;
; 2.182 ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                  ; SDRAM_BA[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.284      ; 1.929      ;
; 2.186 ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                             ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.307      ; 1.956      ;
; 2.190 ; sdram_statemachine:sdram_adaptor|ras_n_reg                                  ; SDRAM_nRAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.286      ; 1.939      ;
; 2.191 ; sdram_statemachine:sdram_adaptor|ba_reg[0]                                  ; SDRAM_BA[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.285      ; 1.939      ;
; 2.191 ; sdram_statemachine:sdram_adaptor|cas_n_reg                                  ; SDRAM_nCAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.285      ; 1.939      ;
; 2.192 ; sdram_statemachine:sdram_adaptor|addr_reg[10]                               ; SDRAM_A[10]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.284      ; 1.939      ;
; 2.192 ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                ; SDRAM_A[0]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.284      ; 1.939      ;
; 2.193 ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                ; SDRAM_A[1]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.283      ; 1.939      ;
; 2.193 ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                ; SDRAM_A[2]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.283      ; 1.939      ;
; 2.194 ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                              ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.309      ; 1.966      ;
; 2.194 ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                              ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.309      ; 1.966      ;
; 2.201 ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                ; SDRAM_A[4]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.302      ; 1.966      ;
; 2.201 ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                             ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.302      ; 1.966      ;
; 2.204 ; sdram_statemachine:sdram_adaptor|we_n_reg                                   ; SDRAM_nWE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.282      ; 1.949      ;
; 2.204 ; sdram_statemachine:sdram_adaptor|ldqm_reg                                   ; SDRAM_DQML                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.282      ; 1.949      ;
; 2.204 ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                ; SDRAM_A[3]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.282      ; 1.949      ;
; 2.204 ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                              ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.282      ; 1.949      ;
; 2.204 ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                              ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.282      ; 1.949      ;
; 2.205 ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                              ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.281      ; 1.949      ;
; 2.215 ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                              ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.281      ; 1.959      ;
; 2.231 ; sdram_statemachine:sdram_adaptor|udqm_reg                                   ; SDRAM_DQMH                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.311      ; 2.005      ;
; 2.231 ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                              ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.311      ; 2.005      ;
; 2.231 ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                              ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.311      ; 2.005      ;
; 2.239 ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.313      ; 2.015      ;
; 2.242 ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                              ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.310      ; 2.015      ;
; 2.243 ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                ; SDRAM_A[6]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.309      ; 2.015      ;
; 2.245 ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                             ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.307      ; 2.015      ;
; 2.246 ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                ; SDRAM_A[9]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.306      ; 2.015      ;
; 2.247 ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                ; SDRAM_A[7]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.305      ; 2.015      ;
; 2.247 ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                ; SDRAM_A[8]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.305      ; 2.015      ;
; 2.252 ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                             ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.300      ; 2.015      ;
; 2.252 ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                             ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.300      ; 2.015      ;
; 2.253 ; sdram_statemachine:sdram_adaptor|addr_reg[11]                               ; SDRAM_A[11]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.309      ; 2.025      ;
; 2.258 ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                ; SDRAM_A[5]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.304      ; 2.025      ;
; 2.260 ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                             ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.302      ; 2.025      ;
; 7.982 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -6.853       ; -0.826     ; 0.470      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                 ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                      ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 6.422 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 2.200      ;
; 6.428 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 2.201      ;
; 6.429 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 2.191      ;
; 6.429 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 2.191      ;
; 6.429 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.123     ; 2.198      ;
; 6.429 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.125     ; 2.196      ;
; 6.429 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 2.193      ;
; 6.430 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|udqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 2.190      ;
; 6.431 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.184     ; 2.133      ;
; 6.431 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.184     ; 2.133      ;
; 6.431 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 2.187      ;
; 6.433 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.186     ; 2.129      ;
; 6.435 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 2.194      ;
; 6.435 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 2.194      ;
; 6.435 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.124     ; 2.191      ;
; 6.435 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.124     ; 2.191      ;
; 6.436 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.126     ; 2.188      ;
; 6.436 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.126     ; 2.188      ;
; 6.437 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.175     ; 2.136      ;
; 6.437 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.175     ; 2.136      ;
; 6.437 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 2.184      ;
; 6.438 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.180     ; 2.130      ;
; 6.438 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.180     ; 2.130      ;
; 6.439 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.183     ; 2.126      ;
; 6.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.119     ; 2.188      ;
; 6.443 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.119     ; 2.188      ;
; 6.445 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 2.130      ;
; 6.445 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 2.130      ;
; 6.445 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 2.177      ;
; 6.445 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 2.177      ;
; 6.447 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.182     ; 2.119      ;
; 6.447 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.182     ; 2.119      ;
; 6.457 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.104     ; 2.189      ;
; 6.458 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.192      ;
; 6.458 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.192      ;
; 6.458 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.101     ; 2.191      ;
; 6.458 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.101     ; 2.191      ;
; 6.458 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.189      ;
; 6.458 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 2.187      ;
; 6.458 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.104     ; 2.188      ;
; 6.458 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.189      ;
; 6.458 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.102     ; 2.190      ;
; 6.458 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.102     ; 2.190      ;
; 6.458 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.101     ; 2.191      ;
; 6.458 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.189      ;
; 6.459 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.101     ; 2.190      ;
; 6.459 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.101     ; 2.190      ;
; 6.460 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.155     ; 2.133      ;
; 6.460 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.154     ; 2.134      ;
; 6.460 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.155     ; 2.133      ;
; 6.460 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.154     ; 2.134      ;
; 6.529 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.139     ; 2.070      ;
; 6.529 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.139     ; 2.070      ;
; 6.531 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 2.066      ;
; 6.535 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 2.073      ;
; 6.535 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 2.073      ;
; 6.536 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.135     ; 2.067      ;
; 6.536 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.135     ; 2.067      ;
; 6.537 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.138     ; 2.063      ;
; 6.543 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 2.067      ;
; 6.543 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 2.067      ;
; 6.545 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 2.056      ;
; 6.545 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 2.056      ;
; 6.558 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.109     ; 2.071      ;
; 6.558 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.109     ; 2.071      ;
; 6.558 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.110     ; 2.070      ;
; 6.558 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.110     ; 2.070      ;
; 6.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 2.032      ;
; 6.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 2.032      ;
; 6.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 2.032      ;
; 6.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 2.032      ;
; 6.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 2.032      ;
; 6.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 2.032      ;
; 6.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 2.032      ;
; 6.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 2.032      ;
; 6.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 2.032      ;
; 6.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 2.032      ;
; 6.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 2.032      ;
; 6.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 2.032      ;
; 6.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 2.032      ;
; 6.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 2.032      ;
; 6.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 2.032      ;
; 6.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 2.032      ;
; 6.670 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.099     ; 2.028      ;
; 6.670 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.099     ; 2.028      ;
; 6.670 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.099     ; 2.028      ;
; 6.670 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.099     ; 2.028      ;
; 6.670 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.099     ; 2.028      ;
; 6.670 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.099     ; 2.028      ;
; 6.676 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.091     ; 2.030      ;
; 6.676 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.091     ; 2.030      ;
; 6.676 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.091     ; 2.030      ;
; 6.676 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.091     ; 2.030      ;
; 6.676 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.091     ; 2.030      ;
; 6.681 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.085     ; 2.031      ;
; 6.681 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.085     ; 2.031      ;
; 6.681 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.085     ; 2.031      ;
; 6.681 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.085     ; 2.031      ;
; 6.681 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.085     ; 2.031      ;
; 6.681 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.085     ; 2.031      ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                           ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 13.615 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 3.905      ;
; 13.615 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 3.899      ;
; 13.615 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 3.899      ;
; 13.615 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 3.899      ;
; 13.625 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 3.898      ;
; 13.625 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 3.898      ;
; 13.625 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 3.898      ;
; 13.625 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 3.898      ;
; 13.625 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[20]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 3.898      ;
; 13.631 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 3.889      ;
; 13.631 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 3.889      ;
; 13.631 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_32BIT_WRITE_ENABLE_reg                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 3.889      ;
; 13.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.092     ; 3.884      ;
; 13.632 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.092     ; 3.884      ;
; 13.648 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 3.871      ;
; 13.648 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 3.871      ;
; 13.648 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 3.871      ;
; 13.648 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 3.871      ;
; 13.802 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.099      ; 3.905      ;
; 13.803 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.095      ; 3.900      ;
; 13.815 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[3]                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.706      ;
; 13.815 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.100     ; 3.693      ;
; 13.815 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[13]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.100     ; 3.693      ;
; 13.815 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[8]                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.100     ; 3.693      ;
; 13.815 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.100     ; 3.693      ;
; 13.815 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[12]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.100     ; 3.693      ;
; 13.815 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[14]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.100     ; 3.693      ;
; 13.815 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[15]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.100     ; 3.693      ;
; 13.815 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.100     ; 3.693      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|memory_ready_reg                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.701      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 3.707      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 3.707      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 3.707      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 3.707      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 3.707      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[16] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[12] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 3.707      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_safe_reg                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.083     ; 3.705      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.083     ; 3.705      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[1]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[2]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[3]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[4]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[5]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[6]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[7]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[8]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[9]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[10]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[11]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[12]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[13]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[14]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[15]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[16]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[17]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[18]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[19]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[20]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[21]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[22]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[23]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[24]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[25]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[26]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[27]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 3.707      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[28]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[24]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 3.707      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[29]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[30]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[31]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.706      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[21]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 3.707      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 3.707      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[20]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 3.707      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[23]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 3.707      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 3.707      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.698      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.698      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.mstr_ack         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 3.700      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.slv_ack1         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 3.700      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.rd               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 3.700      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.slv_ack2         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 3.700      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.wr               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 3.700      ;
; 13.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 3.699      ;
; 13.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[15] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 3.706      ;
; 13.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[14] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 3.706      ;
; 13.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 3.706      ;
; 13.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.705      ;
; 13.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.705      ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.687 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|dffe4                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 0.982      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a39 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a38 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a37 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a36 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a35 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a34 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a33 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a32 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a27 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a26 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a25 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a24 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 1.560      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a63 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a62 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a61 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a60 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a59 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a58 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a57 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a56 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a55 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a54 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a53 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a52 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a51 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a50 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a49 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a48 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a47 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a46 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a45 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a44 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a43 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a42 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a41 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a40 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a31 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a29 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a28 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a23 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a22 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a21 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a20 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a19 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a18 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a17 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 1.720      ;
; 1.447 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[0]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.285      ; 1.816      ;
; 1.634 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[2]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.292      ; 2.010      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[9]                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[82]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[102]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[44]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[363]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 1.831      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[10]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 1.830      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[11]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 1.830      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[13]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 1.826      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[15]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 1.830      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[20]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 1.826      ;
; 1.642 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[1]                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 1.830      ;
; 1.643 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[6]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.289      ; 2.016      ;
; 1.643 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[3]                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 1.825      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                   ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.831      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.831      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.831      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.831      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.831      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.831      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.831      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.831      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.831      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.831      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.831      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.831      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.831      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.630 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.830      ;
; 1.631 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.832      ;
; 1.631 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.100      ; 1.834      ;
; 1.631 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.827      ;
; 1.631 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.827      ;
; 1.631 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.827      ;
; 1.631 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.827      ;
; 1.631 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.827      ;
; 1.631 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.100      ; 1.834      ;
; 1.631 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.100      ; 1.834      ;
; 1.631 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.100      ; 1.834      ;
; 1.631 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cke_reg                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.096      ; 1.830      ;
; 1.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.091      ; 1.830      ;
; 1.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.091      ; 1.830      ;
; 1.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.091      ; 1.830      ;
; 1.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.091      ; 1.830      ;
; 1.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.091      ; 1.830      ;
; 1.644 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.830      ;
; 1.644 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.833      ;
; 1.644 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.833      ;
; 1.644 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.833      ;
; 1.644 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.833      ;
; 1.644 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.833      ;
; 1.644 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.833      ;
; 1.644 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.833      ;
; 1.644 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.833      ;
; 1.644 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.833      ;
; 1.644 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.830      ;
; 1.644 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.830      ;
; 1.644 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.830      ;
; 1.644 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.833      ;
; 1.644 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.833      ;
; 1.644 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.833      ;
; 1.644 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.833      ;
; 1.644 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.833      ;
; 1.644 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.833      ;
; 1.644 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.833      ;
; 1.644 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.830      ;
; 1.644 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.830      ;
; 1.717 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.878      ;
; 1.717 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.878      ;
; 1.718 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 1.878      ;
; 1.718 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 1.878      ;
; 1.733 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.059      ; 1.875      ;
; 1.733 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.059      ; 1.875      ;
; 1.735 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.049      ; 1.867      ;
; 1.735 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.049      ; 1.867      ;
; 1.739 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.048      ; 1.870      ;
; 1.740 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.052      ; 1.875      ;
; 1.740 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.052      ; 1.875      ;
; 1.742 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.056      ; 1.881      ;
; 1.742 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.056      ; 1.881      ;
; 1.746 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.045      ; 1.874      ;
; 1.747 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.048      ; 1.878      ;
; 1.747 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.048      ; 1.878      ;
; 1.838 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.001      ;
; 1.838 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.001      ;
; 1.838 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.999      ;
; 1.838 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.996      ;
; 1.838 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.998      ;
; 1.838 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.085      ; 2.000      ;
; 1.838 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.085      ; 2.000      ;
; 1.838 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.998      ;
; 1.838 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[1]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.999      ;
; 1.838 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.085      ; 2.000      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                             ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cke_reg                      ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|reply_reg                    ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ;
; 4.189 ; 4.344        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ;
; 4.189 ; 4.344        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ;
; 4.191 ; 4.346        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ;
; 4.191 ; 4.346        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ;
; 4.191 ; 4.346        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg                ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ;
; 4.194 ; 4.349        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                 ;
; 4.194 ; 4.349        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                 ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]                ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]                ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                 ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                 ;
; 4.196 ; 4.351        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                ;
; 4.196 ; 4.351        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                ;
; 4.196 ; 4.351        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                 ;
; 4.198 ; 4.353        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                 ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                     ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 4.331 ; 4.400        ; 0.069          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.357 ; 4.410        ; 0.053          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.378 ; 4.378        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.378 ; 4.378        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|i                                                                                                                    ;
; 4.378 ; 4.378        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|o                                                                                                                    ;
; 4.400 ; 4.400        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.400 ; 4.400        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 4.410 ; 4.410        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.410 ; 4.410        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 4.431 ; 4.431        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.431 ; 4.431        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|i                                                                                                                    ;
; 4.431 ; 4.431        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|o                                                                                                                    ;
; 4.810 ; 8.810        ; 4.000          ; Port Rate        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                         ;
+-------+--------------+----------------+-----------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type            ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                                                                                                                     ;
+-------+--------------+----------------+-----------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.559 ; 8.789        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_address_reg0                                                                                              ;
; 8.559 ; 8.789        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg                                                                                                    ;
; 8.559 ; 8.789        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_address_reg0                                                                                              ;
; 8.559 ; 8.789        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg                                                                                                    ;
; 8.559 ; 8.789        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a3~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_we_reg       ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_address_reg0                                 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_we_reg                                       ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_address_reg0   ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a4~porta_address_reg0                                                                                              ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a4~porta_we_reg                                                                                                    ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a10~porta_address_reg0                                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a12~porta_address_reg0                                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a13~porta_address_reg0                                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a14~porta_address_reg0                                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a23~porta_address_reg0                                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a5~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a6~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a7~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a8~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a9~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_address_reg0                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_we_reg                                                                                                                 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_address_reg0                                                                                                          ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_we_reg                                                                                                                ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                  ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_address_reg0                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_we_reg                                                                                                                  ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_address_reg0             ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_we_reg                   ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|altsyncram_gd81:FIFOram|ram_block1a0~porta_address_reg0           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|altsyncram_gd81:FIFOram|ram_block1a0~porta_we_reg                 ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_address_reg0    ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~portb_address_reg0   ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0                                                                                               ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0                                                                                               ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a4~porta_address_reg0                                                                                              ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a4~porta_we_reg                                                                                                    ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a11~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                          ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                              ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_we_reg                                                                                                                                    ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_datain_reg0                                  ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~portb_address_reg0    ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0    ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|gtia_palette:palette4|altsyncram:Mux18_rtl_0|altsyncram_vq01:auto_generated|ram_block1a0~porta_address_reg0                                                                                                       ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a4~porta_datain_reg0                                                                                               ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                            ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a4~porta_address_reg0                                                                                                                            ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                            ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_datain_reg0                                                                                                            ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                            ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_datain_reg0                                                                                                           ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                             ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_datain_reg0                                                                                                             ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_datain_reg0              ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|altsyncram_gd81:FIFOram|ram_block1a0~porta_datain_reg0            ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                              ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_we_reg                                                                                                                                    ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0     ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                    ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a4~porta_datain_reg0                                                                                               ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a1~porta_address_reg0                                                                                                                            ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_address_reg0                                                                                                           ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_we_reg                                                                                                                 ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                           ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~portb_address_reg0             ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                               ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a17                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a18                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a19                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a20                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a21                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a22                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a23                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a28                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a29                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a30                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a31                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a40                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a41                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a42                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a43                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a44                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a45                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a46                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a47                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a48                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a49                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a50                      ;
+-------+--------------+----------------+-----------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                           ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                ; Clock Edge ; Target                                                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.310 ; 16.310       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.310 ; 16.310       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.315 ; 16.315       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.316 ; 16.316       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.321 ; 16.321       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.321 ; 16.321       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.330 ; 16.330       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.330 ; 16.330       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.330 ; 16.330       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.330 ; 16.330       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'clk_27'                                                                                                               ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target                                                                         ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 17.928 ; 17.928       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 17.928 ; 17.928       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 17.929 ; 17.929       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 17.929 ; 17.929       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 17.960 ; 17.960       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 17.962 ; 17.962       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 17.962 ; 17.962       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 17.962 ; 17.962       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 17.962 ; 17.962       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 17.962 ; 17.962       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 17.962 ; 17.962       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 17.962 ; 17.962       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 17.962 ; 17.962       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 17.962 ; 17.962       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 17.970 ; 17.970       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 17.971 ; 17.971       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 17.972 ; 17.972       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 17.972 ; 17.972       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.853 ; 19.069       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.853 ; 19.069       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.853 ; 19.069       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.853 ; 19.069       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.853 ; 19.069       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.853 ; 19.069       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.853 ; 19.069       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.853 ; 19.069       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.853 ; 19.069       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 19.064 ; 19.064       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 19.064 ; 19.064       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 19.066 ; 19.066       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 19.067 ; 19.067       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 19.077 ; 19.077       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 19.107 ; 19.107       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 19.107 ; 19.107       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 19.108 ; 19.108       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 19.108 ; 19.108       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 33.037 ; 37.037       ; 4.000          ; Port Rate        ; clk_27 ; Rise       ; CLOCK_27[0]                                                                    ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'SPI_SCK'                                                                                                                                        ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                                                                                  ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+
; 20.000 ; 20.230       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 20.000 ; 20.230       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_we_reg       ;
; 20.000 ; 20.230       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ;
; 20.000 ; 20.230       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_we_reg       ;
; 20.002 ; 20.232       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 20.002 ; 20.232       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ;
; 20.023 ; 20.239       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|SPI_MISO~en                                                                          ;
; 20.023 ; 20.239       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|SPI_MISO~reg0                                                                        ;
; 20.023 ; 20.239       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[0]                                                                   ;
; 20.023 ; 20.239       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[1]                                                                   ;
; 20.023 ; 20.239       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[2]                                                                   ;
; 20.023 ; 20.239       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[3]                                                                   ;
; 20.023 ; 20.239       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[4]                                                                   ;
; 20.023 ; 20.239       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[5]                                                                   ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[0]                                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[1]                                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[2]                                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[0]                                                                            ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[1]                                                                            ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[2]                                                                            ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[3]                                                                            ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[4]                                                                            ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[5]                                                                            ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[6]                                                                            ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[0]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[1]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[2]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[3]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[4]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[5]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[6]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[7]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_transfer_end_r                                                                 ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[0]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[10]                                                                                   ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[1]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[2]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[3]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[4]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[5]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[6]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[7]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[8]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[9]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[0]                                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[1]                                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[2]                                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[3]                                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[4]                                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|osd_enable                                                                                 ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[0]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[1]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[0]                                                                           ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[1]                                                                           ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[2]                                                                           ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[0]                                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[1]                                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[2]                                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[3]                                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[4]                                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[5]                                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[6]                                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[7]                                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[8]                                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[9]                                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[0]                                                                               ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[2]                                                                               ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[4]                                                                               ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[0]                                                                       ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[1]                                                                       ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[2]                                                                       ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[4]                                                                       ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[7]                                                                       ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[0]                                                                      ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[1]                                                                      ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[2]                                                                      ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[3]                                                                      ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[4]                                                                      ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[5]                                                                      ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[6]                                                                      ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[7]                                                                      ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_receiver_strobe_r                                                                ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transfer_end_r                                                                   ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.drive_sel_r[0]                                                       ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[0]                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[10]                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[11]                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[12]                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[13]                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[14]                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[15]                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[16]                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[17]                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[18]                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[19]                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[1]                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[20]                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[21]                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[22]                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[23]                                                         ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                      ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                                                                                                                                ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 40.631 ; 41.641       ; 1.010          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ;
; 40.680 ; 41.690       ; 1.010          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ;
; 41.415 ; 41.645       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ;
; 41.415 ; 41.645       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_we_reg       ;
; 41.417 ; 41.647       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 41.418 ; 41.648       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ;
; 41.418 ; 41.648       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ;
; 41.419 ; 41.649       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|q_a[0]                                                                                                              ;
; 41.419 ; 41.649       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pal_rom:pll_rom_pal|altsyncram:altsyncram_component|altsyncram_gfr3:auto_generated|q_a[0]                                                                                                                ;
; 41.437 ; 41.653       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate3_state                                                                   ;
; 41.448 ; 41.664       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[2]                                                                     ;
; 41.448 ; 41.664       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[4]                                                                     ;
; 41.448 ; 41.664       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[6]                                                                     ;
; 41.448 ; 41.664       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[4]                                                                      ;
; 41.448 ; 41.664       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                                                       ;
; 41.448 ; 41.664       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                                                      ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                           ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                 ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                 ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                 ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                 ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                 ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                 ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                 ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                 ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[0]                                                                     ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[1]                                                                     ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[3]                                                                     ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[5]                                                                     ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[7]                                                                     ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[0]                                                                      ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[1]                                                                      ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[3]                                                                      ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[5]                                                                      ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[6]                                                                      ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[7]                                                                      ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[0]                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                        ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                                                 ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; rom_loaded                                                                                                                                                                                                                            ;
; 41.450 ; 41.680       ; 0.230          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|q_a[0]                                                                                                              ;
; 41.450 ; 41.680       ; 0.230          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pal_rom:pll_rom_pal|altsyncram:altsyncram_component|altsyncram_gfr3:auto_generated|q_a[0]                                                                                                                ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                                ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                                ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                                ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                                ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                                ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                                ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                                ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                                 ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                                 ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_reconfig_write_from_rom                                                                                                                                                                              ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                      ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                                              ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                                  ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                                  ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                                  ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[2]                                                                      ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0]                         ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1]                         ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2]                         ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3]                         ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4]                         ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5]                         ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                         ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7]                         ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                                        ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|rden_a_store                                                                                                        ;
; 41.452 ; 41.682       ; 0.230          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ;
; 41.452 ; 41.682       ; 0.230          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                          ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                          ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                                          ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                          ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                          ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; 2.746 ; 3.416 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 3.671 ; 3.939 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; 0.325 ; 0.795 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; 1.011 ; 1.383 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 1.471 ; 2.023 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.465 ; 2.017 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.462 ; 2.014 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.471 ; 2.023 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.471 ; 2.023 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.446 ; 2.004 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.456 ; 2.014 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.447 ; 2.005 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.447 ; 2.005 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.453 ; 2.005 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.453 ; 2.005 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.452 ; 2.004 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.452 ; 2.004 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.459 ; 2.011 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.459 ; 2.011 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.464 ; 2.016 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.464 ; 2.016 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                        ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; -1.563 ; -2.324 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 0.171  ; -0.255 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; -0.174 ; -0.666 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; -0.288 ; -0.720 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; -0.968 ; -1.526 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; -0.988 ; -1.540 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; -0.985 ; -1.537 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; -0.994 ; -1.546 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; -0.994 ; -1.546 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; -0.968 ; -1.526 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; -0.978 ; -1.536 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; -0.969 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; -0.969 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; -0.975 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; -0.975 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; -0.974 ; -1.526 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; -0.974 ; -1.526 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; -0.981 ; -1.533 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; -0.981 ; -1.533 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; -0.987 ; -1.539 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; -0.987 ; -1.539 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                             ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 5.577  ; 5.431  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 1.615  ; 1.481  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 1.534  ; 1.413  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 1.535  ; 1.414  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 1.536  ; 1.415  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 1.546  ; 1.425  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 1.539  ; 1.424  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 1.615  ; 1.481  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 1.599  ; 1.465  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 1.603  ; 1.469  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 1.603  ; 1.469  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 1.603  ; 1.469  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 1.535  ; 1.414  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 1.610  ; 1.476  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 1.533  ; 1.412  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 1.533  ; 1.412  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 1.525  ; 1.404  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 1.059  ; 1.053  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 1.616  ; 1.482  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.595  ; 1.461  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.598  ; 1.464  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.531  ; 1.416  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.531  ; 1.416  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.547  ; 1.426  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.557  ; 1.436  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.546  ; 1.425  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.546  ; 1.425  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.588  ; 1.454  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.588  ; 1.454  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.609  ; 1.475  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.609  ; 1.475  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.524  ; 1.409  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.602  ; 1.468  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.616  ; 1.482  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.538  ; 1.423  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 1.587  ; 1.453  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 1.546  ; 1.425  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 1.534  ; 1.413  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 1.532  ; 1.411  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 1.546  ; 1.425  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 10.330 ; 10.325 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 10.204 ; 10.270 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 10.165 ; 10.166 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 10.330 ; 10.325 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 10.125 ; 10.162 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 9.963  ; 10.067 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 9.662  ; 9.804  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 9.633  ; 9.655  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 9.461  ; 9.483  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 9.474  ; 9.540  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 9.633  ; 9.655  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 9.468  ; 9.536  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 9.037  ; 9.089  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 8.178  ; 8.278  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 3.814  ; 3.607  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 10.730 ; 10.741 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 10.460 ; 10.514 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 10.730 ; 10.741 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 10.559 ; 10.587 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 10.542 ; 10.584 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 10.430 ; 10.555 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 10.498 ; 10.518 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 3.521  ; 3.386  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -1.808 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -1.834 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                     ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 5.492  ; 5.342  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 1.105  ; 0.986  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 1.105  ; 0.986  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 1.106  ; 0.987  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 1.106  ; 0.987  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 1.117  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 1.108  ; 0.995  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 1.184  ; 1.052  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 1.169  ; 1.037  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 1.173  ; 1.041  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 1.173  ; 1.041  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 1.172  ; 1.040  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 1.105  ; 0.986  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 1.179  ; 1.047  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 1.095  ; 0.976  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 1.104  ; 0.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 1.095  ; 0.976  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 0.651  ; 0.644  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 1.093  ; 0.980  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.165  ; 1.033  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.168  ; 1.036  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.101  ; 0.988  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.101  ; 0.988  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.118  ; 0.999  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.128  ; 1.009  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.117  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.117  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.157  ; 1.025  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.157  ; 1.025  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.178  ; 1.046  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.178  ; 1.046  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.093  ; 0.980  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.171  ; 1.039  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.186  ; 1.054  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.108  ; 0.995  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 1.157  ; 1.025  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 1.117  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 1.104  ; 0.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 1.103  ; 0.984  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 1.117  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 2.666  ; 2.825  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 2.937  ; 3.084  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 2.666  ; 2.825  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 2.957  ; 2.963  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 3.009  ; 3.019  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 2.866  ; 3.122  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 2.816  ; 2.870  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 2.721  ; 2.864  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 2.891  ; 2.902  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 2.741  ; 2.922  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 2.721  ; 2.864  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 3.075  ; 3.123  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 2.762  ; 2.916  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 3.005  ; 3.259  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 3.119  ; 2.912  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 2.870  ; 2.926  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 2.895  ; 2.926  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 2.979  ; 3.104  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 2.870  ; 3.125  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 3.102  ; 3.167  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 3.029  ; 3.269  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 3.095  ; 3.195  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 2.810  ; 2.615  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -2.192 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -2.219 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+----------------------------------------------------------+
; Propagation Delay                                        ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 5.322 ; 5.322 ; 6.016 ; 5.989 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------+
; Minimum Propagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 4.424 ; 4.307 ; 4.995 ; 4.995 ;
+------------+-------------+-------+-------+-------+-------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 5.040 ; 5.013 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 2.249 ; 2.171 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.264 ; 2.178 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.267 ; 2.181 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.278 ; 2.192 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.278 ; 2.192 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.250 ; 2.175 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.260 ; 2.185 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.249 ; 2.174 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.249 ; 2.174 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.257 ; 2.171 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.257 ; 2.171 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.278 ; 2.192 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.278 ; 2.192 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.271 ; 2.185 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.271 ; 2.185 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.285 ; 2.199 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.285 ; 2.199 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                     ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 4.055 ; 4.055 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 0.933 ; 0.876 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 0.941 ; 0.884 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 0.944 ; 0.887 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 0.955 ; 0.898 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 0.955 ; 0.898 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 0.953 ; 0.899 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 0.963 ; 0.909 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 0.952 ; 0.898 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 0.952 ; 0.898 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 0.933 ; 0.876 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 0.933 ; 0.876 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 0.954 ; 0.897 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 0.954 ; 0.897 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 0.947 ; 0.890 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 0.947 ; 0.890 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 0.962 ; 0.905 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 0.962 ; 0.905 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 5.180     ; 5.180     ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 2.225     ; 2.281     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.237     ; 2.296     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.240     ; 2.299     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.251     ; 2.310     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.251     ; 2.310     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.226     ; 2.282     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.236     ; 2.292     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.225     ; 2.281     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.225     ; 2.281     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.230     ; 2.289     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.230     ; 2.289     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.251     ; 2.310     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.251     ; 2.310     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.244     ; 2.303     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.244     ; 2.303     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.258     ; 2.317     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.258     ; 2.317     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 4.190     ; 4.307     ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 0.907     ; 1.081     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 0.915     ; 1.089     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 0.918     ; 1.092     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 0.929     ; 1.103     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 0.929     ; 1.103     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 0.930     ; 1.116     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 0.940     ; 1.126     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 0.929     ; 1.115     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 0.929     ; 1.115     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 0.907     ; 1.081     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 0.907     ; 1.081     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 0.928     ; 1.102     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 0.928     ; 1.102     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 0.921     ; 1.095     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 0.921     ; 1.095     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 0.936     ; 1.110     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 0.936     ; 1.110     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                ;
+------------------------------------------------------------------------+--------+-------+----------+---------+---------------------+
; Clock                                                                  ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------------------------------------------------------------+--------+-------+----------+---------+---------------------+
; Worst-case Slack                                                       ; -1.593 ; 0.135 ; 3.696    ; 0.687   ; 4.094               ;
;  SPI_SCK                                                               ; 13.455 ; 0.153 ; N/A      ; N/A     ; 20.000              ;
;  clk_27                                                                ; 34.116 ; 0.186 ; N/A      ; N/A     ; 17.784              ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.945  ; 0.187 ; 3.696    ; 1.630   ; 4.094               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.382  ; 0.135 ; 8.990    ; 0.687   ; 8.375               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.593 ; 1.850 ; N/A      ; N/A     ; 4.167               ;
;  pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A    ; N/A   ; N/A      ; N/A     ; 16.275              ;
;  reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 36.573 ; 0.160 ; N/A      ; N/A     ; 40.596              ;
; Design-wide TNS                                                        ; -1.593 ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
;  SPI_SCK                                                               ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  clk_27                                                                ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000  ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000  ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.593 ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A    ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
+------------------------------------------------------------------------+--------+-------+----------+---------+---------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; 5.835 ; 6.478 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 7.815 ; 8.168 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; 0.706 ; 1.115 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; 2.062 ; 2.385 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 3.027 ; 3.140 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 3.021 ; 3.134 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 3.013 ; 3.126 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 3.027 ; 3.140 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 3.027 ; 3.140 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.964 ; 3.081 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.974 ; 3.091 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.964 ; 3.081 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.965 ; 3.082 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 3.008 ; 3.121 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 3.008 ; 3.121 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.998 ; 3.111 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.998 ; 3.111 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 3.011 ; 3.124 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 3.011 ; 3.124 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 3.012 ; 3.125 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 3.012 ; 3.125 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                        ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; -1.563 ; -2.324 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 0.560  ; 0.370  ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; -0.174 ; -0.666 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; -0.288 ; -0.710 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; -0.968 ; -1.526 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; -0.988 ; -1.540 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; -0.985 ; -1.537 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; -0.994 ; -1.546 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; -0.994 ; -1.546 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; -0.968 ; -1.526 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; -0.978 ; -1.536 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; -0.969 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; -0.969 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; -0.975 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; -0.975 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; -0.974 ; -1.526 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; -0.974 ; -1.526 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; -0.981 ; -1.533 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; -0.981 ; -1.533 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; -0.987 ; -1.539 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; -0.987 ; -1.539 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                             ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 9.763  ; 9.220  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 3.319  ; 3.129  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 3.163  ; 2.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 3.164  ; 2.971  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 3.165  ; 2.972  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 3.175  ; 2.982  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 3.162  ; 2.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 3.319  ; 3.129  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 3.302  ; 3.112  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 3.307  ; 3.117  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 3.307  ; 3.117  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 3.303  ; 3.113  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 3.164  ; 2.971  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 3.310  ; 3.120  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 3.162  ; 2.969  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 3.162  ; 2.969  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 3.154  ; 2.961  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 2.450  ; 2.326  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 3.318  ; 3.128  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 3.291  ; 3.101  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 3.299  ; 3.109  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 3.147  ; 2.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 3.147  ; 2.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 3.176  ; 2.983  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 3.186  ; 2.993  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 3.176  ; 2.983  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 3.176  ; 2.983  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 3.284  ; 3.094  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 3.284  ; 3.094  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 3.311  ; 3.121  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 3.311  ; 3.121  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 3.142  ; 2.965  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 3.301  ; 3.111  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 3.318  ; 3.128  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 3.159  ; 2.982  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 3.284  ; 3.094  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 3.175  ; 2.982  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 3.163  ; 2.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 3.162  ; 2.969  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 3.175  ; 2.982  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 24.639 ; 24.303 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 24.333 ; 24.023 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 24.105 ; 23.925 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 24.639 ; 24.303 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 23.978 ; 23.732 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 23.847 ; 23.404 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 23.206 ; 22.830 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 22.855 ; 22.541 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 22.449 ; 22.056 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 22.356 ; 21.977 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 22.855 ; 22.541 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 22.402 ; 22.019 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 21.487 ; 21.098 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 19.326 ; 18.780 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 7.411  ; 6.731  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 25.451 ; 25.112 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 24.945 ; 24.642 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 25.451 ; 25.112 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 25.052 ; 24.713 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 25.003 ; 24.607 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 24.917 ; 24.530 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 25.003 ; 24.635 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 6.969  ; 6.115  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -0.884 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -1.122 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                     ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 5.492  ; 5.342  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 1.105  ; 0.986  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 1.105  ; 0.986  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 1.106  ; 0.987  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 1.106  ; 0.987  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 1.117  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 1.108  ; 0.995  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 1.184  ; 1.052  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 1.169  ; 1.037  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 1.173  ; 1.041  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 1.173  ; 1.041  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 1.172  ; 1.040  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 1.105  ; 0.986  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 1.179  ; 1.047  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 1.095  ; 0.976  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 1.104  ; 0.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 1.095  ; 0.976  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 0.651  ; 0.644  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 1.093  ; 0.980  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.165  ; 1.033  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.168  ; 1.036  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.101  ; 0.988  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.101  ; 0.988  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.118  ; 0.999  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.128  ; 1.009  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.117  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.117  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.157  ; 1.025  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.157  ; 1.025  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.178  ; 1.046  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.178  ; 1.046  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.093  ; 0.980  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.171  ; 1.039  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.186  ; 1.054  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.108  ; 0.995  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 1.157  ; 1.025  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 1.117  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 1.104  ; 0.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 1.103  ; 0.984  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 1.117  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 2.666  ; 2.825  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 2.937  ; 3.084  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 2.666  ; 2.825  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 2.957  ; 2.963  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 3.009  ; 3.019  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 2.866  ; 3.122  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 2.816  ; 2.870  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 2.721  ; 2.864  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 2.891  ; 2.902  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 2.741  ; 2.922  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 2.721  ; 2.864  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 3.075  ; 3.123  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 2.762  ; 2.916  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 3.005  ; 3.259  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 3.119  ; 2.912  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 2.870  ; 2.926  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 2.895  ; 2.926  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 2.979  ; 3.104  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 2.870  ; 3.125  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 3.102  ; 3.167  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 3.029  ; 3.269  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 3.095  ; 3.195  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 2.810  ; 2.615  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -2.192 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -2.219 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+----------------------------------------------------------+
; Progagation Delay                                        ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 9.445 ; 9.205 ; 9.854 ; 9.854 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------+
; Minimum Progagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 4.424 ; 4.307 ; 4.995 ; 4.995 ;
+------------+-------------+-------+-------+-------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin          ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; VGA_VS       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_HS       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_L      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_R      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[0]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[1]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nCS    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nRAS   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nCAS   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nWE    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQMH   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQML   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CLK    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CKE    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[0]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[1]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[2]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[3]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[4]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[5]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[6]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[7]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[8]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[9]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[10]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[11]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[12]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; UART_TX      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SPI_DO       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+------------------------------------------------------------------+
; Input Transition Times                                           ;
+---------------+--------------+-----------------+-----------------+
; Pin           ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+---------------+--------------+-----------------+-----------------+
; CLOCK_27[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; UART_RX       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SS4       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[2]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[3]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[4]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[5]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[6]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[7]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[8]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[9]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[10]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[11]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[12]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[13]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[14]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[15]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_DO        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SCK       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CONF_DATA0    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_DI        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SS3       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CLOCK_27[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SS2       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+---------------+--------------+-----------------+-----------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; VGA_HS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_B[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_B[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_B[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_B[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_B[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_G[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; VGA_G[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_G[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_G[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_G[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_G[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_R[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_R[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_R[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_R[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_R[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_R[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; AUDIO_L      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.08 V              ; -0.00545 V          ; 0.234 V                              ; 0.291 V                              ; 5.77e-09 s                  ; 4.44e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.01e-07 V                  ; 3.08 V             ; -0.00545 V         ; 0.234 V                             ; 0.291 V                             ; 5.77e-09 s                 ; 4.44e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_BA[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_nCS    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_nRAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_nCAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_nWE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQMH   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQML   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_CLK    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_CKE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[0]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[1]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[2]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[3]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[4]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[5]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_A[6]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_A[7]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_A[8]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_A[9]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_A[10]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[11]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_A[12]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; LED          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.08 V              ; -0.00545 V          ; 0.234 V                              ; 0.291 V                              ; 5.77e-09 s                  ; 4.44e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.01e-07 V                  ; 3.08 V             ; -0.00545 V         ; 0.234 V                             ; 0.291 V                             ; 5.77e-09 s                 ; 4.44e-09 s                 ; Yes                       ; Yes                       ;
; UART_TX      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; SPI_DO       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.08 V              ; -0.00545 V          ; 0.234 V                              ; 0.291 V                              ; 5.77e-09 s                  ; 4.44e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.01e-07 V                  ; 3.08 V             ; -0.00545 V         ; 0.234 V                             ; 0.291 V                             ; 5.77e-09 s                 ; 4.44e-09 s                 ; Yes                       ; Yes                       ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; VGA_HS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; VGA_B[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_B[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_B[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_B[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_B[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_B[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_G[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; VGA_G[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_G[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_G[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_G[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_G[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_R[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_R[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_R[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_R[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_R[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_R[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; AUDIO_L      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; AUDIO_R      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.48 V              ; -0.0164 V           ; 0.353 V                              ; 0.315 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.48 V             ; -0.0164 V          ; 0.353 V                             ; 0.315 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; SDRAM_BA[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_BA[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_nCS    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_nRAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_nCAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_nWE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_DQMH   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQML   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_CLK    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_CKE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; SDRAM_A[0]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_A[1]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_A[2]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_A[3]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_A[4]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; SDRAM_A[5]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_A[6]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_A[7]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_A[8]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_A[9]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_A[10]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_A[11]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_A[12]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; LED          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.48 V              ; -0.0164 V           ; 0.353 V                              ; 0.315 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.48 V             ; -0.0164 V          ; 0.353 V                             ; 0.315 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; UART_TX      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; SPI_DO       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.48 V              ; -0.0164 V           ; 0.353 V                              ; 0.315 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.48 V             ; -0.0164 V          ; 0.353 V                             ; 0.315 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                             ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+----------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths   ; FR Paths ; RF Paths ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+----------+----------+
; clk_27                                                                ; clk_27                                                                ; 85         ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2566       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 120        ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 16         ; 0        ; 0        ; 0        ;
; clk_27                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 36         ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 237548529  ; 20       ; 1        ; 817      ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0        ; 0        ; 0        ;
; SPI_SCK                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 52         ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0          ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; false path ; 0        ; 0        ; 0        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 1489       ; 4        ; 20       ; 1        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; SPI_SCK                                                               ; false path ; 0        ; 0        ; 0        ;
; SPI_SCK                                                               ; SPI_SCK                                                               ; 8003       ; 6        ; 147      ; 57       ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                              ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+----------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths   ; FR Paths ; RF Paths ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+----------+----------+
; clk_27                                                                ; clk_27                                                                ; 85         ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2566       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 120        ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 16         ; 0        ; 0        ; 0        ;
; clk_27                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 36         ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 237548529  ; 20       ; 1        ; 817      ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0        ; 0        ; 0        ;
; SPI_SCK                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 52         ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0          ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; false path ; 0        ; 0        ; 0        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 1489       ; 4        ; 20       ; 1        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; SPI_SCK                                                               ; false path ; 0        ; 0        ; 0        ;
; SPI_SCK                                                               ; SPI_SCK                                                               ; 8003       ; 6        ; 147      ; 57       ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                                            ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+------------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths   ; FR Paths ; RF Paths   ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+------------+----------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; clk_27                                                                ; false path ; 0        ; 0          ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 141        ; 0        ; 0          ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 13793      ; 0        ; 0          ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; SPI_SCK                                                               ; 0          ; 0        ; false path ; 0        ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                                             ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+------------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths   ; FR Paths ; RF Paths   ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+------------+----------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; clk_27                                                                ; false path ; 0        ; 0          ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 141        ; 0        ; 0          ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 13793      ; 0        ; 0          ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; SPI_SCK                                                               ; 0          ; 0        ; false path ; 0        ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 4     ; 4    ;
; Unconstrained Input Port Paths  ; 186   ; 186  ;
; Unconstrained Output Ports      ; 2     ; 2    ;
; Unconstrained Output Port Paths ; 5     ; 5    ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Sun Feb  7 09:46:35 2021
Info: Command: quartus_sta atari800core -c atari800core
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 12 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 6 of the 6 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'atari800core.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 27 -multiply_by 100 -duty_cycle 50.00 -name {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]} {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 27 -multiply_by 50 -duty_cycle 50.00 -name {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]} {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 27 -multiply_by 100 -phase -100.00 -duty_cycle 50.00 -name {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]} {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 200 -multiply_by 227 -duty_cycle 50.00 -name {pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]} {pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 9 -multiply_by 4 -duty_cycle 50.00 -name {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]} {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332125): Found combinational loop of 4 nodes
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[0]~7|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[0]~6|datab"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[0]~6|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[0]~7|dataa"
Warning (332125): Found combinational loop of 4 nodes
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[0]~7|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[0]~6|dataa"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[0]~6|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[0]~7|dataa"
Warning (332125): Found combinational loop of 4 nodes
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[1]~10|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[1]~8|datad"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[1]~8|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[1]~10|dataa"
Warning (332125): Found combinational loop of 4 nodes
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[1]~9|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[1]~8|datab"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[1]~8|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[1]~9|datab"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -1.593
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.593        -1.593 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     0.382         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.945         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    13.455         0.000 SPI_SCK 
    Info (332119):    34.116         0.000 clk_27 
    Info (332119):    36.573         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case hold slack is 0.398
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.398         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.448         0.000 SPI_SCK 
    Info (332119):     0.454         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.454         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.455         0.000 clk_27 
    Info (332119):     2.208         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is 3.696
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     3.696         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     8.990         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case removal slack is 1.607
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     1.607         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     3.627         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 4.094
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.094         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.194         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.375         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    16.275         0.000 pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    18.275         0.000 clk_27 
    Info (332119):    20.415         0.000 SPI_SCK 
    Info (332119):    40.596         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -1.296
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.296        -1.296 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     0.979         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.551         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    13.962         0.000 SPI_SCK 
    Info (332119):    34.379         0.000 clk_27 
    Info (332119):    36.824         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case hold slack is 0.383
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.383         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.402         0.000 SPI_SCK 
    Info (332119):     0.402         0.000 clk_27 
    Info (332119):     0.402         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.402         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     2.111         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is 4.091
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.091         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     9.705         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case removal slack is 1.457
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     1.457         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     3.257         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 4.097
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.097         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.167         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.403         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    16.280         0.000 pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    18.271         0.000 clk_27 
    Info (332119):    20.400         0.000 SPI_SCK 
    Info (332119):    40.596         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 0.323
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.323         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     2.393         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     7.016         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    18.226         0.000 SPI_SCK 
    Info (332119):    35.770         0.000 clk_27 
    Info (332119):    39.814         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case hold slack is 0.135
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.135         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.153         0.000 SPI_SCK 
    Info (332119):     0.160         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.186         0.000 clk_27 
    Info (332119):     0.187         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.850         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is 6.422
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     6.422         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    13.615         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case removal slack is 0.687
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.687         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     1.630         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 4.186
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.186         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.331         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.559         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    16.300         0.000 pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.784         0.000 clk_27 
    Info (332119):    20.000         0.000 SPI_SCK 
    Info (332119):    40.631         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 22 warnings
    Info: Peak virtual memory: 571 megabytes
    Info: Processing ended: Sun Feb  7 09:46:44 2021
    Info: Elapsed time: 00:00:09
    Info: Total CPU time (on all processors): 00:00:11


