TimeQuest Timing Analyzer report for atari800core
Sat Feb  6 21:48:11 2021
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 14. Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
 15. Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 16. Slow 1200mV 85C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 17. Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 18. Slow 1200mV 85C Model Setup: 'SPI_SCK'
 19. Slow 1200mV 85C Model Setup: 'CLOCK_27[0]'
 20. Slow 1200mV 85C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 21. Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 22. Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 23. Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
 24. Slow 1200mV 85C Model Hold: 'CLOCK_27[0]'
 25. Slow 1200mV 85C Model Hold: 'SPI_SCK'
 26. Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 27. Slow 1200mV 85C Model Recovery: 'CLOCK_27[0]'
 28. Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 29. Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 30. Slow 1200mV 85C Model Recovery: 'SPI_SCK'
 31. Slow 1200mV 85C Model Removal: 'CLOCK_27[0]'
 32. Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 33. Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 34. Slow 1200mV 85C Model Removal: 'SPI_SCK'
 35. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 36. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 37. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 38. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
 39. Slow 1200mV 85C Model Minimum Pulse Width: 'SPI_SCK'
 40. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_27[0]'
 41. Slow 1200mV 85C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 42. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
 43. Setup Times
 44. Hold Times
 45. Clock to Output Times
 46. Minimum Clock to Output Times
 47. Propagation Delay
 48. Minimum Propagation Delay
 49. Output Enable Times
 50. Minimum Output Enable Times
 51. Output Disable Times
 52. Minimum Output Disable Times
 53. Slow 1200mV 85C Model Metastability Report
 54. Slow 1200mV 0C Model Fmax Summary
 55. Slow 1200mV 0C Model Setup Summary
 56. Slow 1200mV 0C Model Hold Summary
 57. Slow 1200mV 0C Model Recovery Summary
 58. Slow 1200mV 0C Model Removal Summary
 59. Slow 1200mV 0C Model Minimum Pulse Width Summary
 60. Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 61. Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
 62. Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 63. Slow 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 64. Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 65. Slow 1200mV 0C Model Setup: 'SPI_SCK'
 66. Slow 1200mV 0C Model Setup: 'CLOCK_27[0]'
 67. Slow 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 68. Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 69. Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 70. Slow 1200mV 0C Model Hold: 'CLOCK_27[0]'
 71. Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
 72. Slow 1200mV 0C Model Hold: 'SPI_SCK'
 73. Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 74. Slow 1200mV 0C Model Recovery: 'CLOCK_27[0]'
 75. Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 76. Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 77. Slow 1200mV 0C Model Recovery: 'SPI_SCK'
 78. Slow 1200mV 0C Model Removal: 'CLOCK_27[0]'
 79. Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 80. Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 81. Slow 1200mV 0C Model Removal: 'SPI_SCK'
 82. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 83. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 84. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 85. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
 86. Slow 1200mV 0C Model Minimum Pulse Width: 'SPI_SCK'
 87. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_27[0]'
 88. Slow 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 89. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
 90. Setup Times
 91. Hold Times
 92. Clock to Output Times
 93. Minimum Clock to Output Times
 94. Propagation Delay
 95. Minimum Propagation Delay
 96. Output Enable Times
 97. Minimum Output Enable Times
 98. Output Disable Times
 99. Minimum Output Disable Times
100. Slow 1200mV 0C Model Metastability Report
101. Fast 1200mV 0C Model Setup Summary
102. Fast 1200mV 0C Model Hold Summary
103. Fast 1200mV 0C Model Recovery Summary
104. Fast 1200mV 0C Model Removal Summary
105. Fast 1200mV 0C Model Minimum Pulse Width Summary
106. Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
107. Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
108. Fast 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
109. Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
110. Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
111. Fast 1200mV 0C Model Setup: 'SPI_SCK'
112. Fast 1200mV 0C Model Setup: 'CLOCK_27[0]'
113. Fast 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
114. Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
115. Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
116. Fast 1200mV 0C Model Hold: 'CLOCK_27[0]'
117. Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
118. Fast 1200mV 0C Model Hold: 'SPI_SCK'
119. Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
120. Fast 1200mV 0C Model Recovery: 'CLOCK_27[0]'
121. Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
122. Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
123. Fast 1200mV 0C Model Recovery: 'SPI_SCK'
124. Fast 1200mV 0C Model Removal: 'CLOCK_27[0]'
125. Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
126. Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
127. Fast 1200mV 0C Model Removal: 'SPI_SCK'
128. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
129. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
130. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
131. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
132. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_27[0]'
133. Fast 1200mV 0C Model Minimum Pulse Width: 'SPI_SCK'
134. Fast 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
135. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
136. Setup Times
137. Hold Times
138. Clock to Output Times
139. Minimum Clock to Output Times
140. Propagation Delay
141. Minimum Propagation Delay
142. Output Enable Times
143. Minimum Output Enable Times
144. Output Disable Times
145. Minimum Output Disable Times
146. Fast 1200mV 0C Model Metastability Report
147. Multicorner Timing Analysis Summary
148. Setup Times
149. Hold Times
150. Clock to Output Times
151. Minimum Clock to Output Times
152. Progagation Delay
153. Minimum Progagation Delay
154. Board Trace Model Assignments
155. Input Transition Times
156. Slow Corner Signal Integrity Metrics
157. Fast Corner Signal Integrity Metrics
158. Setup Transfers
159. Hold Transfers
160. Recovery Transfers
161. Removal Transfers
162. Report TCCS
163. Report RSKM
164. Unconstrained Paths
165. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; atari800core                                                      ;
; Device Family      ; Cyclone III                                                       ;
; Device Name        ; EP3C25E144C8                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Combined                                                          ;
; Rise/Fall Delays   ; Enabled                                                           ;
+--------------------+-------------------------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 12          ;
; Maximum allowed            ; 6           ;
;                            ;             ;
; Average used               ; 1.11        ;
; Maximum used               ; 6           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;  11.1%      ;
;     Processors 3-6         ; < 0.1%      ;
;     Processors 7-12        ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------+
; SDC File List                                        ;
+------------------+--------+--------------------------+
; SDC File Path    ; Status ; Read at                  ;
+------------------+--------+--------------------------+
; atari800core.sdc ; OK     ; Sat Feb  6 21:48:02 2021 ;
+------------------+--------+--------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-----------------------------------------------------------------------+-----------+-----------+------------+--------+-----------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------------------------------------------------------------------+-------------------------------------------------------------------------+---------------------------------------------------------------------------+
; Clock Name                                                            ; Type      ; Period    ; Frequency  ; Rise   ; Fall      ; Duty Cycle ; Divide by ; Multiply by ; Phase  ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                                               ; Source                                                                  ; Targets                                                                   ;
+-----------------------------------------------------------------------+-----------+-----------+------------+--------+-----------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------------------------------------------------------------------+-------------------------------------------------------------------------+---------------------------------------------------------------------------+
; CLOCK_27[0]                                                           ; Base      ; 37.037    ; 27.0 MHz   ; 0.000  ; 18.518    ;            ;           ;             ;        ;        ;           ;            ;          ;                                                                      ;                                                                         ; { CLOCK_27[0] }                                                           ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 8.810     ; 113.51 MHz ; 0.000  ; 4.405     ; 50.00      ; 27        ; 100         ;        ;        ;           ;            ; false    ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] } ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 17.621    ; 56.75 MHz  ; 0.000  ; 8.810     ; 50.00      ; 27        ; 50          ;        ;        ;           ;            ; false    ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] } ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 8.810     ; 113.51 MHz ; -2.447 ; 1.958     ; 50.00      ; 27        ; 100         ; -100.0 ;        ;           ;            ; false    ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] } ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Generated ; 88105.638 ; 0.01 MHz   ; -2.447 ; 44050.372 ; 50.00      ; 2700      ; 1           ; -0.0   ;        ;           ;            ; false    ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] } ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; Generated ; 32.631    ; 30.65 MHz  ; 0.000  ; 16.315    ; 50.00      ; 200       ; 227         ;        ;        ;           ;            ; false    ; CLOCK_27[0]                                                          ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]  ; { pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] }  ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; Generated ; 83.333    ; 12.0 MHz   ; 0.000  ; 41.666    ; 50.00      ; 9         ; 4           ;        ;        ;           ;            ; false    ; CLOCK_27[0]                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]              ; { reconfig_pll|altpll_component|auto_generated|pll1|clk[0] }              ;
; SPI_SCK                                                               ; Base      ; 41.666    ; 24.0 MHz   ; 20.800 ; 41.666    ;            ;           ;             ;        ;        ;           ;            ;          ;                                                                      ;                                                                         ; { SPI_SCK }                                                               ;
+-----------------------------------------------------------------------+-----------+-----------+------------+--------+-----------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------------------------------------------------------------------+-------------------------------------------------------------------------+---------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                          ;
+------------+-----------------+-----------------------------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                                            ; Note ;
+------------+-----------------+-----------------------------------------------------------------------+------+
; 39.72 MHz  ; 39.72 MHz       ; SPI_SCK                                                               ;      ;
; 61.82 MHz  ; 61.82 MHz       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;      ;
; 70.65 MHz  ; 70.65 MHz       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ;      ;
; 144.63 MHz ; 144.63 MHz      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;      ;
; 235.29 MHz ; 235.29 MHz      ; CLOCK_27[0]                                                           ;      ;
; 254.19 MHz ; 254.19 MHz      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ;      ;
+------------+-----------------+-----------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+-------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                             ;
+-----------------------------------------------------------------------+---------+---------------+
; Clock                                                                 ; Slack   ; End Point TNS ;
+-----------------------------------------------------------------------+---------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -24.931 ; -3419.723     ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; -16.485 ; -194.448      ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.530  ; -1.530        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; -0.339  ; -0.339        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.906   ; 0.000         ;
; SPI_SCK                                                               ; 8.258   ; 0.000         ;
; CLOCK_27[0]                                                           ; 32.787  ; 0.000         ;
+-----------------------------------------------------------------------+---------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                             ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; -1.331 ; -1.331        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.344  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.453  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.454  ; 0.000         ;
; CLOCK_27[0]                                                           ; 0.455  ; 0.000         ;
; SPI_SCK                                                               ; 0.741  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 9.616  ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                         ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; CLOCK_27[0]                                                           ; -0.800 ; -7.200        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.117  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.003 ; 0.000         ;
; SPI_SCK                                                               ; 14.514 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                          ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; CLOCK_27[0]                                                           ; -0.817 ; -7.353        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.593  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 3.268  ; 0.000         ;
; SPI_SCK                                                               ; 18.903 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                                 ;
+-----------------------------------------------------------------------+-----------+---------------+
; Clock                                                                 ; Slack     ; End Point TNS ;
+-----------------------------------------------------------------------+-----------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.093     ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 4.225     ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.372     ; 0.000         ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 16.276    ; 0.000         ;
; SPI_SCK                                                               ; 16.636    ; 0.000         ;
; CLOCK_27[0]                                                           ; 18.277    ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 40.596    ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 44052.505 ; 0.000         ;
+-----------------------------------------------------------------------+-----------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                 ;
+---------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                        ; To Node                                                                                                                 ; Launch Clock ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -24.931 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.456    ; 11.397     ;
; -24.894 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 11.365     ;
; -24.834 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 11.301     ;
; -24.793 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.456    ; 11.259     ;
; -24.765 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.456    ; 11.231     ;
; -24.728 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 11.199     ;
; -24.668 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 11.135     ;
; -24.649 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.456    ; 11.115     ;
; -24.640 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.985    ; 11.577     ;
; -24.627 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.456    ; 11.093     ;
; -24.625 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.457    ; 11.090     ;
; -24.612 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 11.083     ;
; -24.600 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 11.067     ;
; -24.587 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.456    ; 11.053     ;
; -24.552 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 11.019     ;
; -24.550 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 11.021     ;
; -24.517 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.456    ; 10.983     ;
; -24.511 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.456    ; 10.977     ;
; -24.499 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.456    ; 10.965     ;
; -24.490 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 10.957     ;
; -24.480 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.951     ;
; -24.474 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.985    ; 11.411     ;
; -24.462 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.933     ;
; -24.459 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.457    ; 10.924     ;
; -24.449 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 10.916     ;
; -24.449 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.456    ; 10.915     ;
; -24.447 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.918     ;
; -24.445 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.456    ; 10.911     ;
; -24.434 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 10.901     ;
; -24.420 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 10.887     ;
; -24.408 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.879     ;
; -24.402 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 10.869     ;
; -24.379 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.456    ; 10.845     ;
; -24.361 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.456    ; 10.827     ;
; -24.358 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.985    ; 11.295     ;
; -24.348 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 10.815     ;
; -24.343 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.457    ; 10.808     ;
; -24.336 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[21]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.807     ;
; -24.332 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[22]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.803     ;
; -24.318 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 10.785     ;
; -24.307 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.456    ; 10.773     ;
; -24.296 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.985    ; 11.233     ;
; -24.283 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 10.750     ;
; -24.281 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.457    ; 10.746     ;
; -24.281 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.752     ;
; -24.256 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 10.723     ;
; -24.226 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.985    ; 11.163     ;
; -24.211 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.457    ; 10.676     ;
; -24.208 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.985    ; 11.145     ;
; -24.199 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[20]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 10.666     ;
; -24.193 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.457    ; 10.658     ;
; -24.186 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 10.653     ;
; -24.170 ; user_io:my_user_io|joystick_1[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.984    ; 11.108     ;
; -24.170 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[21]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.641     ;
; -24.168 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 10.635     ;
; -24.167 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 10.634     ;
; -24.166 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[22]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.637     ;
; -24.165 ; user_io:my_user_io|joystick_1[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.984    ; 11.103     ;
; -24.165 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.636     ;
; -24.154 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.985    ; 11.091     ;
; -24.139 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.457    ; 10.604     ;
; -24.130 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[13]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.450    ; 10.602     ;
; -24.122 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[17]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.429    ; 10.615     ;
; -24.114 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 10.581     ;
; -24.105 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 10.572     ;
; -24.103 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.574     ;
; -24.059 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[18]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.457    ; 10.524     ;
; -24.054 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[21]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.525     ;
; -24.050 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[22]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.521     ;
; -24.035 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 10.502     ;
; -24.033 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[20]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 10.500     ;
; -24.033 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.504     ;
; -24.017 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 10.484     ;
; -24.015 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.486     ;
; -24.004 ; user_io:my_user_io|joystick_1[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.984    ; 10.942     ;
; -23.999 ; user_io:my_user_io|joystick_1[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.984    ; 10.937     ;
; -23.992 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[21]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.463     ;
; -23.988 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[22]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.459     ;
; -23.985 ; user_io:my_user_io|joystick_1[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.971    ; 10.936     ;
; -23.971 ; user_io:my_user_io|joystick_1[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.971    ; 10.922     ;
; -23.968 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[15]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.427    ; 10.463     ;
; -23.964 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[13]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.450    ; 10.436     ;
; -23.963 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 10.430     ;
; -23.961 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.432     ;
; -23.956 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[17]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.429    ; 10.449     ;
; -23.941 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[16]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.450    ; 10.413     ;
; -23.928 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[19]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.399     ;
; -23.922 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[21]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.393     ;
; -23.918 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[22]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.389     ;
; -23.917 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[20]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 10.384     ;
; -23.904 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[21]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.375     ;
; -23.900 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[22]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.371     ;
; -23.893 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[18]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.457    ; 10.358     ;
; -23.880 ; user_io:my_user_io|joystick_1[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.984    ; 10.818     ;
; -23.875 ; user_io:my_user_io|joystick_1[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.984    ; 10.813     ;
; -23.855 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[20]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.455    ; 10.322     ;
; -23.850 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[21]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.321     ;
; -23.848 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[13]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.450    ; 10.320     ;
; -23.846 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[22]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -13.451    ; 10.317     ;
; -23.845 ; user_io:my_user_io|joystick_1[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.968    ; 10.799     ;
+---------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                          ;
+---------+--------------------------------+------------------------------------+--------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                      ; To Node                            ; Launch Clock ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+---------+--------------------------------+------------------------------------+--------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -16.485 ; user_io:my_user_io|ps2_fifo~54 ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.459    ; 2.948      ;
; -16.394 ; user_io:my_user_io|ps2_fifo~55 ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.459    ; 2.857      ;
; -16.352 ; user_io:my_user_io|ps2_fifo~53 ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.459    ; 2.815      ;
; -16.350 ; user_io:my_user_io|ps2_fifo~47 ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.459    ; 2.813      ;
; -16.335 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.810      ;
; -16.335 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.810      ;
; -16.335 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.810      ;
; -16.335 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.810      ;
; -16.335 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.810      ;
; -16.335 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.810      ;
; -16.335 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.810      ;
; -16.335 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_parity      ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.810      ;
; -16.294 ; user_io:my_user_io|ps2_fifo~9  ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.445    ; 2.771      ;
; -16.283 ; user_io:my_user_io|ps2_fifo~50 ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.459    ; 2.746      ;
; -16.275 ; user_io:my_user_io|ps2_fifo~38 ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.460    ; 2.737      ;
; -16.274 ; user_io:my_user_io|ps2_fifo~45 ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.459    ; 2.737      ;
; -16.241 ; user_io:my_user_io|ps2_fifo~42 ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.459    ; 2.704      ;
; -16.240 ; user_io:my_user_io|ps2_fifo~46 ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.459    ; 2.703      ;
; -16.237 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.712      ;
; -16.223 ; user_io:my_user_io|ps2_fifo~12 ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.445    ; 2.700      ;
; -16.211 ; user_io:my_user_io|ps2_fifo~49 ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.460    ; 2.673      ;
; -16.197 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.672      ;
; -16.197 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.672      ;
; -16.197 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.672      ;
; -16.197 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.672      ;
; -16.197 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.672      ;
; -16.197 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.672      ;
; -16.197 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.672      ;
; -16.197 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_parity      ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.672      ;
; -16.186 ; user_io:my_user_io|ps2_fifo~39 ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.460    ; 2.648      ;
; -16.158 ; user_io:my_user_io|ps2_fifo~15 ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.445    ; 2.635      ;
; -16.142 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_state[0] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.446    ; 2.618      ;
; -16.113 ; user_io:my_user_io|ps2_fifo~37 ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.460    ; 2.575      ;
; -16.074 ; user_io:my_user_io|ps2_fifo~34 ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.460    ; 2.536      ;
; -16.070 ; user_io:my_user_io|ps2_fifo~23 ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.445    ; 2.547      ;
; -16.056 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.531      ;
; -16.038 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.513      ;
; -16.038 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.513      ;
; -16.038 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.513      ;
; -16.038 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.513      ;
; -16.038 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.513      ;
; -16.038 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.513      ;
; -16.038 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.513      ;
; -16.038 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_parity      ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.513      ;
; -16.037 ; user_io:my_user_io|ps2_fifo~51 ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.460    ; 2.499      ;
; -16.024 ; user_io:my_user_io|ps2_fifo~48 ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.459    ; 2.487      ;
; -15.987 ; user_io:my_user_io|ps2_fifo~33 ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.460    ; 2.449      ;
; -15.982 ; user_io:my_user_io|ps2_fifo~8  ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.445    ; 2.459      ;
; -15.981 ; user_io:my_user_io|ps2_fifo~11 ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.445    ; 2.458      ;
; -15.965 ; user_io:my_user_io|ps2_fifo~52 ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.459    ; 2.428      ;
; -15.961 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_state[0] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.446    ; 2.437      ;
; -15.957 ; user_io:my_user_io|ps2_fifo~41 ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.460    ; 2.419      ;
; -15.949 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 2.424      ;
; -15.949 ; user_io:my_user_io|ps2_fifo~7  ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.446    ; 2.425      ;
; -15.909 ; user_io:my_user_io|ps2_fifo~40 ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.459    ; 2.372      ;
; -15.901 ; user_io:my_user_io|ps2_fifo~43 ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.460    ; 2.363      ;
; -15.894 ; user_io:my_user_io|ps2_fifo~16 ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.445    ; 2.371      ;
; -15.893 ; user_io:my_user_io|ps2_fifo~19 ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.445    ; 2.370      ;
; -15.892 ; user_io:my_user_io|ps2_fifo~14 ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.445    ; 2.369      ;
; -15.889 ; user_io:my_user_io|ps2_fifo~20 ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.445    ; 2.366      ;
; -15.882 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_kbd_data    ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.446    ; 2.358      ;
; -15.878 ; user_io:my_user_io|ps2_fifo~17 ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.445    ; 2.355      ;
; -15.863 ; user_io:my_user_io|ps2_fifo~44 ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.459    ; 2.326      ;
; -15.854 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_state[0] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.446    ; 2.330      ;
; -15.822 ; user_io:my_user_io|ps2_fifo~10 ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.445    ; 2.299      ;
; -15.819 ; user_io:my_user_io|ps2_fifo~22 ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.445    ; 2.296      ;
; -15.794 ; user_io:my_user_io|ps2_fifo~13 ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.445    ; 2.271      ;
; -15.785 ; user_io:my_user_io|ps2_fifo~32 ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.460    ; 2.247      ;
; -15.780 ; user_io:my_user_io|ps2_fifo~35 ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.460    ; 2.242      ;
; -15.773 ; user_io:my_user_io|ps2_fifo~3  ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.446    ; 2.249      ;
; -15.771 ; user_io:my_user_io|ps2_fifo~63 ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.460    ; 2.233      ;
; -15.770 ; user_io:my_user_io|ps2_fifo~0  ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.446    ; 2.246      ;
; -15.755 ; user_io:my_user_io|ps2_fifo~36 ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.460    ; 2.217      ;
; -15.751 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_kbd_data    ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.446    ; 2.227      ;
; -15.748 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_kbd_data    ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.446    ; 2.224      ;
; -15.711 ; user_io:my_user_io|ps2_fifo~4  ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.446    ; 2.187      ;
; -15.707 ; user_io:my_user_io|ps2_fifo~1  ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.446    ; 2.183      ;
; -15.695 ; user_io:my_user_io|ps2_fifo~61 ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.460    ; 2.157      ;
; -15.661 ; user_io:my_user_io|ps2_fifo~58 ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.460    ; 2.123      ;
; -15.655 ; user_io:my_user_io|ps2_fifo~62 ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.460    ; 2.117      ;
; -15.652 ; user_io:my_user_io|ps2_fifo~6  ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.446    ; 2.128      ;
; -15.583 ; user_io:my_user_io|ps2_fifo~2  ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.446    ; 2.059      ;
; -15.583 ; user_io:my_user_io|ps2_fifo~5  ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.446    ; 2.059      ;
; -15.544 ; user_io:my_user_io|ps2_fifo~21 ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.445    ; 2.021      ;
; -15.542 ; user_io:my_user_io|ps2_fifo~18 ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.445    ; 2.019      ;
; -15.532 ; user_io:my_user_io|ps2_fifo~31 ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.446    ; 2.008      ;
; -15.370 ; user_io:my_user_io|ps2_fifo~56 ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.460    ; 1.832      ;
; -15.367 ; user_io:my_user_io|ps2_fifo~57 ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.460    ; 1.829      ;
; -15.365 ; user_io:my_user_io|ps2_fifo~59 ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.460    ; 1.827      ;
; -15.358 ; user_io:my_user_io|ps2_fifo~27 ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.446    ; 1.834      ;
; -15.357 ; user_io:my_user_io|ps2_fifo~24 ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.446    ; 1.833      ;
; -15.340 ; user_io:my_user_io|ps2_fifo~60 ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.460    ; 1.802      ;
; -15.296 ; user_io:my_user_io|ps2_fifo~28 ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.446    ; 1.772      ;
; -15.291 ; user_io:my_user_io|ps2_fifo~25 ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.446    ; 1.767      ;
; -15.237 ; user_io:my_user_io|ps2_fifo~30 ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.446    ; 1.713      ;
; -15.183 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_r_inc       ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 1.658      ;
; -15.026 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_r_inc       ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 1.501      ;
; -14.961 ; user_io:my_user_io|ps2_fifo~26 ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.446    ; 1.437      ;
; -14.961 ; user_io:my_user_io|ps2_fifo~29 ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.446    ; 1.437      ;
; -14.895 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_r_inc       ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -13.447    ; 1.370      ;
+---------+--------------------------------+------------------------------------+--------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                  ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -1.530 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.958        ; -2.032     ; 1.324      ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                                                     ; Launch Clock                                                          ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -0.339 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.371        ; 1.357      ; 1.908      ;
; 34.589 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.799     ; 8.670      ;
; 35.196 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|altsyncram:altsyncram4|altsyncram_cul3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.798     ; 8.064      ;
; 36.738 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.406     ; 6.914      ;
; 36.739 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.406     ; 6.913      ;
; 36.847 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.404     ; 6.807      ;
; 36.847 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.404     ; 6.807      ;
; 36.963 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.406     ; 6.689      ;
; 37.076 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.404     ; 6.578      ;
; 37.088 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.412     ; 6.558      ;
; 37.109 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.406     ; 6.543      ;
; 37.125 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                                               ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.403     ; 6.530      ;
; 37.220 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.404     ; 6.434      ;
; 37.637 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.403     ; 6.018      ;
; 37.855 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.406     ; 5.797      ;
; 37.963 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.404     ; 5.691      ;
; 38.148 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.091      ; 7.611      ;
; 38.225 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.403     ; 5.430      ;
; 38.227 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.403     ; 5.428      ;
; 38.301 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                                               ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.406     ; 5.351      ;
; 38.310 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.406     ; 5.342      ;
; 38.412 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.403     ; 5.243      ;
; 38.480 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.088      ; 7.276      ;
; 38.532 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.406     ; 5.120      ;
; 38.548 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.091      ; 7.211      ;
; 38.560 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.403     ; 5.095      ;
; 38.561 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.091      ; 7.198      ;
; 38.656 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.088      ; 7.100      ;
; 38.681 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.088      ; 7.075      ;
; 38.709 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.403     ; 4.946      ;
; 38.719 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.406     ; 4.933      ;
; 38.739 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.406     ; 4.913      ;
; 38.867 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.406     ; 4.785      ;
; 38.884 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.406     ; 4.768      ;
; 39.045 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.118      ; 6.741      ;
; 40.449 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate2_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate3_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.124     ; 1.094      ;
; 40.452 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate3_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.124     ; 1.091      ;
; 74.039 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.104     ; 9.191      ;
; 74.327 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.107     ; 8.900      ;
; 74.410 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.104     ; 8.820      ;
; 74.433 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.104     ; 8.797      ;
; 74.498 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.107     ; 8.729      ;
; 74.541 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.107     ; 8.686      ;
; 74.889 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.077     ; 8.368      ;
; 75.168 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 8.081      ;
; 75.324 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 7.934      ;
; 75.456 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 7.793      ;
; 75.550 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 7.705      ;
; 75.554 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 7.695      ;
; 75.612 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 7.643      ;
; 75.695 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 7.563      ;
; 75.718 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 7.540      ;
; 75.783 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 7.472      ;
; 75.798 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 7.451      ;
; 75.826 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 7.429      ;
; 75.838 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 7.414      ;
; 75.898 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.126     ; 7.310      ;
; 75.921 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 7.334      ;
; 75.944 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 7.311      ;
; 76.009 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 7.243      ;
; 76.052 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 7.200      ;
; 76.155 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 7.111      ;
; 76.186 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.129     ; 7.019      ;
; 76.269 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.126     ; 6.939      ;
; 76.292 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.126     ; 6.916      ;
; 76.357 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.129     ; 6.848      ;
; 76.381 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 6.882      ;
; 76.400 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.129     ; 6.805      ;
; 76.689 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.095     ; 6.550      ;
; 76.767 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 6.487      ;
; 76.857 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.098     ; 6.379      ;
; 76.892 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.098     ; 6.344      ;
; 76.977 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.095     ; 6.262      ;
; 77.007 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.126     ; 6.201      ;
; 77.052 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.098     ; 6.184      ;
; 77.065 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.095     ; 6.174      ;
; 77.084 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.098     ; 6.152      ;
; 77.120 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.098     ; 6.116      ;
; 77.145 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.098     ; 6.091      ;
; 77.243 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.098     ; 5.993      ;
; 77.280 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.098     ; 5.956      ;
; 77.295 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.126     ; 5.913      ;
; 77.308 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.095     ; 5.931      ;
; 77.312 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.098     ; 5.924      ;
; 77.325 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.098     ; 5.911      ;
; 77.393 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.126     ; 5.815      ;
; 77.487 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.098     ; 5.749      ;
; 77.495 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.101     ; 5.738      ;
; 77.553 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.098     ; 5.683      ;
; 77.637 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.126     ; 5.571      ;
; 77.655 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.101     ; 5.578      ;
; 77.687 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.101     ; 5.546      ;
; 77.880 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.101     ; 5.353      ;
; 77.928 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.101     ; 5.305      ;
; 78.040 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.101     ; 5.193      ;
; 78.072 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.101     ; 5.161      ;
; 78.112 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 5.143      ;
; 78.112 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 5.143      ;
; 78.112 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 5.143      ;
; 78.112 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 5.143      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                 ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.906 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.405        ; -2.032     ; 1.325      ;
; 1.896 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 6.633      ;
; 1.932 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 6.597      ;
; 1.957 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 6.572      ;
; 2.036 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 6.493      ;
; 2.126 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.158     ; 6.397      ;
; 2.147 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 6.428      ;
; 2.149 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.157     ; 6.375      ;
; 2.153 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.157     ; 6.371      ;
; 2.162 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.158     ; 6.361      ;
; 2.185 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.157     ; 6.339      ;
; 2.187 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.158     ; 6.336      ;
; 2.234 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 6.295      ;
; 2.257 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.157     ; 6.267      ;
; 2.266 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.158     ; 6.257      ;
; 2.275 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 6.301      ;
; 2.278 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.104     ; 6.299      ;
; 2.283 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 6.246      ;
; 2.292 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 6.284      ;
; 2.333 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 6.206      ;
; 2.352 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.164     ; 6.165      ;
; 2.376 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.150     ; 6.155      ;
; 2.406 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 6.172      ;
; 2.420 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.104     ; 6.157      ;
; 2.426 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 6.150      ;
; 2.430 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 6.146      ;
; 2.448 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 6.081      ;
; 2.452 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 6.077      ;
; 2.455 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.157     ; 6.069      ;
; 2.462 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 6.114      ;
; 2.484 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 6.045      ;
; 2.490 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.162     ; 6.029      ;
; 2.504 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.163     ; 6.014      ;
; 2.510 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.158     ; 6.013      ;
; 2.513 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.140     ; 6.028      ;
; 2.513 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.158     ; 6.010      ;
; 2.521 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.151     ; 6.009      ;
; 2.527 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 6.049      ;
; 2.531 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 6.009      ;
; 2.534 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 6.039      ;
; 2.534 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 6.042      ;
; 2.542 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|ldqm_reg                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 6.033      ;
; 2.556 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 5.973      ;
; 2.570 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 6.003      ;
; 2.577 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.076     ; 6.158      ;
; 2.586 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                    ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.076     ; 6.149      ;
; 2.595 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 5.978      ;
; 2.597 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.155     ; 5.929      ;
; 2.598 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 5.977      ;
; 2.602 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 5.973      ;
; 2.604 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                    ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.076     ; 6.131      ;
; 2.606 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.156     ; 5.919      ;
; 2.615 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 5.924      ;
; 2.634 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 5.941      ;
; 2.641 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.155     ; 5.885      ;
; 2.655 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.104     ; 5.922      ;
; 2.663 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 5.890      ;
; 2.674 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 5.899      ;
; 2.677 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.155     ; 5.849      ;
; 2.679 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.076     ; 6.056      ;
; 2.683 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|udqm_reg                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.166     ; 5.832      ;
; 2.697 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 5.879      ;
; 2.702 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.155     ; 5.824      ;
; 2.704 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 5.825      ;
; 2.706 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 5.869      ;
; 2.730 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 5.843      ;
; 2.739 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.163     ; 5.779      ;
; 2.742 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.156     ; 5.783      ;
; 2.746 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.140     ; 5.795      ;
; 2.760 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 5.780      ;
; 2.761 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 5.748      ;
; 2.765 ; sdram_statemachine:sdram_adaptor|request_sreg                               ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.698     ; 5.348      ;
; 2.766 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 5.774      ;
; 2.769 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 5.784      ;
; 2.773 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.076     ; 5.962      ;
; 2.775 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.962      ;
; 2.776 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 5.798      ;
; 2.780 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 5.794      ;
; 2.781 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.155     ; 5.745      ;
; 2.784 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                    ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.953      ;
; 2.786 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.150     ; 5.745      ;
; 2.792 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.157     ; 5.732      ;
; 2.795 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 5.779      ;
; 2.802 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                    ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.935      ;
; 2.804 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.933      ;
; 2.810 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.076     ; 5.925      ;
; 2.812 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 5.762      ;
; 2.813 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                    ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.924      ;
; 2.825 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.151     ; 5.705      ;
; 2.831 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                    ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.906      ;
; 2.835 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 5.705      ;
; 2.839 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.164     ; 5.678      ;
; 2.843 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.126     ; 5.712      ;
; 2.856 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.157     ; 5.668      ;
; 2.866 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|ba_reg[0]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.109     ; 5.706      ;
; 2.874 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 5.704      ;
; 2.877 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 5.860      ;
; 2.882 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 5.691      ;
; 2.884 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 5.690      ;
; 2.894 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.127     ; 5.660      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'SPI_SCK'                                                                                                                ;
+--------+--------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                      ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 8.258  ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.882     ; 8.727      ;
; 8.487  ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.882     ; 8.498      ;
; 8.676  ; user_io:my_user_io|cmd[1]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.892     ; 8.299      ;
; 8.881  ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.882     ; 8.104      ;
; 9.149  ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.892     ; 7.826      ;
; 9.391  ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.587      ;
; 9.391  ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.587      ;
; 9.391  ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.587      ;
; 9.391  ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.587      ;
; 9.391  ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.587      ;
; 9.432  ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.882     ; 7.553      ;
; 9.458  ; user_io:my_user_io|cmd[4]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.520      ;
; 9.458  ; user_io:my_user_io|cmd[4]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.520      ;
; 9.458  ; user_io:my_user_io|cmd[4]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.520      ;
; 9.458  ; user_io:my_user_io|cmd[4]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.520      ;
; 9.458  ; user_io:my_user_io|cmd[4]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.520      ;
; 9.501  ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.477      ;
; 9.568  ; user_io:my_user_io|cmd[4]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.410      ;
; 9.762  ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.216      ;
; 9.762  ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.216      ;
; 9.762  ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.216      ;
; 9.762  ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.216      ;
; 9.762  ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.216      ;
; 9.853  ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.125      ;
; 9.853  ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.125      ;
; 9.853  ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.125      ;
; 9.853  ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.125      ;
; 9.853  ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.125      ;
; 9.872  ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.106      ;
; 9.963  ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 7.015      ;
; 10.359 ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 6.620      ;
; 10.426 ; user_io:my_user_io|cmd[4]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 6.553      ;
; 10.453 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 6.525      ;
; 10.453 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 6.525      ;
; 10.453 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 6.525      ;
; 10.453 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 6.525      ;
; 10.453 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 6.525      ;
; 10.563 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 6.415      ;
; 10.643 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 6.335      ;
; 10.643 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 6.335      ;
; 10.643 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 6.335      ;
; 10.643 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 6.335      ;
; 10.643 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 6.335      ;
; 10.685 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.887     ; 6.295      ;
; 10.694 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.887     ; 6.286      ;
; 10.730 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 6.249      ;
; 10.753 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.889     ; 6.225      ;
; 10.821 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 6.158      ;
; 10.893 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.887     ; 6.087      ;
; 10.948 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.887     ; 6.032      ;
; 11.008 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.971      ;
; 11.023 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.956      ;
; 11.024 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.955      ;
; 11.024 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.955      ;
; 11.024 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.955      ;
; 11.024 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.955      ;
; 11.024 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.955      ;
; 11.025 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.887     ; 5.955      ;
; 11.033 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.946      ;
; 11.033 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.946      ;
; 11.033 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.946      ;
; 11.033 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.946      ;
; 11.033 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.946      ;
; 11.099 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.880      ;
; 11.108 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.871      ;
; 11.149 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.883     ; 5.835      ;
; 11.149 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.883     ; 5.835      ;
; 11.149 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.883     ; 5.835      ;
; 11.149 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.883     ; 5.835      ;
; 11.149 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.883     ; 5.835      ;
; 11.224 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.883     ; 5.760      ;
; 11.232 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.747      ;
; 11.232 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.747      ;
; 11.232 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.747      ;
; 11.232 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.747      ;
; 11.232 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.747      ;
; 11.307 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.672      ;
; 11.364 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.615      ;
; 11.364 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.615      ;
; 11.364 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.615      ;
; 11.364 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.615      ;
; 11.364 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.615      ;
; 11.439 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.540      ;
; 11.460 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.887     ; 5.520      ;
; 11.511 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.468      ;
; 11.511 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.468      ;
; 11.511 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.468      ;
; 11.511 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.468      ;
; 11.511 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.468      ;
; 11.556 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.423      ;
; 11.556 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.423      ;
; 11.556 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.423      ;
; 11.556 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.423      ;
; 11.556 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.423      ;
; 11.581 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.887     ; 5.399      ;
; 11.586 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.393      ;
; 11.631 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.888     ; 5.348      ;
; 12.443 ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.893     ; 4.531      ;
; 12.443 ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.893     ; 4.531      ;
; 12.443 ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.893     ; 4.531      ;
+--------+--------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'CLOCK_27[0]'                                                                                                                                                           ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 32.787 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 4.171      ;
; 32.891 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 4.067      ;
; 32.995 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 3.964      ;
; 33.470 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.078     ; 3.490      ;
; 33.546 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 3.412      ;
; 33.891 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 3.067      ;
; 33.891 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 3.067      ;
; 33.922 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 3.037      ;
; 33.957 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 3.002      ;
; 33.961 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.078     ; 2.999      ;
; 34.010 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.078     ; 2.950      ;
; 34.075 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.883      ;
; 34.115 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.844      ;
; 34.216 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.743      ;
; 34.225 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.733      ;
; 34.259 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.700      ;
; 34.286 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.673      ;
; 34.365 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.594      ;
; 34.390 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.569      ;
; 34.413 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.546      ;
; 34.444 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.515      ;
; 34.482 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.477      ;
; 34.523 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.078     ; 2.437      ;
; 34.553 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.078     ; 2.407      ;
; 34.588 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.371      ;
; 34.640 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.319      ;
; 34.686 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.273      ;
; 34.707 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.252      ;
; 34.831 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.128      ;
; 34.836 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.123      ;
; 34.842 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.117      ;
; 34.844 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.115      ;
; 34.848 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.111      ;
; 34.849 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.110      ;
; 34.875 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.078     ; 2.085      ;
; 34.876 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.078     ; 2.084      ;
; 34.952 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.007      ;
; 34.975 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.984      ;
; 35.006 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.953      ;
; 35.015 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.944      ;
; 35.020 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.939      ;
; 35.024 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.935      ;
; 35.031 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.928      ;
; 35.033 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.926      ;
; 35.044 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.915      ;
; 35.046 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.913      ;
; 35.066 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.893      ;
; 35.067 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.892      ;
; 35.076 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.883      ;
; 35.089 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.870      ;
; 35.092 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.867      ;
; 35.105 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.854      ;
; 35.121 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.838      ;
; 35.199 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.760      ;
; 35.204 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.755      ;
; 35.266 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.693      ;
; 35.672 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.287      ;
; 35.684 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.275      ;
; 35.724 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.235      ;
; 36.101 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 0.858      ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                   ; To Node                                                                                                                                                                                                                                             ; Launch Clock                                                          ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -1.331 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.017        ; 2.703      ; 1.771      ;
; 0.454  ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.494  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.785      ;
; 0.495  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.786      ;
; 0.496  ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.788      ;
; 0.504  ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.796      ;
; 0.510  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.801      ;
; 0.511  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|tmp_seq_ena_state                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.802      ;
; 0.511  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.802      ;
; 0.512  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.803      ;
; 0.517  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.472      ; 1.243      ;
; 0.529  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|altsyncram:altsyncram4|altsyncram_cul3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.474      ; 1.257      ;
; 0.536  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reset_state                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.827      ;
; 0.536  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.827      ;
; 0.536  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.827      ;
; 0.545  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.836      ;
; 0.556  ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.847      ;
; 0.649  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.472      ; 1.375      ;
; 0.654  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.945      ;
; 0.655  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|tmp_seq_ena_state                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.946      ;
; 0.655  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_ena_state                                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.946      ;
; 0.662  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_counter_state                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.953      ;
; 0.663  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_counter_state                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.954      ;
; 0.681  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reset_state                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.972      ;
; 0.699  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate_state                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.990      ;
; 0.702  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|tmp_seq_ena_state                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_ena_state                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.993      ;
; 0.711  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reset_state                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.002      ;
; 0.716  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_ena_state                                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.007      ;
; 0.718  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.009      ;
; 0.722  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_counter_state                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.012      ;
; 0.736  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.028      ;
; 0.736  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.028      ;
; 0.736  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.028      ;
; 0.737  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.029      ;
; 0.738  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.029      ;
; 0.738  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.029      ;
; 0.738  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.029      ;
; 0.739  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.739  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.739  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.739  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.030      ;
; 0.740  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.741  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.033      ;
; 0.741  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.741  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.741  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.741  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.742  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.033      ;
; 0.743  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.035      ;
; 0.743  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.034      ;
; 0.743  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.034      ;
; 0.746  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.037      ;
; 0.746  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.037      ;
; 0.747  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.038      ;
; 0.747  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.038      ;
; 0.747  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.038      ;
; 0.748  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.039      ;
; 0.748  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.039      ;
; 0.748  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.039      ;
; 0.748  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.039      ;
; 0.748  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.039      ;
; 0.748  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.039      ;
; 0.749  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.749  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.749  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.749  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.749  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.749  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.749  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.472      ; 1.475      ;
; 0.749  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.750  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.041      ;
; 0.750  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.041      ;
; 0.750  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.472      ; 1.476      ;
; 0.750  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.041      ;
; 0.750  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.041      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                   ; To Node                                                                                                                                                                                                                                 ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.344 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[4]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.486      ; 1.084      ;
; 0.358 ; sdram_statemachine:sdram_adaptor|data_out_reg[10]                                                                                                                                                           ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[10]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 0.795      ;
; 0.358 ; sdram_statemachine:sdram_adaptor|data_out_reg[9]                                                                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[9]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 0.795      ;
; 0.396 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]                                                                                                            ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a4~porta_datain_reg0                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.132      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.485      ; 1.141      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.484      ; 1.140      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[2]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.483      ; 1.139      ;
; 0.408 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.142      ;
; 0.410 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.485      ; 1.149      ;
; 0.411 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.485      ; 1.150      ;
; 0.413 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.483      ; 1.150      ;
; 0.416 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.150      ;
; 0.416 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[4]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.484      ; 1.154      ;
; 0.417 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[4]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.483      ; 1.154      ;
; 0.419 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.483      ; 1.156      ;
; 0.420 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[0]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.154      ;
; 0.420 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]                                                                                                            ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a4~porta_datain_reg0                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.156      ;
; 0.427 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[0]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.160      ;
; 0.431 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.483      ; 1.168      ;
; 0.431 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[4]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.483      ; 1.168      ;
; 0.432 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[7]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.483      ; 1.169      ;
; 0.432 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.485      ; 1.171      ;
; 0.433 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.484      ; 1.171      ;
; 0.433 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.485      ; 1.172      ;
; 0.433 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[7]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.165      ;
; 0.433 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.166      ;
; 0.434 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_add_sp2                                                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_add_sp2                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_resync                                                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_resync                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe3a[0]                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~portb_address_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.475      ; 1.163      ;
; 0.434 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]                                                                                                            ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a4~porta_datain_reg0                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.170      ;
; 0.434 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.435 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|altsyncram_eg81:FIFOram|ram_block1a0~porta_address_reg0        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.473      ; 1.162      ;
; 0.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|control_pressed_reg                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|control_pressed_reg                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 0.746      ;
; 0.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|break_pressed_reg                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|break_pressed_reg                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 0.746      ;
; 0.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|shift_pressed_reg                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|shift_pressed_reg                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 0.746      ;
; 0.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.483      ; 1.172      ;
; 0.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.483      ; 1.173      ;
; 0.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 0.746      ;
; 0.437 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[1] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|altsyncram_eg81:FIFOram|ram_block1a0~porta_address_reg0        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.473      ; 1.164      ;
; 0.439 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[2]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.473      ; 1.166      ;
; 0.440 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.484      ; 1.178      ;
; 0.442 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[1]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.175      ;
; 0.442 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[0]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.483      ; 1.179      ;
; 0.443 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[3] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|altsyncram_eg81:FIFOram|ram_block1a0~porta_address_reg0        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.473      ; 1.170      ;
; 0.443 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[6] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|altsyncram_eg81:FIFOram|ram_block1a0~porta_address_reg0        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.473      ; 1.170      ;
; 0.443 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.179      ;
; 0.447 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[4]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.473      ; 1.174      ;
; 0.447 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[4]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.180      ;
; 0.449 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[0]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.484      ; 1.187      ;
; 0.450 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[5]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.473      ; 1.177      ;
; 0.450 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]                                                                                                            ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a4~porta_datain_reg0                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.186      ;
; 0.452 ; scandoubler:scandoubler1|colour_reg[2]                                                                                                                                                                      ; scandoubler:scandoubler1|gtia_palette:palette4|altsyncram:Mux21_rtl_0|altsyncram_tt01:auto_generated|ram_block1a0~porta_address_reg0                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.477      ; 1.183      ;
; 0.453 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                                                         ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[119]                                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[119]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[14]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[14]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[20]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[20]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_enable                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_enable                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchTaken                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchTaken                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[0]                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[0]                                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[370]                                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[370]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[1]                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[1]                                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[9]                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[9]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[10]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[10]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_32bit_reg                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_32bit_reg                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; paddle_mode_reg                                                                                                                                                                                             ; paddle_mode_reg                                                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                                                                                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                                                                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_reg                                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_reg                                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready                                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load2                                                                                                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load2                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk                                                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_fetch                                                                                                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_fetch                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_store_sp2                                                                                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_store_sp2                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                            ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                     ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.453 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.454 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.491 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.784      ;
; 0.736 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.029      ;
; 0.739 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.032      ;
; 0.739 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.032      ;
; 0.739 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.032      ;
; 0.740 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.033      ;
; 0.741 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.034      ;
; 0.741 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.034      ;
; 0.745 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.038      ;
; 0.745 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.038      ;
; 0.745 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.038      ;
; 0.747 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.040      ;
; 0.747 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.040      ;
; 0.748 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.041      ;
; 0.750 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.043      ;
; 0.756 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.048      ;
; 0.757 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.049      ;
; 0.759 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.051      ;
; 0.760 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.052      ;
; 0.760 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.052      ;
; 0.763 ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.056      ;
; 0.765 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.058      ;
; 0.765 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.057      ;
; 0.766 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.058      ;
; 0.768 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.061      ;
; 0.769 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.062      ;
; 0.771 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.064      ;
; 0.772 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.065      ;
; 0.773 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.066      ;
; 0.780 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.072      ;
; 0.793 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.086      ;
; 0.802 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.095      ;
; 0.894 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.182      ; 1.307      ;
; 0.917 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.182      ; 1.330      ;
; 0.918 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.182      ; 1.331      ;
; 0.946 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.238      ;
; 0.952 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.245      ;
; 0.959 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.251      ;
; 0.966 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.258      ;
; 0.970 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.262      ;
; 1.091 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.384      ;
; 1.093 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.386      ;
; 1.093 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.386      ;
; 1.100 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.393      ;
; 1.100 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.393      ;
; 1.100 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.393      ;
; 1.100 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.393      ;
; 1.101 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.394      ;
; 1.101 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.394      ;
; 1.101 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.394      ;
; 1.102 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.395      ;
; 1.102 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.395      ;
; 1.109 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.402      ;
; 1.109 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.402      ;
; 1.109 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.402      ;
; 1.111 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.404      ;
; 1.111 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.403      ;
; 1.111 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.404      ;
; 1.111 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.404      ;
; 1.112 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.404      ;
; 1.117 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.409      ;
; 1.118 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.410      ;
; 1.118 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.411      ;
; 1.118 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.411      ;
; 1.119 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.411      ;
; 1.120 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.412      ;
; 1.120 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.413      ;
; 1.123 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.416      ;
; 1.124 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.417      ;
; 1.124 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.416      ;
; 1.126 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.419      ;
; 1.128 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.082      ; 1.422      ;
; 1.128 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.420      ;
; 1.129 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.421      ;
; 1.131 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.082      ; 1.425      ;
; 1.133 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.424      ;
; 1.133 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.426      ;
; 1.133 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.425      ;
; 1.134 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.427      ;
; 1.135 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.428      ;
; 1.140 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.433      ;
; 1.142 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.435      ;
; 1.143 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.436      ;
; 1.147 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.440      ;
; 1.149 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.442      ;
; 1.161 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.182      ; 1.574      ;
; 1.165 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.182      ; 1.578      ;
; 1.177 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.182      ; 1.590      ;
; 1.205 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.182      ; 1.618      ;
; 1.222 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.515      ;
; 1.224 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.517      ;
; 1.224 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.517      ;
; 1.231 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.524      ;
; 1.231 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.524      ;
; 1.232 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.525      ;
; 1.232 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.525      ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                      ;
+-------+------------------------------------+------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                          ; To Node                            ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------+------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.454 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_rptr[0]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_rptr[1]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_tx_byte[7]  ; user_io:my_user_io|ps2_tx_byte[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_parity      ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.466 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.758      ;
; 0.510 ; user_io:my_user_io|ps2_tx_byte[0]  ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.802      ;
; 0.527 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.819      ;
; 0.698 ; user_io:my_user_io|ps2_tx_byte[2]  ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.990      ;
; 0.699 ; user_io:my_user_io|ps2_tx_byte[5]  ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.991      ;
; 0.699 ; user_io:my_user_io|ps2_tx_byte[3]  ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.991      ;
; 0.699 ; user_io:my_user_io|ps2_tx_byte[1]  ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.991      ;
; 0.700 ; user_io:my_user_io|ps2_tx_byte[6]  ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.992      ;
; 0.701 ; user_io:my_user_io|ps2_tx_byte[4]  ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.993      ;
; 0.753 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.045      ;
; 0.753 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.045      ;
; 0.784 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.076      ;
; 0.791 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.083      ;
; 0.810 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.102      ;
; 0.811 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.103      ;
; 0.812 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.104      ;
; 0.813 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.105      ;
; 0.848 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.140      ;
; 0.941 ; user_io:my_user_io|ps2_tx_byte[7]  ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.233      ;
; 0.950 ; user_io:my_user_io|ps2_r_inc       ; user_io:my_user_io|ps2_rptr[1]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.242      ;
; 0.952 ; user_io:my_user_io|ps2_r_inc       ; user_io:my_user_io|ps2_rptr[0]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.244      ;
; 0.952 ; user_io:my_user_io|ps2_r_inc       ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.244      ;
; 1.078 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.370      ;
; 1.079 ; user_io:my_user_io|ps2_parity      ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.372      ;
; 1.080 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.373      ;
; 1.186 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.478      ;
; 1.256 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.548      ;
; 1.261 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_rptr[1]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.553      ;
; 1.271 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.563      ;
; 1.271 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.563      ;
; 1.272 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.564      ;
; 1.276 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.568      ;
; 1.289 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.581      ;
; 1.292 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.584      ;
; 1.417 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.709      ;
; 1.443 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.735      ;
; 1.443 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.735      ;
; 1.484 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.776      ;
; 1.550 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.842      ;
; 1.581 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.874      ;
; 1.608 ; user_io:my_user_io|ps2_kbd_data    ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.900      ;
; 1.633 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.925      ;
; 1.679 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.971      ;
; 1.711 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.003      ;
; 1.733 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.024      ;
; 1.743 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.035      ;
; 1.765 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.057      ;
; 1.785 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.077      ;
; 1.795 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.087      ;
; 1.829 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.122      ;
; 1.862 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.154      ;
; 1.873 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.164      ;
; 1.884 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.177      ;
; 1.887 ; user_io:my_user_io|ps2_tx_byte[0]  ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.180      ;
; 1.957 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.248      ;
; 1.957 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.248      ;
; 1.957 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.248      ;
; 1.957 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.248      ;
; 1.957 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.248      ;
; 1.957 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.248      ;
; 1.957 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.248      ;
; 1.971 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.263      ;
; 2.014 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.306      ;
; 2.036 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.327      ;
; 2.038 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.329      ;
; 2.043 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.335      ;
; 2.084 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.376      ;
; 2.097 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.388      ;
; 2.097 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.388      ;
; 2.097 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.388      ;
; 2.097 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.388      ;
; 2.097 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.388      ;
; 2.097 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.388      ;
; 2.097 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.388      ;
; 2.143 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.435      ;
; 2.143 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.435      ;
; 2.154 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.447      ;
; 2.162 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.454      ;
; 2.163 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.455      ;
; 2.165 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.458      ;
; 2.197 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.489      ;
; 2.202 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.494      ;
; 2.204 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.496      ;
; 2.245 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.537      ;
; 2.261 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.552      ;
; 2.261 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.552      ;
; 2.261 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.552      ;
; 2.261 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.552      ;
; 2.261 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.552      ;
; 2.261 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.552      ;
; 2.261 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.552      ;
; 2.262 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.554      ;
+-------+------------------------------------+------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'CLOCK_27[0]'                                                                                                                                                           ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.467 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 0.758      ;
; 0.748 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.039      ;
; 0.748 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.039      ;
; 0.764 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.055      ;
; 1.101 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.392      ;
; 1.106 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.397      ;
; 1.108 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.399      ;
; 1.113 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.404      ;
; 1.133 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.424      ;
; 1.147 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.438      ;
; 1.203 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.494      ;
; 1.247 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.538      ;
; 1.250 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.541      ;
; 1.252 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.543      ;
; 1.253 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.544      ;
; 1.254 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.545      ;
; 1.256 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.547      ;
; 1.262 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.553      ;
; 1.267 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.558      ;
; 1.347 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.638      ;
; 1.398 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.689      ;
; 1.411 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.702      ;
; 1.411 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.702      ;
; 1.415 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.706      ;
; 1.428 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.719      ;
; 1.430 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.721      ;
; 1.430 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.721      ;
; 1.452 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.743      ;
; 1.456 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.747      ;
; 1.463 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.754      ;
; 1.468 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.759      ;
; 1.471 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.762      ;
; 1.473 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.764      ;
; 1.509 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.800      ;
; 1.509 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.800      ;
; 1.513 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.804      ;
; 1.513 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.804      ;
; 1.525 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.816      ;
; 1.561 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.852      ;
; 1.561 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.852      ;
; 1.576 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.867      ;
; 1.576 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.867      ;
; 1.589 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.880      ;
; 1.589 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.880      ;
; 1.602 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.894      ;
; 1.605 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.897      ;
; 1.615 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.907      ;
; 1.633 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.925      ;
; 1.697 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.989      ;
; 1.734 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 2.026      ;
; 1.735 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 2.027      ;
; 2.226 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.078      ; 2.516      ;
; 2.403 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.078      ; 2.693      ;
; 2.568 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.078      ; 2.858      ;
; 2.581 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.078      ; 2.871      ;
; 2.910 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.078      ; 3.200      ;
; 2.914 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.078      ; 3.204      ;
; 2.926 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.078      ; 3.216      ;
; 3.044 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 3.335      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'SPI_SCK'                                                                                                                          ;
+-------+---------------------------------------+------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                  ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.741 ; user_io:my_user_io|sbuf[3]            ; user_io:my_user_io|joystick_analog_0[4]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.033      ;
; 0.742 ; user_io:my_user_io|sbuf[3]            ; user_io:my_user_io|sbuf[4]               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.034      ;
; 0.758 ; user_io:my_user_io|sbuf[1]            ; user_io:my_user_io|joystick_analog_0[2]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.050      ;
; 0.759 ; user_io:my_user_io|sbuf[6]            ; user_io:my_user_io|joystick_analog_0[7]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.051      ;
; 0.774 ; user_io:my_user_io|sbuf[4]            ; user_io:my_user_io|sbuf[5]               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.066      ;
; 0.943 ; user_io:my_user_io|sbuf[4]            ; user_io:my_user_io|joystick_analog_0[5]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.235      ;
; 0.944 ; user_io:my_user_io|sbuf[5]            ; user_io:my_user_io|sbuf[6]               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.236      ;
; 0.945 ; user_io:my_user_io|sbuf[5]            ; user_io:my_user_io|joystick_analog_0[6]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.237      ;
; 0.949 ; user_io:my_user_io|sbuf[2]            ; user_io:my_user_io|sbuf[3]               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.241      ;
; 0.951 ; user_io:my_user_io|sbuf[2]            ; user_io:my_user_io|joystick_analog_0[3]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.243      ;
; 0.969 ; user_io:my_user_io|sbuf[0]            ; user_io:my_user_io|sbuf[1]               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.261      ;
; 1.038 ; user_io:my_user_io|serial_out_rptr[5] ; user_io:my_user_io|serial_out_rptr[5]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.330      ;
; 1.154 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|serial_out_rptr[0]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.446      ;
; 1.155 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|byte_cnt[4]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.447      ;
; 1.155 ; user_io:my_user_io|sbuf[0]            ; user_io:my_user_io|joystick_analog_0[1]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.447      ;
; 1.165 ; user_io:my_user_io|status[0]          ; user_io:my_user_io|status[0]             ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.457      ;
; 1.178 ; user_io:my_user_io|sbuf[1]            ; user_io:my_user_io|sbuf[2]               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.470      ;
; 1.312 ; user_io:my_user_io|serial_out_rptr[3] ; user_io:my_user_io|serial_out_rptr[3]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.604      ;
; 1.340 ; user_io:my_user_io|ps2_wptr[1]        ; user_io:my_user_io|ps2_wptr[1]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.632      ;
; 1.354 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|byte_cnt[5]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.646      ;
; 1.363 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|bit_cnt[0]            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.655      ;
; 1.364 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|bit_cnt[2]            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.656      ;
; 1.416 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_wptr[0]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.708      ;
; 1.434 ; user_io:my_user_io|sbuf[6]            ; user_io:my_user_io|joystick_analog_1[7]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.726      ;
; 1.459 ; user_io:my_user_io|sbuf[0]            ; user_io:my_user_io|joystick_analog_1[9]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.084      ; 1.755      ;
; 1.462 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_wptr[1]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.754      ;
; 1.482 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|byte_cnt[7]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.774      ;
; 1.498 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|byte_cnt[4]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.790      ;
; 1.541 ; user_io:my_user_io|sbuf[6]            ; user_io:my_user_io|joystick_analog_1[15] ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.084      ; 1.837      ;
; 1.544 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|bit_cnt[2]            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.836      ;
; 1.545 ; user_io:my_user_io|serial_out_rptr[2] ; user_io:my_user_io|serial_out_rptr[2]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.837      ;
; 1.547 ; user_io:my_user_io|serial_out_rptr[4] ; user_io:my_user_io|serial_out_rptr[4]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.839      ;
; 1.557 ; user_io:my_user_io|sbuf[5]            ; user_io:my_user_io|joystick_analog_1[14] ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.083      ; 1.852      ;
; 1.558 ; user_io:my_user_io|sbuf[5]            ; user_io:my_user_io|cmd[6]                ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.083      ; 1.853      ;
; 1.573 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_wptr[2]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.865      ;
; 1.574 ; user_io:my_user_io|sbuf[6]            ; user_io:my_user_io|cmd[7]                ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.083      ; 1.869      ;
; 1.589 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|byte_cnt[3]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.881      ;
; 1.594 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|byte_cnt[6]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.886      ;
; 1.597 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|serial_out_rptr[1]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.889      ;
; 1.618 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_wptr[2]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.910      ;
; 1.649 ; user_io:my_user_io|sbuf[3]            ; user_io:my_user_io|cmd[4]                ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.083      ; 1.944      ;
; 1.651 ; user_io:my_user_io|sbuf[3]            ; user_io:my_user_io|joystick_analog_1[12] ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.083      ; 1.946      ;
; 1.664 ; user_io:my_user_io|serial_out_rptr[2] ; user_io:my_user_io|serial_out_rptr[3]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.956      ;
; 1.671 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|byte_cnt[4]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.963      ;
; 1.672 ; user_io:my_user_io|sbuf[2]            ; user_io:my_user_io|joystick_analog_1[3]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.964      ;
; 1.672 ; user_io:my_user_io|serial_out_rptr[4] ; user_io:my_user_io|serial_out_rptr[5]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.964      ;
; 1.675 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|byte_cnt[1]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.967      ;
; 1.682 ; user_io:my_user_io|serial_out_rptr[3] ; user_io:my_user_io|serial_out_rptr[5]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.974      ;
; 1.687 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|bit_cnt[2]            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.979      ;
; 1.688 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|serial_out_rptr[3]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.980      ;
; 1.707 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|byte_cnt[5]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.999      ;
; 1.723 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|byte_cnt[5]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 2.015      ;
; 1.744 ; user_io:my_user_io|ps2_wptr[1]        ; user_io:my_user_io|ps2_wptr[2]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 2.036      ;
; 1.764 ; user_io:my_user_io|sbuf[3]            ; user_io:my_user_io|joystick_0[4]         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.087      ; 2.063      ;
; 1.781 ; user_io:my_user_io|serial_out_rptr[1] ; user_io:my_user_io|serial_out_rptr[1]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 2.073      ;
; 1.805 ; user_io:my_user_io|serial_out_rptr[2] ; user_io:my_user_io|serial_out_rptr[5]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 2.097      ;
; 1.806 ; user_io:my_user_io|sbuf[4]            ; user_io:my_user_io|joystick_analog_1[13] ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.084      ; 2.102      ;
; 1.829 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|serial_out_rptr[5]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 2.121      ;
; 1.830 ; user_io:my_user_io|sbuf[4]            ; user_io:my_user_io|cmd[5]                ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.083      ; 2.125      ;
; 1.840 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|bit_cnt[1]            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 2.132      ;
; 1.855 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|byte_cnt[2]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 2.147      ;
; 1.868 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|byte_cnt[4]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 2.160      ;
; 1.877 ; user_io:my_user_io|serial_out_rptr[3] ; user_io:my_user_io|serial_out_rptr[4]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 2.169      ;
; 1.889 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|serial_out_rptr[2]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 2.181      ;
; 1.896 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|byte_cnt[5]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 2.188      ;
; 1.897 ; user_io:my_user_io|serial_out_rptr[1] ; user_io:my_user_io|serial_out_rptr[3]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 2.189      ;
; 1.899 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|byte_cnt[7]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 2.191      ;
; 1.901 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~7            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 2.192      ;
; 1.901 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~6            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 2.192      ;
; 1.901 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~5            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 2.192      ;
; 1.901 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~4            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 2.192      ;
; 1.901 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~3            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 2.192      ;
; 1.901 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~2            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 2.192      ;
; 1.901 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~1            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 2.192      ;
; 1.901 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~0            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 2.192      ;
; 1.906 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~23           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.078      ; 2.196      ;
; 1.906 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~22           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.078      ; 2.196      ;
; 1.906 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~21           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.078      ; 2.196      ;
; 1.906 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~20           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.078      ; 2.196      ;
; 1.906 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~19           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.078      ; 2.196      ;
; 1.906 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~18           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.078      ; 2.196      ;
; 1.906 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~17           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.078      ; 2.196      ;
; 1.906 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~16           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.078      ; 2.196      ;
; 1.917 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|byte_cnt[7]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 2.209      ;
; 1.929 ; user_io:my_user_io|sbuf[4]            ; user_io:my_user_io|joystick_analog_1[5]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 2.221      ;
; 1.932 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|byte_cnt[6]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 2.224      ;
; 1.963 ; user_io:my_user_io|sbuf[6]            ; user_io:my_user_io|joystick_analog_0[15] ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 2.246      ;
; 1.967 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|byte_cnt[2]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 2.259      ;
; 1.967 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~23           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.078      ; 2.257      ;
; 1.967 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~22           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.078      ; 2.257      ;
; 1.967 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~21           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.078      ; 2.257      ;
; 1.967 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~20           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.078      ; 2.257      ;
; 1.967 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~19           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.078      ; 2.257      ;
; 1.967 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~18           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.078      ; 2.257      ;
; 1.967 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~17           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.078      ; 2.257      ;
; 1.967 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~16           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.078      ; 2.257      ;
; 1.992 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|byte_cnt[3]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 2.284      ;
; 2.000 ; user_io:my_user_io|serial_out_rptr[2] ; user_io:my_user_io|serial_out_rptr[4]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 2.292      ;
; 2.024 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|serial_out_rptr[4]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 2.316      ;
; 2.038 ; user_io:my_user_io|serial_out_rptr[1] ; user_io:my_user_io|serial_out_rptr[5]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 2.330      ;
+-------+---------------------------------------+------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 9.616 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -6.853       ; -1.747     ; 1.127      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'CLOCK_27[0]'                                                                                                                                                                                                                              ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                   ; Launch Clock                                                          ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.800 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.595      ; 4.465      ;
; -0.800 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.595      ; 4.465      ;
; -0.800 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.595      ; 4.465      ;
; -0.800 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.595      ; 4.465      ;
; -0.800 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.595      ; 4.465      ;
; -0.800 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.595      ; 4.465      ;
; -0.800 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.595      ; 4.465      ;
; -0.800 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.594      ; 4.464      ;
; -0.800 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.595      ; 4.465      ;
; -0.640 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.599      ; 4.309      ;
; -0.640 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.599      ; 4.309      ;
; -0.640 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.599      ; 4.309      ;
; -0.640 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.599      ; 4.309      ;
; -0.640 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.599      ; 4.309      ;
; -0.640 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.599      ; 4.309      ;
; -0.640 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.599      ; 4.309      ;
; -0.640 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.598      ; 4.308      ;
; -0.640 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.599      ; 4.309      ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                      ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 4.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.237     ; 4.327      ;
; 4.118 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.241     ; 4.322      ;
; 4.118 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.244     ; 4.319      ;
; 4.119 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.243     ; 4.319      ;
; 4.122 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.382     ; 4.165      ;
; 4.123 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.378     ; 4.168      ;
; 4.123 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.378     ; 4.168      ;
; 4.125 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.359     ; 4.185      ;
; 4.125 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.385     ; 4.159      ;
; 4.125 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.359     ; 4.185      ;
; 4.129 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.377     ; 4.163      ;
; 4.129 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.377     ; 4.163      ;
; 4.131 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.373     ; 4.165      ;
; 4.131 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.372     ; 4.166      ;
; 4.131 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.373     ; 4.165      ;
; 4.131 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.372     ; 4.166      ;
; 4.134 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.255     ; 4.292      ;
; 4.134 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.235     ; 4.312      ;
; 4.135 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.251     ; 4.295      ;
; 4.135 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.251     ; 4.295      ;
; 4.135 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|udqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.252     ; 4.294      ;
; 4.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.258     ; 4.286      ;
; 4.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.232     ; 4.312      ;
; 4.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.232     ; 4.312      ;
; 4.141 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.250     ; 4.290      ;
; 4.141 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.250     ; 4.290      ;
; 4.143 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.245     ; 4.293      ;
; 4.143 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.245     ; 4.293      ;
; 4.143 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.246     ; 4.292      ;
; 4.143 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.246     ; 4.292      ;
; 4.143 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.238     ; 4.300      ;
; 4.143 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.238     ; 4.300      ;
; 4.148 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.319     ; 4.202      ;
; 4.148 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.318     ; 4.203      ;
; 4.148 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.318     ; 4.203      ;
; 4.149 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.318     ; 4.202      ;
; 4.164 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.191     ; 4.326      ;
; 4.164 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.191     ; 4.326      ;
; 4.164 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.192     ; 4.325      ;
; 4.164 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 4.322      ;
; 4.164 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.194     ; 4.323      ;
; 4.164 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 4.322      ;
; 4.164 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 4.322      ;
; 4.164 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.193     ; 4.324      ;
; 4.164 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.194     ; 4.323      ;
; 4.165 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.191     ; 4.325      ;
; 4.165 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.194     ; 4.322      ;
; 4.165 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.192     ; 4.324      ;
; 4.165 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.192     ; 4.324      ;
; 4.165 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.192     ; 4.324      ;
; 4.165 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.191     ; 4.325      ;
; 4.231 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.206     ; 4.374      ;
; 4.231 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.206     ; 4.374      ;
; 4.383 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.207     ; 4.055      ;
; 4.383 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.207     ; 4.055      ;
; 4.383 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.208     ; 4.054      ;
; 4.384 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.207     ; 4.054      ;
; 4.394 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.271     ; 3.980      ;
; 4.395 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.267     ; 3.983      ;
; 4.395 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.267     ; 3.983      ;
; 4.397 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.274     ; 3.974      ;
; 4.397 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.248     ; 4.000      ;
; 4.397 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.248     ; 4.000      ;
; 4.401 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.266     ; 3.978      ;
; 4.401 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.266     ; 3.978      ;
; 4.403 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.261     ; 3.981      ;
; 4.403 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.261     ; 3.981      ;
; 4.403 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.262     ; 3.980      ;
; 4.403 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.262     ; 3.980      ;
; 4.702 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.193     ; 3.916      ;
; 4.703 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 3.913      ;
; 4.703 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 3.913      ;
; 4.703 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 3.913      ;
; 4.703 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 3.913      ;
; 4.703 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 3.913      ;
; 4.703 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.193     ; 3.915      ;
; 4.703 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 3.913      ;
; 4.703 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.193     ; 3.915      ;
; 4.703 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 3.913      ;
; 4.703 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 3.913      ;
; 4.703 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 3.913      ;
; 4.703 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 3.913      ;
; 4.703 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 3.913      ;
; 4.703 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 3.913      ;
; 4.703 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 3.913      ;
; 4.703 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.193     ; 3.915      ;
; 4.703 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 3.913      ;
; 4.703 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 3.913      ;
; 4.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 3.918      ;
; 4.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 3.918      ;
; 4.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 3.922      ;
; 4.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 3.922      ;
; 4.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 3.922      ;
; 4.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 3.918      ;
; 4.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 3.918      ;
; 4.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 3.918      ;
; 4.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 3.918      ;
; 4.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 3.918      ;
; 4.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 3.918      ;
; 4.708 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 3.918      ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                          ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 11.003 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[1]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 6.535      ;
; 11.016 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 6.535      ;
; 11.016 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 6.535      ;
; 11.091 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[1]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 6.348      ;
; 11.104 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.170     ; 6.348      ;
; 11.104 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.170     ; 6.348      ;
; 11.190 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[1]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 6.348      ;
; 11.203 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 6.348      ;
; 11.203 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 6.348      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[16]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.097      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[17]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.097      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[18]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.097      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[19]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.097      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[20]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.097      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[21]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.097      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[22]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.097      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[23]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.097      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[24]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.097      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[25]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.097      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[26]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.097      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[27]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.097      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[2]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 6.094      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[1]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 6.094      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[3]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 6.094      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[1]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 6.094      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[7]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 6.094      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot4_reg[7]                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 6.094      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|clock_sync_reg                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|last_bus_reg[7]                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 6.094      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[2]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 6.099      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[4]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|latch_delay_line:stimer_delay|data_in_reg                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|latch_delay_line:stimer_delay|shift_reg[2]                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|latch_delay_line:stimer_delay|shift_reg[1]                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|latch_delay_line:stimer_delay|shift_reg[0]                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[5]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audctl_reg[3]                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audctl_reg[5]                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audctl_reg[0]                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[2]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[3]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_clock_reg                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_control_reg[2]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 6.094      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_input_reg[4]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 6.094      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 6.091      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[6]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audctl_reg[4]                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[7]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[3]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|latch_delay_line:twotone_del|shift_reg[1]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|latch_delay_line:twotone_del|shift_reg[0]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audctl_reg[6]                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[3]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[0]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[0]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[1]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[1]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[2]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[2]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[3]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[4]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[4]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[5]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[6]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[6]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[7]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.103      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_reg[4]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 6.091      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot4_reg[4]                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 6.094      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_reg[4]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 6.094      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_full_reg                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_active_reg                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[0]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[2]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[3]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[5]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[6]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[7]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[9]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[8]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[7]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[6]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[4]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[5]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[4]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[3]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[1]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[2]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[1]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serial_out_reg                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_clock_last_reg                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqen_reg[4]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
; 11.446 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[4]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 6.102      ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'SPI_SCK'                                                                                                           ;
+--------+------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                    ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 14.514 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.884     ; 2.469      ;
; 14.514 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.884     ; 2.469      ;
; 14.514 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.884     ; 2.469      ;
; 14.514 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.884     ; 2.469      ;
; 14.514 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.884     ; 2.469      ;
; 14.514 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.884     ; 2.469      ;
+--------+------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'CLOCK_27[0]'                                                                                                                                                                                                                               ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                   ; Launch Clock                                                          ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.817 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.524      ; 4.038      ;
; -0.817 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.524      ; 4.038      ;
; -0.817 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.524      ; 4.038      ;
; -0.817 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.524      ; 4.038      ;
; -0.817 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.524      ; 4.038      ;
; -0.817 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.524      ; 4.038      ;
; -0.817 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.524      ; 4.038      ;
; -0.817 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.523      ; 4.037      ;
; -0.817 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.524      ; 4.038      ;
; -0.646 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.519      ; 4.204      ;
; -0.646 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.519      ; 4.204      ;
; -0.646 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.519      ; 4.204      ;
; -0.646 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.519      ; 4.204      ;
; -0.646 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.519      ; 4.204      ;
; -0.646 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.519      ; 4.204      ;
; -0.646 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.519      ; 4.204      ;
; -0.646 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.518      ; 4.203      ;
; -0.646 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.519      ; 4.204      ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.593 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|dffe4                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 2.235      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a63 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a62 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a61 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a60 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a59 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a58 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a57 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a56 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a31 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a29 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a28 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a27 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a26 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a25 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a24 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.529      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a55 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a54 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a53 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a52 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a51 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a50 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a49 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a48 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a47 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a46 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a45 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a44 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a43 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a42 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a41 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a40 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a39 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a38 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a37 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a36 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a35 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a34 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a33 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a32 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a23 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a22 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a21 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a20 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a19 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a18 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a17 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a16 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 1.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.398      ; 2.552      ;
; 2.804 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|request_sreg                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.703      ; 3.719      ;
; 3.207 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.627      ; 4.046      ;
; 3.208 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.620      ; 4.040      ;
; 3.231 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.604      ; 4.047      ;
; 3.231 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.604      ; 4.047      ;
; 3.247 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[10]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.583      ; 4.042      ;
; 3.247 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[14]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.583      ; 4.042      ;
; 3.272 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[3]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.553      ; 4.037      ;
; 3.272 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.553      ; 4.037      ;
; 3.272 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[7]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.553      ; 4.037      ;
; 3.277 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[0]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 3.690      ;
; 3.277 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[1]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 3.690      ;
; 3.277 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|enable_divider:enable_div|count_reg[2]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 3.690      ;
; 3.277 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|enable_divider:enable_div|count_reg[3]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 3.690      ;
; 3.277 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|enable_divider:enable_div|count_reg[4]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 3.690      ;
; 3.277 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|enable_divider:enable_div|count_reg[5]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 3.690      ;
; 3.277 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|enable_divider:enable_div|count_reg[6]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 3.690      ;
; 3.277 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|enable_divider:enable_div|count_reg[7]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 3.690      ;
; 3.277 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|enable_divider:enable_div|enabled_out_reg                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 3.690      ;
; 3.277 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 3.690      ;
; 3.277 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 3.690      ;
; 3.277 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[4]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 3.690      ;
; 3.277 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; enable_divider:enable_179_clock_div_zpu_pokey|enabled_out_reg                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 3.690      ;
; 3.279 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[19]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.195      ; 3.686      ;
; 3.279 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[31]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.195      ; 3.686      ;
; 3.279 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[24]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.195      ; 3.686      ;
; 3.279 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[28]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.195      ; 3.686      ;
; 3.279 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[21]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.195      ; 3.686      ;
; 3.282 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[23]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.189      ; 3.683      ;
; 3.282 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[29]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.189      ; 3.683      ;
; 3.282 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[17]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.189      ; 3.683      ;
; 3.282 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[20]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.189      ; 3.683      ;
; 3.282 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[25]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.189      ; 3.683      ;
; 3.283 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 3.691      ;
; 3.283 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 3.691      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                  ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 3.268 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 3.692      ;
; 3.268 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 3.692      ;
; 3.268 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 3.692      ;
; 3.268 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 3.692      ;
; 3.268 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 3.692      ;
; 3.268 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 3.692      ;
; 3.268 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 3.692      ;
; 3.268 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 3.692      ;
; 3.268 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 3.692      ;
; 3.268 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 3.692      ;
; 3.268 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 3.692      ;
; 3.268 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 3.692      ;
; 3.270 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cke_reg                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.204      ; 3.705      ;
; 3.272 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.215      ; 3.718      ;
; 3.272 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 3.709      ;
; 3.272 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 3.709      ;
; 3.272 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 3.709      ;
; 3.272 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 3.709      ;
; 3.272 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 3.709      ;
; 3.272 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 3.709      ;
; 3.272 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 3.709      ;
; 3.272 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 3.709      ;
; 3.272 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 3.709      ;
; 3.272 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 3.709      ;
; 3.272 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 3.709      ;
; 3.275 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.683      ;
; 3.275 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.683      ;
; 3.275 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.683      ;
; 3.275 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.683      ;
; 3.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.204      ; 3.720      ;
; 3.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.204      ; 3.720      ;
; 3.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.204      ; 3.720      ;
; 3.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.204      ; 3.720      ;
; 3.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.204      ; 3.720      ;
; 3.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.204      ; 3.720      ;
; 3.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.204      ; 3.720      ;
; 3.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.198      ; 3.714      ;
; 3.286 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 3.717      ;
; 3.286 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 3.717      ;
; 3.286 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 3.717      ;
; 3.286 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 3.717      ;
; 3.286 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 3.717      ;
; 3.286 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 3.717      ;
; 3.286 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.199      ; 3.716      ;
; 3.286 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 3.717      ;
; 3.286 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 3.717      ;
; 3.286 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 3.717      ;
; 3.286 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 3.717      ;
; 3.286 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 3.717      ;
; 3.286 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 3.717      ;
; 3.286 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 3.717      ;
; 3.286 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.200      ; 3.717      ;
; 3.286 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.199      ; 3.716      ;
; 3.292 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 3.712      ;
; 3.292 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 3.712      ;
; 3.292 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 3.712      ;
; 3.292 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 3.712      ;
; 3.292 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 3.712      ;
; 3.292 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.191      ; 3.714      ;
; 3.292 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.191      ; 3.714      ;
; 3.292 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 3.712      ;
; 3.292 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.191      ; 3.714      ;
; 3.292 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 3.712      ;
; 3.292 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 3.712      ;
; 3.292 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 3.712      ;
; 3.292 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 3.712      ;
; 3.292 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 3.712      ;
; 3.292 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 3.712      ;
; 3.292 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 3.712      ;
; 3.292 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.191      ; 3.714      ;
; 3.292 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 3.712      ;
; 3.292 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 3.712      ;
; 3.479 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.182      ; 3.824      ;
; 3.480 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.182      ; 3.825      ;
; 3.480 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.182      ; 3.825      ;
; 3.480 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 3.824      ;
; 3.484 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 3.787      ;
; 3.484 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 3.787      ;
; 3.485 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.126      ; 3.774      ;
; 3.485 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.126      ; 3.774      ;
; 3.485 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.125      ; 3.773      ;
; 3.485 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.125      ; 3.773      ;
; 3.486 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.121      ; 3.770      ;
; 3.486 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.121      ; 3.770      ;
; 3.493 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.116      ; 3.772      ;
; 3.493 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.112      ; 3.768      ;
; 3.493 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.119      ; 3.775      ;
; 3.493 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.119      ; 3.775      ;
; 3.720 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 4.129      ;
; 3.720 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 4.129      ;
; 3.803 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.104      ;
; 3.803 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.104      ;
; 3.804 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 4.091      ;
; 3.804 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 4.091      ;
; 3.804 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 4.090      ;
; 3.804 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 4.090      ;
; 3.805 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.137      ; 4.087      ;
; 3.805 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.137      ; 4.087      ;
; 3.807 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[7]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 4.101      ;
; 3.807 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[8]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 4.101      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'SPI_SCK'                                                                                                            ;
+--------+------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                    ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 18.903 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; -20.800      ; 4.007      ; 2.342      ;
; 18.903 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; -20.800      ; 4.007      ; 2.342      ;
; 18.903 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; -20.800      ; 4.007      ; 2.342      ;
; 18.903 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; -20.800      ; 4.007      ; 2.342      ;
; 18.903 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; -20.800      ; 4.007      ; 2.342      ;
; 18.903 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; -20.800      ; 4.007      ; 2.342      ;
+--------+------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                            ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cke_reg                      ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|reply_reg                    ;
; 4.201 ; 4.359        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                ;
; 4.201 ; 4.359        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                ;
; 4.201 ; 4.359        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ;
; 4.201 ; 4.359        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ;
; 4.205 ; 4.358        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[11]                 ;
; 4.205 ; 4.358        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[5]                  ;
; 4.205 ; 4.358        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[7]                  ;
; 4.205 ; 4.358        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[8]                  ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[10]                 ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[2]                  ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[3]                  ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ;
; 4.206 ; 4.364        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]                ;
; 4.206 ; 4.364        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]                ;
; 4.206 ; 4.364        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                 ;
; 4.206 ; 4.364        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                 ;
; 4.206 ; 4.364        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                 ;
; 4.206 ; 4.364        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                 ;
; 4.206 ; 4.364        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                 ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]               ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]               ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 4.225 ; 4.369        ; 0.144          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.316 ; 4.440        ; 0.124          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.369 ; 4.369        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.440 ; 4.440        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                       ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                                                   ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.372 ; 8.773        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                ;
; 8.372 ; 8.773        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                ;
; 8.372 ; 8.773        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                ;
; 8.372 ; 8.773        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                ;
; 8.372 ; 8.773        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                ;
; 8.372 ; 8.773        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                     ;
; 8.372 ; 8.773        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                     ;
; 8.372 ; 8.773        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                     ;
; 8.372 ; 8.773        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                     ;
; 8.372 ; 8.773        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                     ;
; 8.372 ; 8.773        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                     ;
; 8.372 ; 8.773        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                     ;
; 8.372 ; 8.773        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                     ;
; 8.372 ; 8.773        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                     ;
; 8.372 ; 8.773        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                     ;
; 8.372 ; 8.773        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                     ;
; 8.372 ; 8.773        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                      ;
; 8.372 ; 8.773        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                      ;
; 8.372 ; 8.773        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                      ;
; 8.372 ; 8.773        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                      ;
; 8.372 ; 8.773        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                      ;
; 8.427 ; 8.828        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                ;
; 8.427 ; 8.828        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                ;
; 8.427 ; 8.828        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                ;
; 8.427 ; 8.828        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                ;
; 8.427 ; 8.828        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                ;
; 8.427 ; 8.828        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                     ;
; 8.427 ; 8.828        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                     ;
; 8.427 ; 8.828        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                     ;
; 8.427 ; 8.828        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                     ;
; 8.427 ; 8.828        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                     ;
; 8.427 ; 8.828        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                     ;
; 8.427 ; 8.828        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                     ;
; 8.427 ; 8.828        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                     ;
; 8.427 ; 8.828        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                     ;
; 8.427 ; 8.828        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                     ;
; 8.427 ; 8.828        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                     ;
; 8.427 ; 8.828        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                      ;
; 8.427 ; 8.828        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                      ;
; 8.427 ; 8.828        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                      ;
; 8.427 ; 8.828        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                      ;
; 8.427 ; 8.828        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                      ;
; 8.474 ; 8.694        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[4]                                                         ;
; 8.474 ; 8.694        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Nreg                                                         ;
; 8.474 ; 8.694        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[4]                                                         ;
; 8.474 ; 8.694        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[5]                                                         ;
; 8.474 ; 8.694        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[1]                                                         ;
; 8.474 ; 8.694        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                                                         ;
; 8.474 ; 8.694        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Zreg                                                         ;
; 8.475 ; 8.695        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[4]                                                         ;
; 8.475 ; 8.695        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]                                                  ;
; 8.475 ; 8.695        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]                                                  ;
; 8.475 ; 8.695        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[34]                                                  ;
; 8.475 ; 8.695        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[43]                                                  ;
; 8.476 ; 8.696        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[3]                                                         ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|ram_bank[12]                                           ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[0]                                                         ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:prior_longer_delay|shift_reg[0][0]                                    ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:prior_longer_delay|shift_reg[0][1]                                    ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|break_irq_reg       ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|break_pressed_reg   ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|control_pressed_reg ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|shift_pressed_reg   ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                                                 ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                   ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gractl_reg[4]                                                                         ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                                                                          ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                                          ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[6]                                                                          ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]                                                                          ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[6]                                                         ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theOpcode[7]                                                 ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:prior_longer_delay|shift_reg[1][0]                                    ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                                                                  ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                                                                 ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                                                 ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                                                 ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                                                 ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                                                 ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                                                                  ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                                                                  ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                                                                  ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                                                                  ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                                                                  ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                                                         ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[1]                                                         ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[2]                                                         ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[7]                                                         ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[0]                                                         ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[7]                                                         ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[4]                                                         ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[5]                                                         ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]                                                         ;
; 8.483 ; 8.703        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[13]                                                                                                    ;
; 8.483 ; 8.703        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[3]                                                                                                                          ;
; 8.483 ; 8.703        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]                                                                                                                          ;
; 8.483 ; 8.703        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[7]                                                                                                                          ;
; 8.484 ; 8.704        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                                   ;
; 8.484 ; 8.704        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39]                                                  ;
; 8.484 ; 8.704        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40]                                                  ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                          ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                ; Clock Edge ; Target                                                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; 16.276 ; 16.276       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.280 ; 16.280       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.280 ; 16.280       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.297 ; 16.297       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.297 ; 16.297       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.297 ; 16.297       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.297 ; 16.297       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 16.297 ; 16.297       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.332 ; 16.332       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.332 ; 16.332       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.332 ; 16.332       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.332 ; 16.332       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 16.332 ; 16.332       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.350 ; 16.350       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.350 ; 16.350       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.354 ; 16.354       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'SPI_SCK'                                                                        ;
+--------+--------------+----------------+------------------+---------+------------+------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                   ;
+--------+--------------+----------------+------------------+---------+------------+------------------------------------------+
; 16.636 ; 16.824       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sd_ack                ;
; 16.636 ; 16.824       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sd_din_strobe         ;
; 16.636 ; 16.824       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sd_dout_strobe        ;
; 16.669 ; 16.889       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|SPI_MISO~en           ;
; 16.669 ; 16.889       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|SPI_MISO~reg0         ;
; 16.670 ; 16.890       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[0]    ;
; 16.670 ; 16.890       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[1]    ;
; 16.670 ; 16.890       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[2]    ;
; 16.670 ; 16.890       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[3]    ;
; 16.670 ; 16.890       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[4]    ;
; 16.670 ; 16.890       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[5]    ;
; 16.728 ; 16.916       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~40           ;
; 16.728 ; 16.916       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~41           ;
; 16.728 ; 16.916       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~42           ;
; 16.728 ; 16.916       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~43           ;
; 16.728 ; 16.916       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~44           ;
; 16.728 ; 16.916       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~45           ;
; 16.728 ; 16.916       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~46           ;
; 16.728 ; 16.916       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~47           ;
; 16.728 ; 16.916       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~48           ;
; 16.728 ; 16.916       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~49           ;
; 16.728 ; 16.916       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~50           ;
; 16.728 ; 16.916       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~51           ;
; 16.728 ; 16.916       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~52           ;
; 16.728 ; 16.916       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~53           ;
; 16.728 ; 16.916       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~54           ;
; 16.728 ; 16.916       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~55           ;
; 16.728 ; 16.916       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sd_dout[0]            ;
; 16.728 ; 16.916       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sd_dout[3]            ;
; 16.728 ; 16.916       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sd_dout[4]            ;
; 16.728 ; 16.916       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sd_dout[6]            ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[0]            ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[1]            ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[2]            ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[0]           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[1]           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[2]           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[3]           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[4]           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[5]           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[6]           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[7]           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[0]                ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[1]                ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~32           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~33           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~34           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~35           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~36           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~37           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~38           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~39           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~56           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~57           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~58           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~59           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~60           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~61           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~62           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~63           ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|stick_idx[0]          ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|stick_idx[1]          ;
; 16.729 ; 16.917       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|stick_idx[2]          ;
; 16.731 ; 16.919       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[2]                ;
; 16.731 ; 16.919       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[3]                ;
; 16.731 ; 16.919       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[4]                ;
; 16.731 ; 16.919       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[5]                ;
; 16.731 ; 16.919       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[6]                ;
; 16.731 ; 16.919       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[7]                ;
; 16.731 ; 16.919       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[10] ;
; 16.731 ; 16.919       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[11] ;
; 16.731 ; 16.919       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[12] ;
; 16.731 ; 16.919       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[13] ;
; 16.731 ; 16.919       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[14] ;
; 16.731 ; 16.919       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[15] ;
; 16.731 ; 16.919       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[8]  ;
; 16.731 ; 16.919       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[9]  ;
; 16.732 ; 16.920       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_0[0]         ;
; 16.732 ; 16.920       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_0[1]         ;
; 16.732 ; 16.920       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_0[2]         ;
; 16.732 ; 16.920       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_0[3]         ;
; 16.732 ; 16.920       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_0[4]         ;
; 16.732 ; 16.920       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_0[5]         ;
; 16.732 ; 16.920       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[10] ;
; 16.732 ; 16.920       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[11] ;
; 16.732 ; 16.920       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[12] ;
; 16.732 ; 16.920       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[13] ;
; 16.732 ; 16.920       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[14] ;
; 16.732 ; 16.920       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[15] ;
; 16.732 ; 16.920       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[2]  ;
; 16.732 ; 16.920       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[7]  ;
; 16.732 ; 16.920       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[8]  ;
; 16.732 ; 16.920       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[9]  ;
; 16.732 ; 16.920       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[1]  ;
; 16.732 ; 16.920       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[7]  ;
; 16.733 ; 16.921       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|but_sw[0]             ;
; 16.733 ; 16.921       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|but_sw[1]             ;
; 16.733 ; 16.921       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_1[0]         ;
; 16.733 ; 16.921       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_1[1]         ;
; 16.733 ; 16.921       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_1[2]         ;
+--------+--------------+----------------+------------------+---------+------------+------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_27[0]'                                                                                                              ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock       ; Clock Edge ; Target                                                                         ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+
; 18.277 ; 18.465       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.277 ; 18.465       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.277 ; 18.465       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.277 ; 18.465       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.277 ; 18.465       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.277 ; 18.465       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.277 ; 18.465       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.277 ; 18.465       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.277 ; 18.465       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.350 ; 18.570       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.350 ; 18.570       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.350 ; 18.570       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.350 ; 18.570       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.350 ; 18.570       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.350 ; 18.570       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.350 ; 18.570       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.350 ; 18.570       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.351 ; 18.571       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.362 ; 18.362       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.362 ; 18.362       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 18.366 ; 18.366       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.366 ; 18.366       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.400 ; 18.400       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.410 ; 18.410       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.410 ; 18.410       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.417 ; 18.417       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.417 ; 18.417       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.417 ; 18.417       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.417 ; 18.417       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.417 ; 18.417       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.417 ; 18.417       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.417 ; 18.417       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.417 ; 18.417       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.417 ; 18.417       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.434 ; 18.434       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.438 ; 18.438       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.598 ; 18.598       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.602 ; 18.602       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.619 ; 18.619       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.619 ; 18.619       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.619 ; 18.619       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.619 ; 18.619       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.619 ; 18.619       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.619 ; 18.619       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.619 ; 18.619       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.619 ; 18.619       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.620 ; 18.620       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.626 ; 18.626       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.626 ; 18.626       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.637 ; 18.637       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.668 ; 18.668       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.668 ; 18.668       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.672 ; 18.672       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.672 ; 18.672       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 33.037 ; 37.037       ; 4.000          ; Port Rate        ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]                                                                    ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                           ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                                                                                                                      ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 40.596 ; 41.626       ; 1.030          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ;
; 40.674 ; 41.704       ; 1.030          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_ena_state                                                  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_ena_state                                                  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_ena_state                                                  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate_state                                            ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_ena_state                                        ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|tmp_seq_ena_state                                             ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                      ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                      ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                            ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                                    ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                        ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                        ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                        ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_ena_state                                                                  ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_ena_state                                                                  ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_ena_state                                                                  ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_ena_state                                                                  ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_ena_state                                                                  ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                           ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate_state                                                            ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0]                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5]                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0]                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_counter_state                                                        ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_ena_state                                                        ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reset_state                                                                   ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|tmp_seq_ena_state                                                             ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_ena_state                                                  ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate2_state                                           ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                        ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack     ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 44052.505 ; 44052.725    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 44052.505 ; 44052.725    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 44052.505 ; 44052.725    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 44052.505 ; 44052.725    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 44052.505 ; 44052.725    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
; 44052.505 ; 44052.725    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 44052.638 ; 44052.782    ; 0.144          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 44052.722 ; 44052.910    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 44052.722 ; 44052.910    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 44052.722 ; 44052.910    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 44052.722 ; 44052.910    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
; 44052.722 ; 44052.910    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ;
; 44052.730 ; 44052.854    ; 0.124          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 44052.774 ; 44052.774    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_kbd_data|clk                                                                                                           ;
; 44052.774 ; 44052.774    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_r_inc|clk                                                                                                              ;
; 44052.774 ; 44052.774    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[0]|clk                                                                                                        ;
; 44052.774 ; 44052.774    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[1]|clk                                                                                                        ;
; 44052.774 ; 44052.774    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[2]|clk                                                                                                        ;
; 44052.774 ; 44052.774    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[3]|clk                                                                                                        ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_parity|clk                                                                                                             ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[0]|clk                                                                                                            ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[1]|clk                                                                                                            ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[2]|clk                                                                                                            ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[0]|clk                                                                                                         ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[1]|clk                                                                                                         ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[2]|clk                                                                                                         ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[3]|clk                                                                                                         ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[4]|clk                                                                                                         ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[5]|clk                                                                                                         ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[6]|clk                                                                                                         ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[7]|clk                                                                                                         ;
; 44052.782 ; 44052.782    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 44052.782 ; 44052.782    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 44052.854 ; 44052.854    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 44052.854 ; 44052.854    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_parity|clk                                                                                                             ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_r_inc|clk                                                                                                              ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[0]|clk                                                                                                            ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[1]|clk                                                                                                            ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[2]|clk                                                                                                            ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[0]|clk                                                                                                         ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[1]|clk                                                                                                         ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[2]|clk                                                                                                         ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[3]|clk                                                                                                         ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[4]|clk                                                                                                         ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[5]|clk                                                                                                         ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[6]|clk                                                                                                         ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[7]|clk                                                                                                         ;
; 44052.862 ; 44052.862    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_kbd_data|clk                                                                                                           ;
; 44052.862 ; 44052.862    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[0]|clk                                                                                                        ;
; 44052.862 ; 44052.862    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[1]|clk                                                                                                        ;
; 44052.862 ; 44052.862    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[2]|clk                                                                                                        ;
; 44052.862 ; 44052.862    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[3]|clk                                                                                                        ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                      ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK     ; 4.018 ; 4.789 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK     ; 4.334 ; 4.789 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 3.028 ; 3.141 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 3.023 ; 3.136 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 3.026 ; 3.139 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 3.028 ; 3.141 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 3.028 ; 3.141 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.965 ; 3.082 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.975 ; 3.092 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.965 ; 3.082 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.966 ; 3.083 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 3.009 ; 3.122 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 3.009 ; 3.122 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 3.000 ; 3.113 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 3.000 ; 3.113 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 3.013 ; 3.126 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 3.013 ; 3.126 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 3.024 ; 3.137 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 3.024 ; 3.137 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                         ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK     ; 5.886  ; 5.588  ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK     ; 9.605  ; 9.380  ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; -1.950 ; -2.067 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; -2.010 ; -2.123 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; -2.014 ; -2.127 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; -2.015 ; -2.128 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; -2.015 ; -2.128 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; -1.950 ; -2.067 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; -1.960 ; -2.077 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; -1.950 ; -2.067 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; -1.951 ; -2.068 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; -1.997 ; -2.110 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; -1.997 ; -2.110 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; -1.986 ; -2.099 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; -1.986 ; -2.099 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; -2.000 ; -2.113 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; -2.000 ; -2.113 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; -2.011 ; -2.124 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; -2.011 ; -2.124 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                              ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK     ; 18.176 ; 17.609 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; CLOCK_27[0] ; 2.550  ; 2.205  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 2.331  ; 2.037  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 2.333  ; 2.039  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 2.334  ; 2.040  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 2.345  ; 2.051  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 2.249  ; 1.981  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 2.550  ; 2.205  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 2.534  ; 2.189  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 2.539  ; 2.194  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 2.539  ; 2.194  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 2.536  ; 2.191  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 2.332  ; 2.038  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 2.543  ; 2.198  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 2.331  ; 2.037  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 2.331  ; 2.037  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 2.322  ; 2.028  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 2.586  ; 2.354  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.546  ; 2.201  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.522  ; 2.177  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.518  ; 2.173  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.234  ; 1.966  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.234  ; 1.966  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.345  ; 2.051  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.355  ; 2.061  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.345  ; 2.051  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.344  ; 2.050  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.515  ; 2.170  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.515  ; 2.170  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.546  ; 2.201  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.546  ; 2.201  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.229  ; 1.961  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.532  ; 2.187  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.541  ; 2.196  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.238  ; 1.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 2.515  ; 2.170  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 2.344  ; 2.050  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 2.332  ; 2.038  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 2.331  ; 2.037  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 2.344  ; 2.050  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 8.856  ; 8.165  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 6.178  ; 5.621  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 5.716  ; 6.376  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 28.098 ; 27.588 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 27.654 ; 27.158 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 28.098 ; 27.588 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 27.595 ; 27.031 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 24.821 ; 24.466 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 26.529 ; 26.089 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 26.694 ; 26.203 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 24.458 ; 23.845 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 23.850 ; 23.367 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 24.458 ; 23.845 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 24.257 ; 23.659 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 22.940 ; 22.433 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 23.560 ; 22.782 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 18.724 ; 18.183 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 5.844  ; 5.251  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 29.151 ; 28.660 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 28.514 ; 28.018 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 29.151 ; 28.660 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 28.379 ; 27.906 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 26.631 ; 26.120 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 27.497 ; 27.114 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 27.144 ; 26.604 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 5.441  ; 4.859  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -0.844 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -1.206 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                      ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK     ; 13.958 ; 13.395 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; CLOCK_27[0] ; 1.418  ; 1.151  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 1.498  ; 1.205  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 1.500  ; 1.207  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 1.501  ; 1.208  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 1.512  ; 1.219  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 1.418  ; 1.151  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 1.719  ; 1.375  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 1.703  ; 1.359  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 1.708  ; 1.364  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 1.708  ; 1.364  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 1.705  ; 1.361  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 1.499  ; 1.206  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 1.712  ; 1.368  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 1.489  ; 1.196  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 1.498  ; 1.205  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 1.489  ; 1.196  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 1.748  ; 1.515  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.398  ; 1.131  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.691  ; 1.347  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.688  ; 1.344  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.403  ; 1.136  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.403  ; 1.136  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.512  ; 1.219  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.522  ; 1.229  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.512  ; 1.219  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.511  ; 1.218  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.685  ; 1.341  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.685  ; 1.341  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.714  ; 1.370  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.714  ; 1.370  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.398  ; 1.131  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.701  ; 1.357  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.710  ; 1.366  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.407  ; 1.140  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 1.684  ; 1.340  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 1.511  ; 1.218  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 1.499  ; 1.206  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 1.498  ; 1.205  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 1.511  ; 1.218  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 7.842  ; 7.160  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 5.270  ; 4.717  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 4.807  ; 5.459  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 5.000  ; 4.483  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 5.904  ; 5.402  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 5.950  ; 5.291  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 5.825  ; 5.407  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 5.684  ; 5.275  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 5.000  ; 4.483  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 5.610  ; 5.174  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 5.377  ; 4.895  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 5.377  ; 4.895  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 6.206  ; 5.545  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 5.906  ; 5.386  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 5.959  ; 5.476  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 6.045  ; 5.542  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 6.185  ; 5.654  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 4.951  ; 4.363  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 5.193  ; 4.734  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 5.779  ; 5.402  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 5.193  ; 4.734  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 5.808  ; 5.363  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 6.201  ; 5.660  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 6.074  ; 5.462  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 5.777  ; 5.279  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 4.564  ; 3.987  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -1.630 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -1.989 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+----------------------------------------------------------+
; Propagation Delay                                        ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 9.387 ; 9.147 ; 9.839 ; 9.839 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------+
; Minimum Propagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 8.613 ; 8.613 ; 9.029 ; 9.058 ;
+------------+-------------+-------+-------+-------+-------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK     ; 17.289 ; 17.289 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.847  ; 2.847  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.854  ; 2.854  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.850  ; 2.850  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.869  ; 2.869  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.869  ; 2.869  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.958  ; 2.958  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.968  ; 2.968  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.958  ; 2.958  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.957  ; 2.957  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.847  ; 2.847  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.847  ; 2.847  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.878  ; 2.878  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.878  ; 2.878  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.864  ; 2.864  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.864  ; 2.864  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.873  ; 2.873  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.873  ; 2.873  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                        ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK     ; 12.524 ; 12.553 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.010  ; 1.037  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.016  ; 1.043  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.013  ; 1.040  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.031  ; 1.058  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.031  ; 1.058  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.087  ; 1.114  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.097  ; 1.124  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.087  ; 1.114  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.086  ; 1.113  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.010  ; 1.037  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.010  ; 1.037  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.039  ; 1.066  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.039  ; 1.066  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.026  ; 1.053  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.026  ; 1.053  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.035  ; 1.062  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.035  ; 1.062  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                     ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK     ; 16.834    ; 17.074    ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.440     ; 2.926     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.447     ; 2.933     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.443     ; 2.929     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.462     ; 2.948     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.462     ; 2.948     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.533     ; 3.037     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.543     ; 3.047     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.533     ; 3.037     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.532     ; 3.036     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.440     ; 2.926     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.440     ; 2.926     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.471     ; 2.957     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.471     ; 2.957     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.457     ; 2.943     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.457     ; 2.943     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.466     ; 2.952     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.466     ; 2.952     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                             ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK     ; 12.317    ; 12.317    ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.086     ; 1.086     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.092     ; 1.092     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.089     ; 1.089     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.107     ; 1.107     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.107     ; 1.107     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.163     ; 1.163     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.173     ; 1.173     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.163     ; 1.163     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.162     ; 1.162     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.086     ; 1.086     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.086     ; 1.086     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.115     ; 1.115     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.115     ; 1.115     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.102     ; 1.102     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.102     ; 1.102     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.111     ; 1.111     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.111     ; 1.111     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                                                                    ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                            ; Note                                                          ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
; 42.45 MHz  ; 42.45 MHz       ; SPI_SCK                                                               ;                                                               ;
; 65.56 MHz  ; 65.56 MHz       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                               ;
; 73.68 MHz  ; 73.68 MHz       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ;                                                               ;
; 155.69 MHz ; 155.69 MHz      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                               ;
; 253.29 MHz ; 250.0 MHz       ; CLOCK_27[0]                                                           ; limit due to minimum period restriction (max I/O toggle rate) ;
; 267.88 MHz ; 267.88 MHz      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ;                                                               ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+-------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                              ;
+-----------------------------------------------------------------------+---------+---------------+
; Clock                                                                 ; Slack   ; End Point TNS ;
+-----------------------------------------------------------------------+---------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -23.058 ; -3167.912     ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; -15.220 ; -178.913      ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.227  ; -1.227        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; -0.396  ; -0.396        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.210   ; 0.000         ;
; SPI_SCK                                                               ; 9.068   ; 0.000         ;
; CLOCK_27[0]                                                           ; 33.089  ; 0.000         ;
+-----------------------------------------------------------------------+---------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                              ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; -1.160 ; -1.160        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.330  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.402  ; 0.000         ;
; CLOCK_27[0]                                                           ; 0.403  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.403  ; 0.000         ;
; SPI_SCK                                                               ; 0.675  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 9.330  ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                                          ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; CLOCK_27[0]                                                           ; -0.827 ; -7.435        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.551  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.511 ; 0.000         ;
; SPI_SCK                                                               ; 14.873 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                                           ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; CLOCK_27[0]                                                           ; -0.608 ; -5.464        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.467  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.940  ; 0.000         ;
; SPI_SCK                                                               ; 19.144 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                                  ;
+-----------------------------------------------------------------------+-----------+---------------+
; Clock                                                                 ; Slack     ; End Point TNS ;
+-----------------------------------------------------------------------+-----------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.097     ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 4.243     ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.403     ; 0.000         ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 16.279    ; 0.000         ;
; SPI_SCK                                                               ; 16.988    ; 0.000         ;
; CLOCK_27[0]                                                           ; 18.273    ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 40.596    ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 44052.511 ; 0.000         ;
+-----------------------------------------------------------------------+-----------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                  ;
+---------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                        ; To Node                                                                                                                 ; Launch Clock ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -23.058 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.333    ; 10.648     ;
; -23.044 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.328    ; 10.639     ;
; -22.947 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 10.538     ;
; -22.935 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.333    ; 10.525     ;
; -22.897 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.333    ; 10.487     ;
; -22.883 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.328    ; 10.478     ;
; -22.791 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.333    ; 10.381     ;
; -22.786 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 10.377     ;
; -22.782 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.333    ; 10.372     ;
; -22.774 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.333    ; 10.364     ;
; -22.768 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.328    ; 10.363     ;
; -22.757 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.333    ; 10.347     ;
; -22.755 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -11.881    ; 10.797     ;
; -22.743 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.328    ; 10.338     ;
; -22.732 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 10.323     ;
; -22.703 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.333    ; 10.293     ;
; -22.689 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.328    ; 10.284     ;
; -22.671 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 10.262     ;
; -22.660 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.333    ; 10.250     ;
; -22.659 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.333    ; 10.249     ;
; -22.646 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.328    ; 10.241     ;
; -22.646 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 10.237     ;
; -22.634 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.333    ; 10.224     ;
; -22.630 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.333    ; 10.220     ;
; -22.624 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.328    ; 10.219     ;
; -22.603 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.333    ; 10.193     ;
; -22.601 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 10.192     ;
; -22.594 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -11.881    ; 10.636     ;
; -22.592 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 10.183     ;
; -22.589 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.328    ; 10.184     ;
; -22.580 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.333    ; 10.170     ;
; -22.571 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 10.162     ;
; -22.549 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 10.140     ;
; -22.537 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.333    ; 10.127     ;
; -22.534 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[21]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.329    ; 10.128     ;
; -22.532 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[22]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.329    ; 10.126     ;
; -22.525 ; user_io:my_user_io|joystick_1[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -11.888    ; 10.560     ;
; -22.518 ; user_io:my_user_io|joystick_1[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -11.888    ; 10.553     ;
; -22.515 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.333    ; 10.105     ;
; -22.492 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 10.083     ;
; -22.490 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.333    ; 10.080     ;
; -22.480 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.333    ; 10.070     ;
; -22.479 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -11.881    ; 10.521     ;
; -22.463 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.328    ; 10.058     ;
; -22.456 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 10.047     ;
; -22.454 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -11.881    ; 10.496     ;
; -22.440 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 10.031     ;
; -22.436 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.333    ; 10.026     ;
; -22.431 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 10.022     ;
; -22.406 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[20]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 9.997      ;
; -22.400 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -11.881    ; 10.442     ;
; -22.393 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.333    ; 9.983      ;
; -22.380 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[13]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.329    ; 9.974      ;
; -22.377 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 9.968      ;
; -22.373 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[21]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.329    ; 9.967      ;
; -22.371 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[22]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.329    ; 9.965      ;
; -22.364 ; user_io:my_user_io|joystick_1[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -11.888    ; 10.399     ;
; -22.357 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -11.881    ; 10.399     ;
; -22.357 ; user_io:my_user_io|joystick_1[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -11.888    ; 10.392     ;
; -22.348 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[17]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.307    ; 9.964      ;
; -22.348 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.328    ; 9.943      ;
; -22.336 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.333    ; 9.926      ;
; -22.334 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 9.925      ;
; -22.327 ; user_io:my_user_io|joystick_1[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -11.866    ; 10.384     ;
; -22.325 ; user_io:my_user_io|joystick_1[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -11.866    ; 10.382     ;
; -22.325 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 9.916      ;
; -22.323 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.328    ; 9.918      ;
; -22.300 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -11.881    ; 10.342     ;
; -22.300 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 9.891      ;
; -22.292 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[18]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.333    ; 9.882      ;
; -22.277 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 9.868      ;
; -22.269 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.328    ; 9.864      ;
; -22.258 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[21]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.329    ; 9.852      ;
; -22.256 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[22]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.329    ; 9.850      ;
; -22.249 ; user_io:my_user_io|joystick_1[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -11.888    ; 10.284     ;
; -22.246 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 9.837      ;
; -22.245 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[20]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 9.836      ;
; -22.242 ; user_io:my_user_io|joystick_1[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -11.888    ; 10.277     ;
; -22.233 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[21]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.329    ; 9.827      ;
; -22.231 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[22]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.329    ; 9.825      ;
; -22.229 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[15]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.304    ; 9.848      ;
; -22.226 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.328    ; 9.821      ;
; -22.224 ; user_io:my_user_io|joystick_1[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -11.888    ; 10.259     ;
; -22.219 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[13]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.329    ; 9.813      ;
; -22.217 ; user_io:my_user_io|joystick_1[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[1]   ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.325    ; 9.815      ;
; -22.217 ; user_io:my_user_io|joystick_1[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -11.888    ; 10.252     ;
; -22.203 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 9.794      ;
; -22.200 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[16]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.330    ; 9.793      ;
; -22.187 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[17]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.307    ; 9.803      ;
; -22.179 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[21]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.329    ; 9.773      ;
; -22.177 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[22]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.329    ; 9.771      ;
; -22.175 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                         ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -11.854    ; 10.244     ;
; -22.169 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.328    ; 9.764      ;
; -22.166 ; user_io:my_user_io|joystick_1[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -11.866    ; 10.223     ;
; -22.164 ; user_io:my_user_io|joystick_1[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -11.866    ; 10.221     ;
; -22.157 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[19]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.330    ; 9.750      ;
; -22.146 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.332    ; 9.737      ;
; -22.137 ; user_io:my_user_io|joystick_1[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -11.869    ; 10.191     ;
; -22.136 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[21]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.329    ; 9.730      ;
; -22.134 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[22]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -12.329    ; 9.728      ;
+---------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                           ;
+---------+--------------------------------+------------------------------------+--------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                      ; To Node                            ; Launch Clock ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+---------+--------------------------------+------------------------------------+--------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -15.220 ; user_io:my_user_io|ps2_fifo~54 ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.332    ; 2.811      ;
; -15.136 ; user_io:my_user_io|ps2_fifo~55 ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.332    ; 2.727      ;
; -15.092 ; user_io:my_user_io|ps2_fifo~53 ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.332    ; 2.683      ;
; -15.087 ; user_io:my_user_io|ps2_fifo~47 ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.332    ; 2.678      ;
; -15.019 ; user_io:my_user_io|ps2_fifo~50 ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.332    ; 2.610      ;
; -15.012 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.612      ;
; -15.012 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.612      ;
; -15.012 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.612      ;
; -15.012 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.612      ;
; -15.012 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.612      ;
; -15.012 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.612      ;
; -15.012 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.612      ;
; -15.012 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_parity      ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.612      ;
; -15.008 ; user_io:my_user_io|ps2_fifo~45 ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.332    ; 2.599      ;
; -14.987 ; user_io:my_user_io|ps2_fifo~38 ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.333    ; 2.577      ;
; -14.981 ; user_io:my_user_io|ps2_fifo~12 ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 2.582      ;
; -14.980 ; user_io:my_user_io|ps2_fifo~49 ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.333    ; 2.570      ;
; -14.978 ; user_io:my_user_io|ps2_fifo~9  ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 2.579      ;
; -14.972 ; user_io:my_user_io|ps2_fifo~42 ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.332    ; 2.563      ;
; -14.969 ; user_io:my_user_io|ps2_fifo~46 ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.332    ; 2.560      ;
; -14.917 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.517      ;
; -14.905 ; user_io:my_user_io|ps2_fifo~15 ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 2.506      ;
; -14.904 ; user_io:my_user_io|ps2_fifo~39 ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.333    ; 2.494      ;
; -14.859 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.459      ;
; -14.859 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.459      ;
; -14.859 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.459      ;
; -14.859 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.459      ;
; -14.859 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.459      ;
; -14.859 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.459      ;
; -14.859 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.459      ;
; -14.859 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_parity      ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.459      ;
; -14.847 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_state[0] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.447      ;
; -14.827 ; user_io:my_user_io|ps2_fifo~37 ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.333    ; 2.417      ;
; -14.808 ; user_io:my_user_io|ps2_fifo~23 ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 2.409      ;
; -14.801 ; user_io:my_user_io|ps2_fifo~51 ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.333    ; 2.391      ;
; -14.792 ; user_io:my_user_io|ps2_fifo~48 ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.332    ; 2.383      ;
; -14.787 ; user_io:my_user_io|ps2_fifo~34 ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.333    ; 2.377      ;
; -14.750 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.350      ;
; -14.745 ; user_io:my_user_io|ps2_fifo~8  ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 2.346      ;
; -14.743 ; user_io:my_user_io|ps2_fifo~11 ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 2.344      ;
; -14.737 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.337      ;
; -14.737 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.337      ;
; -14.737 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.337      ;
; -14.737 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.337      ;
; -14.737 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.337      ;
; -14.737 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.337      ;
; -14.737 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.337      ;
; -14.737 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_parity      ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.337      ;
; -14.736 ; user_io:my_user_io|ps2_fifo~33 ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.333    ; 2.326      ;
; -14.727 ; user_io:my_user_io|ps2_fifo~52 ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.332    ; 2.318      ;
; -14.717 ; user_io:my_user_io|ps2_fifo~41 ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.333    ; 2.307      ;
; -14.680 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_state[0] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.280      ;
; -14.674 ; user_io:my_user_io|ps2_fifo~14 ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 2.275      ;
; -14.671 ; user_io:my_user_io|ps2_fifo~7  ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 2.272      ;
; -14.663 ; user_io:my_user_io|ps2_fifo~40 ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.332    ; 2.254      ;
; -14.660 ; user_io:my_user_io|ps2_fifo~43 ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.333    ; 2.250      ;
; -14.642 ; user_io:my_user_io|ps2_fifo~19 ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 2.243      ;
; -14.638 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.238      ;
; -14.636 ; user_io:my_user_io|ps2_fifo~20 ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 2.237      ;
; -14.633 ; user_io:my_user_io|ps2_fifo~16 ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 2.234      ;
; -14.632 ; user_io:my_user_io|ps2_fifo~17 ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 2.233      ;
; -14.630 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_kbd_data    ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.230      ;
; -14.621 ; user_io:my_user_io|ps2_fifo~44 ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.332    ; 2.212      ;
; -14.611 ; user_io:my_user_io|ps2_fifo~10 ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 2.212      ;
; -14.592 ; user_io:my_user_io|ps2_fifo~22 ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 2.193      ;
; -14.580 ; user_io:my_user_io|ps2_fifo~13 ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 2.181      ;
; -14.568 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_state[0] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.168      ;
; -14.527 ; user_io:my_user_io|ps2_fifo~32 ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.333    ; 2.117      ;
; -14.521 ; user_io:my_user_io|ps2_fifo~35 ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.333    ; 2.111      ;
; -14.511 ; user_io:my_user_io|ps2_fifo~3  ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 2.112      ;
; -14.510 ; user_io:my_user_io|ps2_fifo~63 ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.333    ; 2.100      ;
; -14.509 ; user_io:my_user_io|ps2_fifo~0  ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 2.110      ;
; -14.508 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_kbd_data    ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.108      ;
; -14.494 ; user_io:my_user_io|ps2_fifo~36 ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.333    ; 2.084      ;
; -14.453 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_kbd_data    ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 2.053      ;
; -14.450 ; user_io:my_user_io|ps2_fifo~4  ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 2.051      ;
; -14.446 ; user_io:my_user_io|ps2_fifo~1  ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 2.047      ;
; -14.431 ; user_io:my_user_io|ps2_fifo~61 ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.333    ; 2.021      ;
; -14.407 ; user_io:my_user_io|ps2_fifo~6  ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 2.008      ;
; -14.394 ; user_io:my_user_io|ps2_fifo~58 ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.333    ; 1.984      ;
; -14.387 ; user_io:my_user_io|ps2_fifo~62 ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.333    ; 1.977      ;
; -14.346 ; user_io:my_user_io|ps2_fifo~2  ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 1.947      ;
; -14.345 ; user_io:my_user_io|ps2_fifo~5  ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 1.946      ;
; -14.325 ; user_io:my_user_io|ps2_fifo~21 ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 1.926      ;
; -14.322 ; user_io:my_user_io|ps2_fifo~18 ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 1.923      ;
; -14.277 ; user_io:my_user_io|ps2_fifo~31 ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 1.878      ;
; -14.133 ; user_io:my_user_io|ps2_fifo~56 ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.333    ; 1.723      ;
; -14.130 ; user_io:my_user_io|ps2_fifo~57 ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.333    ; 1.720      ;
; -14.128 ; user_io:my_user_io|ps2_fifo~59 ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.333    ; 1.718      ;
; -14.118 ; user_io:my_user_io|ps2_fifo~27 ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 1.719      ;
; -14.117 ; user_io:my_user_io|ps2_fifo~24 ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 1.718      ;
; -14.100 ; user_io:my_user_io|ps2_fifo~60 ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.333    ; 1.690      ;
; -14.056 ; user_io:my_user_io|ps2_fifo~28 ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 1.657      ;
; -14.051 ; user_io:my_user_io|ps2_fifo~25 ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 1.652      ;
; -14.012 ; user_io:my_user_io|ps2_fifo~30 ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 1.613      ;
; -13.909 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_r_inc       ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 1.509      ;
; -13.776 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_r_inc       ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 1.376      ;
; -13.743 ; user_io:my_user_io|ps2_fifo~26 ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 1.344      ;
; -13.743 ; user_io:my_user_io|ps2_fifo~29 ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.322    ; 1.344      ;
; -13.630 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_r_inc       ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -12.323    ; 1.230      ;
+---------+--------------------------------+------------------------------------+--------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                   ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -1.227 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.958        ; -1.815     ; 1.253      ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                                                     ; Launch Clock                                                          ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -0.396 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.371        ; 1.203      ; 1.812      ;
; 34.880 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.732     ; 8.168      ;
; 35.465 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|altsyncram:altsyncram4|altsyncram_cul3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.731     ; 7.584      ;
; 36.909 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.384     ; 6.487      ;
; 36.909 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.387     ; 6.484      ;
; 36.910 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.384     ; 6.486      ;
; 36.911 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.387     ; 6.482      ;
; 37.095 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                                               ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.384     ; 6.301      ;
; 37.098 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.393     ; 6.289      ;
; 37.124 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.387     ; 6.269      ;
; 37.128 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.384     ; 6.268      ;
; 37.258 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.387     ; 6.135      ;
; 37.262 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.384     ; 6.134      ;
; 37.599 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.384     ; 5.797      ;
; 37.902 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.387     ; 5.491      ;
; 37.922 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.384     ; 5.474      ;
; 38.214 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.383     ; 5.183      ;
; 38.215 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.383     ; 5.182      ;
; 38.258 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                                               ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.387     ; 5.135      ;
; 38.271 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.387     ; 5.122      ;
; 38.389 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.383     ; 5.008      ;
; 38.401 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.606      ; 6.874      ;
; 38.489 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.387     ; 4.904      ;
; 38.525 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.383     ; 4.872      ;
; 38.654 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.386     ; 4.740      ;
; 38.665 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.387     ; 4.728      ;
; 38.673 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.383     ; 4.724      ;
; 38.707 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.603      ; 6.565      ;
; 38.781 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.606      ; 6.494      ;
; 38.791 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.606      ; 6.484      ;
; 38.801 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.387     ; 4.592      ;
; 38.811 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.387     ; 4.582      ;
; 38.882 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.603      ; 6.390      ;
; 38.903 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.603      ; 6.369      ;
; 39.244 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.628      ; 6.053      ;
; 40.541 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate2_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate3_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.122     ; 1.005      ;
; 40.544 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate3_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.122     ; 1.002      ;
; 74.686 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.093     ; 8.556      ;
; 74.940 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.096     ; 8.299      ;
; 75.012 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.093     ; 8.230      ;
; 75.031 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.093     ; 8.211      ;
; 75.092 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.096     ; 8.147      ;
; 75.128 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.096     ; 8.111      ;
; 75.439 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 7.825      ;
; 75.564 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 7.695      ;
; 75.849 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 7.410      ;
; 75.929 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 7.338      ;
; 75.955 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 7.304      ;
; 76.133 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.070     ; 7.132      ;
; 76.165 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 7.094      ;
; 76.183 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 7.081      ;
; 76.255 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 7.012      ;
; 76.274 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 6.993      ;
; 76.335 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 6.929      ;
; 76.371 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 6.893      ;
; 76.387 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.073     ; 6.875      ;
; 76.459 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.070     ; 6.806      ;
; 76.478 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.070     ; 6.787      ;
; 76.496 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.110     ; 6.729      ;
; 76.539 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.073     ; 6.723      ;
; 76.575 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.073     ; 6.687      ;
; 76.666 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.062     ; 6.607      ;
; 76.750 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.113     ; 6.472      ;
; 76.822 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.110     ; 6.403      ;
; 76.841 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.110     ; 6.384      ;
; 76.870 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.064     ; 6.401      ;
; 76.902 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.113     ; 6.320      ;
; 76.938 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.113     ; 6.284      ;
; 77.117 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.083     ; 6.135      ;
; 77.250 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.088     ; 5.997      ;
; 77.265 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.072     ; 5.998      ;
; 77.278 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 5.972      ;
; 77.333 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.088     ; 5.914      ;
; 77.350 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.109     ; 5.876      ;
; 77.402 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.083     ; 5.850      ;
; 77.404 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.088     ; 5.843      ;
; 77.456 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.088     ; 5.791      ;
; 77.508 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.083     ; 5.744      ;
; 77.539 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.088     ; 5.708      ;
; 77.563 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 5.687      ;
; 77.605 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.088     ; 5.642      ;
; 77.610 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.088     ; 5.637      ;
; 77.635 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.109     ; 5.591      ;
; 77.669 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 5.581      ;
; 77.718 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.083     ; 5.534      ;
; 77.741 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.109     ; 5.485      ;
; 77.811 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.088     ; 5.436      ;
; 77.851 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.091     ; 5.393      ;
; 77.879 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 5.371      ;
; 77.934 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.091     ; 5.310      ;
; 77.951 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.109     ; 5.275      ;
; 78.005 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.091     ; 5.239      ;
; 78.206 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.091     ; 5.038      ;
; 78.206 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.091     ; 5.038      ;
; 78.289 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.091     ; 4.955      ;
; 78.360 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.091     ; 4.884      ;
; 78.494 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.770      ;
; 78.494 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.770      ;
; 78.494 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.770      ;
; 78.494 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.770      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.210 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.405        ; -1.814     ; 1.254      ;
; 2.387 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 6.162      ;
; 2.460 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 6.089      ;
; 2.466 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 6.083      ;
; 2.569 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 5.980      ;
; 2.600 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 5.990      ;
; 2.621 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 5.921      ;
; 2.656 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 5.888      ;
; 2.664 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 5.880      ;
; 2.667 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 5.875      ;
; 2.669 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 5.880      ;
; 2.676 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 5.866      ;
; 2.682 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 5.862      ;
; 2.705 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 5.885      ;
; 2.721 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 5.871      ;
; 2.755 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 5.787      ;
; 2.767 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.148     ; 5.771      ;
; 2.775 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 5.774      ;
; 2.782 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 5.776      ;
; 2.785 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 5.759      ;
; 2.788 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 5.802      ;
; 2.826 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 5.766      ;
; 2.860 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 5.689      ;
; 2.864 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.725      ;
; 2.864 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.135     ; 5.687      ;
; 2.868 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 5.681      ;
; 2.872 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.717      ;
; 2.873 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 5.671      ;
; 2.882 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.067     ; 5.863      ;
; 2.886 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 5.663      ;
; 2.888 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 5.652      ;
; 2.890 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.699      ;
; 2.893 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 5.697      ;
; 2.903 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.126     ; 5.657      ;
; 2.909 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                    ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.067     ; 5.836      ;
; 2.909 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|ldqm_reg                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.680      ;
; 2.921 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                    ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.067     ; 5.824      ;
; 2.955 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.148     ; 5.583      ;
; 2.956 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 5.634      ;
; 2.961 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 5.581      ;
; 2.961 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 5.581      ;
; 2.970 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 5.588      ;
; 2.979 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 5.570      ;
; 2.980 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.067     ; 5.765      ;
; 2.989 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 5.560      ;
; 2.993 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 5.565      ;
; 2.993 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.596      ;
; 3.019 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.098     ; 5.569      ;
; 3.023 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.066     ; 5.723      ;
; 3.050 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                    ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.066     ; 5.696      ;
; 3.050 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 5.494      ;
; 3.061 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 5.529      ;
; 3.062 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.066     ; 5.684      ;
; 3.062 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                    ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.066     ; 5.684      ;
; 3.065 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.098     ; 5.523      ;
; 3.071 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|udqm_reg                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.150     ; 5.465      ;
; 3.074 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.098     ; 5.514      ;
; 3.077 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 5.472      ;
; 3.081 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.508      ;
; 3.083 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.067     ; 5.662      ;
; 3.083 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.140     ; 5.463      ;
; 3.089 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                    ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.066     ; 5.657      ;
; 3.094 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.495      ;
; 3.097 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.098     ; 5.491      ;
; 3.101 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                    ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.066     ; 5.645      ;
; 3.102 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.487      ;
; 3.109 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 5.436      ;
; 3.110 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.098     ; 5.478      ;
; 3.114 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.126     ; 5.446      ;
; 3.115 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.067     ; 5.630      ;
; 3.120 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.469      ;
; 3.121 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.066     ; 5.625      ;
; 3.123 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.148     ; 5.415      ;
; 3.130 ; sdram_statemachine:sdram_adaptor|request_sreg                               ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.651     ; 5.031      ;
; 3.131 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 5.413      ;
; 3.138 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 5.420      ;
; 3.139 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.118     ; 5.429      ;
; 3.142 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.098     ; 5.446      ;
; 3.153 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.098     ; 5.435      ;
; 3.155 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 5.390      ;
; 3.160 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.066     ; 5.586      ;
; 3.160 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.157     ; 5.369      ;
; 3.161 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.118     ; 5.407      ;
; 3.164 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 5.381      ;
; 3.181 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 5.377      ;
; 3.183 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 5.361      ;
; 3.185 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 5.357      ;
; 3.205 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.127     ; 5.354      ;
; 3.212 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|ba_reg[0]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 5.374      ;
; 3.213 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.067     ; 5.532      ;
; 3.215 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.374      ;
; 3.216 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.136     ; 5.334      ;
; 3.220 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 5.329      ;
; 3.220 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.098     ; 5.368      ;
; 3.224 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.066     ; 5.522      ;
; 3.225 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|ba_reg[0]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 5.361      ;
; 3.235 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.067     ; 5.510      ;
; 3.236 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.098     ; 5.352      ;
; 3.243 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 5.302      ;
; 3.248 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.148     ; 5.290      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'SPI_SCK'                                                                                                                 ;
+--------+--------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                      ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 9.068  ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.687     ; 8.113      ;
; 9.158  ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.687     ; 8.023      ;
; 9.209  ; user_io:my_user_io|cmd[1]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.699     ; 7.960      ;
; 9.459  ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.687     ; 7.722      ;
; 9.879  ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.699     ; 7.290      ;
; 9.970  ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 7.200      ;
; 9.970  ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 7.200      ;
; 9.970  ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 7.200      ;
; 9.970  ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 7.200      ;
; 9.970  ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 7.200      ;
; 9.992  ; user_io:my_user_io|cmd[4]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 7.178      ;
; 9.992  ; user_io:my_user_io|cmd[4]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 7.178      ;
; 9.992  ; user_io:my_user_io|cmd[4]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 7.178      ;
; 9.992  ; user_io:my_user_io|cmd[4]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 7.178      ;
; 9.992  ; user_io:my_user_io|cmd[4]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 7.178      ;
; 10.048 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.687     ; 7.133      ;
; 10.059 ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 7.111      ;
; 10.081 ; user_io:my_user_io|cmd[4]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 7.089      ;
; 10.294 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.876      ;
; 10.294 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.876      ;
; 10.294 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.876      ;
; 10.294 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.876      ;
; 10.294 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.876      ;
; 10.383 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.787      ;
; 10.383 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.787      ;
; 10.383 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.787      ;
; 10.383 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.787      ;
; 10.383 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.787      ;
; 10.383 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.787      ;
; 10.472 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.698      ;
; 10.913 ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.697     ; 6.258      ;
; 10.935 ; user_io:my_user_io|cmd[4]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.697     ; 6.236      ;
; 10.947 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.223      ;
; 10.947 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.223      ;
; 10.947 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.223      ;
; 10.947 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.223      ;
; 10.947 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.223      ;
; 11.036 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.134      ;
; 11.147 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.023      ;
; 11.147 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.023      ;
; 11.147 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.023      ;
; 11.147 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.023      ;
; 11.147 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 6.023      ;
; 11.236 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.698     ; 5.934      ;
; 11.237 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.697     ; 5.934      ;
; 11.252 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.693     ; 5.923      ;
; 11.259 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.693     ; 5.916      ;
; 11.326 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.697     ; 5.845      ;
; 11.429 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.693     ; 5.746      ;
; 11.473 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.697     ; 5.698      ;
; 11.474 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.697     ; 5.697      ;
; 11.493 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.693     ; 5.682      ;
; 11.552 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.693     ; 5.623      ;
; 11.567 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.607      ;
; 11.567 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.607      ;
; 11.567 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.607      ;
; 11.567 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.607      ;
; 11.567 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.607      ;
; 11.574 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.600      ;
; 11.574 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.600      ;
; 11.574 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.600      ;
; 11.574 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.600      ;
; 11.574 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.600      ;
; 11.634 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.540      ;
; 11.641 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.533      ;
; 11.717 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.688     ; 5.463      ;
; 11.717 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.688     ; 5.463      ;
; 11.717 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.688     ; 5.463      ;
; 11.717 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.688     ; 5.463      ;
; 11.717 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.688     ; 5.463      ;
; 11.744 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.430      ;
; 11.744 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.430      ;
; 11.744 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.430      ;
; 11.744 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.430      ;
; 11.744 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.430      ;
; 11.784 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.688     ; 5.396      ;
; 11.811 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.363      ;
; 11.867 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.307      ;
; 11.867 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.307      ;
; 11.867 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.307      ;
; 11.867 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.307      ;
; 11.867 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.307      ;
; 11.934 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.240      ;
; 12.004 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.693     ; 5.171      ;
; 12.053 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.121      ;
; 12.053 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.121      ;
; 12.053 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.121      ;
; 12.053 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.121      ;
; 12.053 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.121      ;
; 12.094 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.080      ;
; 12.094 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.080      ;
; 12.094 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.080      ;
; 12.094 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.080      ;
; 12.094 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.080      ;
; 12.103 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.693     ; 5.072      ;
; 12.120 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.054      ;
; 12.161 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.694     ; 5.013      ;
; 12.846 ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.700     ; 4.322      ;
; 12.846 ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.700     ; 4.322      ;
; 12.846 ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.700     ; 4.322      ;
+--------+--------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'CLOCK_27[0]'                                                                                                                                                            ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 33.089 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 3.878      ;
; 33.184 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 3.783      ;
; 33.188 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 3.779      ;
; 33.736 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 3.231      ;
; 33.758 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 3.210      ;
; 34.053 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.914      ;
; 34.055 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.912      ;
; 34.181 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.787      ;
; 34.219 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.749      ;
; 34.226 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.741      ;
; 34.253 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.715      ;
; 34.289 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.679      ;
; 34.364 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.603      ;
; 34.426 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.542      ;
; 34.474 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.494      ;
; 34.549 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.419      ;
; 34.554 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.414      ;
; 34.601 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.367      ;
; 34.642 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.326      ;
; 34.649 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.319      ;
; 34.691 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.277      ;
; 34.701 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.267      ;
; 34.740 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.228      ;
; 34.754 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.214      ;
; 34.814 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.154      ;
; 34.891 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.077      ;
; 34.897 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.071      ;
; 34.905 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.063      ;
; 34.974 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.994      ;
; 34.975 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.993      ;
; 35.049 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.919      ;
; 35.056 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.912      ;
; 35.058 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.910      ;
; 35.059 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.909      ;
; 35.066 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.902      ;
; 35.075 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.893      ;
; 35.162 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.806      ;
; 35.168 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.800      ;
; 35.169 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.799      ;
; 35.170 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.798      ;
; 35.212 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.756      ;
; 35.214 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.754      ;
; 35.221 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.747      ;
; 35.226 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.742      ;
; 35.229 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.739      ;
; 35.229 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.739      ;
; 35.230 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.738      ;
; 35.232 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.736      ;
; 35.233 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.735      ;
; 35.236 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.732      ;
; 35.239 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.729      ;
; 35.240 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.728      ;
; 35.288 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.680      ;
; 35.383 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.585      ;
; 35.390 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.578      ;
; 35.423 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.545      ;
; 35.809 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.159      ;
; 35.819 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.149      ;
; 35.854 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.114      ;
; 36.198 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 0.770      ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                   ; To Node                                                                                                                                                                                                                                             ; Launch Clock                                                          ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -1.160 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.017        ; 2.376      ; 1.598      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.404  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.458  ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.724      ;
; 0.458  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.724      ;
; 0.458  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.724      ;
; 0.470  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.736      ;
; 0.471  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.737      ;
; 0.472  ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.738      ;
; 0.479  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.745      ;
; 0.480  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|tmp_seq_ena_state                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.746      ;
; 0.500  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.416      ; 1.146      ;
; 0.500  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.766      ;
; 0.501  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reset_state                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.766      ;
; 0.501  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|altsyncram:altsyncram4|altsyncram_cul3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.419      ; 1.150      ;
; 0.503  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.768      ;
; 0.508  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.774      ;
; 0.529  ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.795      ;
; 0.609  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.875      ;
; 0.610  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|tmp_seq_ena_state                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.876      ;
; 0.611  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_ena_state                                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.877      ;
; 0.619  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_counter_state                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.884      ;
; 0.620  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_counter_state                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.886      ;
; 0.620  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate_state                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.886      ;
; 0.632  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reset_state                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.898      ;
; 0.632  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reset_state                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.898      ;
; 0.644  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_counter_state                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.910      ;
; 0.648  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|tmp_seq_ena_state                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_ena_state                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.914      ;
; 0.648  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.416      ; 1.294      ;
; 0.663  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.929      ;
; 0.664  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_ena_state                                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.929      ;
; 0.683  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.950      ;
; 0.683  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.950      ;
; 0.684  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.951      ;
; 0.684  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.951      ;
; 0.685  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.951      ;
; 0.686  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.953      ;
; 0.686  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.952      ;
; 0.686  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.952      ;
; 0.687  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.954      ;
; 0.687  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.954      ;
; 0.687  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.953      ;
; 0.688  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.954      ;
; 0.689  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.956      ;
; 0.689  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.956      ;
; 0.689  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.689  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.689  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.690  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.957      ;
; 0.690  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.957      ;
; 0.690  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.957      ;
; 0.690  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.956      ;
; 0.692  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.958      ;
; 0.692  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.958      ;
; 0.693  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.959      ;
; 0.693  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.959      ;
; 0.694  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.960      ;
; 0.694  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.960      ;
; 0.694  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.960      ;
; 0.695  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.961      ;
; 0.695  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.961      ;
; 0.695  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.961      ;
; 0.695  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.961      ;
; 0.696  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.962      ;
; 0.696  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.962      ;
; 0.696  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.962      ;
; 0.696  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.962      ;
; 0.696  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.962      ;
; 0.696  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.962      ;
; 0.697  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.963      ;
; 0.697  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.963      ;
; 0.697  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.963      ;
; 0.697  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.963      ;
; 0.697  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.963      ;
; 0.698  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.964      ;
; 0.699  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.965      ;
; 0.700  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.966      ;
; 0.700  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.966      ;
; 0.700  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.966      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                                                 ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.330 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[4]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.428      ; 0.988      ;
; 0.344 ; sdram_statemachine:sdram_adaptor|data_out_reg[9]                                                                                                                                  ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[9]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.177      ; 0.737      ;
; 0.345 ; sdram_statemachine:sdram_adaptor|data_out_reg[10]                                                                                                                                 ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[10]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.177      ; 0.738      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_add_sp2                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_add_sp2                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_resync                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_resync                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.385 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.089      ; 0.669      ;
; 0.386 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|control_pressed_reg          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|control_pressed_reg                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 0.669      ;
; 0.386 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|break_pressed_reg            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|break_pressed_reg                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 0.669      ;
; 0.386 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|shift_pressed_reg            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|shift_pressed_reg                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 0.669      ;
; 0.386 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[6]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.428      ; 1.044      ;
; 0.386 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 0.669      ;
; 0.387 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[1]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.422      ; 1.039      ;
; 0.388 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[3]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.427      ; 1.045      ;
; 0.394 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[6]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.428      ; 1.052      ;
; 0.395 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[5]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.427      ; 1.052      ;
; 0.397 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[3]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.422      ; 1.049      ;
; 0.397 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[6]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.426      ; 1.053      ;
; 0.399 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[0]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.422      ; 1.051      ;
; 0.399 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]                                                                                  ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a4~porta_datain_reg0                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.426      ; 1.055      ;
; 0.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[4]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.427      ; 1.058      ;
; 0.402 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                               ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[1]                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[1]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[2]                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[2]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[3]                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[3]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[0]                                                                                                  ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[0]                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[1]                                                                                                  ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[1]                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[2]                                                                                                  ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[2]                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[3]                                                                                                  ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[3]                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                                                                 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchPage                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchPage                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_enable                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_enable                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|nmiReg                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|nmiReg                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[1]                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[1]                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[0]                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[0]                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                                                                                 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[0]                                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[0]                                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[1]                                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[1]                                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[9]                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[9]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[10]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[10]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_32bit_reg                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_32bit_reg                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5                                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_reg                                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_reg                                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                                                                                                   ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[34]                                                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[34]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[18]                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[18]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_freezer_reg                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_freezer_reg                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|full_dff ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|full_dff                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[50]                                                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[50]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                                                     ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[61]                                                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[61]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[276]                                                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[276]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[18]                                                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[18]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[369]                                                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[369]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[11]                                                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[11]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[6]                                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[6]                                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[5]                                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[5]                                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[1]                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[1]                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                             ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                     ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.402 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.455 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.722      ;
; 0.686 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.952      ;
; 0.688 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.954      ;
; 0.689 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.689 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.692 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.958      ;
; 0.692 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.958      ;
; 0.692 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.958      ;
; 0.693 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.960      ;
; 0.693 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.960      ;
; 0.693 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.960      ;
; 0.697 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.964      ;
; 0.697 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.964      ;
; 0.697 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.964      ;
; 0.699 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.966      ;
; 0.705 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.972      ;
; 0.706 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.973      ;
; 0.706 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.973      ;
; 0.706 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.973      ;
; 0.709 ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.975      ;
; 0.710 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.977      ;
; 0.712 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.979      ;
; 0.713 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.980      ;
; 0.713 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.980      ;
; 0.715 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.981      ;
; 0.715 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.981      ;
; 0.720 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.986      ;
; 0.721 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.987      ;
; 0.723 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.990      ;
; 0.729 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.996      ;
; 0.738 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.004      ;
; 0.750 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.016      ;
; 0.790 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 1.166      ;
; 0.808 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 1.184      ;
; 0.809 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 1.185      ;
; 0.861 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.128      ;
; 0.862 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.129      ;
; 0.865 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.132      ;
; 0.865 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.132      ;
; 0.866 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.133      ;
; 1.001 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.266      ;
; 1.007 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.273      ;
; 1.008 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.274      ;
; 1.009 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.275      ;
; 1.010 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.276      ;
; 1.010 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.276      ;
; 1.013 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.073      ; 1.281      ;
; 1.013 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.279      ;
; 1.013 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.279      ;
; 1.015 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.282      ;
; 1.015 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.282      ;
; 1.015 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.282      ;
; 1.016 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.283      ;
; 1.018 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.285      ;
; 1.018 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.285      ;
; 1.021 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.073      ; 1.289      ;
; 1.021 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.288      ;
; 1.021 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.288      ;
; 1.022 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.288      ;
; 1.026 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.293      ;
; 1.026 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.292      ;
; 1.026 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.292      ;
; 1.027 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.294      ;
; 1.027 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.294      ;
; 1.027 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 1.403      ;
; 1.028 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.295      ;
; 1.028 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.295      ;
; 1.030 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.297      ;
; 1.031 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.298      ;
; 1.031 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 1.407      ;
; 1.033 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.300      ;
; 1.033 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.300      ;
; 1.033 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.300      ;
; 1.034 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.301      ;
; 1.037 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.303      ;
; 1.037 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.303      ;
; 1.039 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.305      ;
; 1.040 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.306      ;
; 1.042 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.309      ;
; 1.043 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.310      ;
; 1.043 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.310      ;
; 1.043 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 1.419      ;
; 1.045 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.311      ;
; 1.047 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.314      ;
; 1.054 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.320      ;
; 1.055 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.321      ;
; 1.060 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.326      ;
; 1.062 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.328      ;
; 1.066 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 1.442      ;
; 1.102 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.368      ;
; 1.108 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.374      ;
; 1.108 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.374      ;
; 1.111 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.378      ;
; 1.112 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.379      ;
; 1.118 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.385      ;
; 1.118 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.385      ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'CLOCK_27[0]'                                                                                                                                                            ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.418 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 0.684      ;
; 0.696 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 0.962      ;
; 0.696 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 0.962      ;
; 0.710 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 0.976      ;
; 1.016 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.282      ;
; 1.021 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.287      ;
; 1.030 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.296      ;
; 1.041 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.307      ;
; 1.044 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.310      ;
; 1.062 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.328      ;
; 1.125 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.391      ;
; 1.132 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.398      ;
; 1.143 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.409      ;
; 1.153 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.419      ;
; 1.158 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.424      ;
; 1.173 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.439      ;
; 1.175 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.441      ;
; 1.176 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.442      ;
; 1.186 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.452      ;
; 1.264 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.530      ;
; 1.307 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.573      ;
; 1.312 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.578      ;
; 1.315 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.581      ;
; 1.318 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.584      ;
; 1.319 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.585      ;
; 1.323 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.589      ;
; 1.326 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.592      ;
; 1.327 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.593      ;
; 1.330 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.596      ;
; 1.338 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.604      ;
; 1.341 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.607      ;
; 1.343 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.609      ;
; 1.350 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.616      ;
; 1.412 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.678      ;
; 1.412 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.678      ;
; 1.415 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.681      ;
; 1.415 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.681      ;
; 1.419 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.686      ;
; 1.422 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.689      ;
; 1.431 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.697      ;
; 1.433 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.699      ;
; 1.435 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.701      ;
; 1.436 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.703      ;
; 1.457 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.724      ;
; 1.472 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.738      ;
; 1.474 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.740      ;
; 1.483 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.749      ;
; 1.485 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.751      ;
; 1.540 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.807      ;
; 1.542 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.809      ;
; 1.543 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.810      ;
; 2.005 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 2.271      ;
; 2.168 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 2.434      ;
; 2.315 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 2.581      ;
; 2.325 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 2.591      ;
; 2.621 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 2.887      ;
; 2.625 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 2.891      ;
; 2.636 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 2.902      ;
; 2.728 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 2.995      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                       ;
+-------+------------------------------------+------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                          ; To Node                            ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------+------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.403 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_rptr[0]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_rptr[1]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; user_io:my_user_io|ps2_tx_byte[7]  ; user_io:my_user_io|ps2_tx_byte[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; user_io:my_user_io|ps2_parity      ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.418 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.684      ;
; 0.472 ; user_io:my_user_io|ps2_tx_byte[0]  ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.738      ;
; 0.493 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.759      ;
; 0.646 ; user_io:my_user_io|ps2_tx_byte[3]  ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.912      ;
; 0.646 ; user_io:my_user_io|ps2_tx_byte[2]  ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.912      ;
; 0.646 ; user_io:my_user_io|ps2_tx_byte[1]  ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.912      ;
; 0.647 ; user_io:my_user_io|ps2_tx_byte[5]  ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.913      ;
; 0.648 ; user_io:my_user_io|ps2_tx_byte[6]  ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.914      ;
; 0.648 ; user_io:my_user_io|ps2_tx_byte[4]  ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.914      ;
; 0.702 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.968      ;
; 0.703 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.969      ;
; 0.735 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.001      ;
; 0.736 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.002      ;
; 0.763 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.029      ;
; 0.763 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.029      ;
; 0.763 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.029      ;
; 0.764 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.030      ;
; 0.789 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.055      ;
; 0.833 ; user_io:my_user_io|ps2_r_inc       ; user_io:my_user_io|ps2_rptr[1]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.099      ;
; 0.834 ; user_io:my_user_io|ps2_r_inc       ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.100      ;
; 0.836 ; user_io:my_user_io|ps2_r_inc       ; user_io:my_user_io|ps2_rptr[0]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.102      ;
; 0.861 ; user_io:my_user_io|ps2_tx_byte[7]  ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.127      ;
; 0.962 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.228      ;
; 0.966 ; user_io:my_user_io|ps2_parity      ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.232      ;
; 1.003 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.269      ;
; 1.113 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.379      ;
; 1.114 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.380      ;
; 1.123 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_rptr[1]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.389      ;
; 1.126 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.392      ;
; 1.126 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.392      ;
; 1.131 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.397      ;
; 1.142 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.408      ;
; 1.145 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.411      ;
; 1.146 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.412      ;
; 1.296 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.562      ;
; 1.322 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.588      ;
; 1.353 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.619      ;
; 1.357 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.623      ;
; 1.417 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.683      ;
; 1.421 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.687      ;
; 1.470 ; user_io:my_user_io|ps2_kbd_data    ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.736      ;
; 1.477 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.743      ;
; 1.495 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.761      ;
; 1.547 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.813      ;
; 1.579 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.845      ;
; 1.585 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.851      ;
; 1.591 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.857      ;
; 1.592 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.858      ;
; 1.599 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.865      ;
; 1.643 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.909      ;
; 1.673 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.939      ;
; 1.684 ; user_io:my_user_io|ps2_tx_byte[0]  ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.950      ;
; 1.691 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.957      ;
; 1.702 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.968      ;
; 1.801 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.067      ;
; 1.801 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.067      ;
; 1.801 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.067      ;
; 1.801 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.067      ;
; 1.801 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.067      ;
; 1.801 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.067      ;
; 1.801 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.067      ;
; 1.814 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.080      ;
; 1.817 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.083      ;
; 1.824 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.090      ;
; 1.859 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.125      ;
; 1.874 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.140      ;
; 1.892 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.158      ;
; 1.910 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.176      ;
; 1.926 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.192      ;
; 1.927 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.193      ;
; 1.941 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.207      ;
; 1.955 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.221      ;
; 1.956 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.222      ;
; 1.956 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.222      ;
; 1.956 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.222      ;
; 1.956 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.222      ;
; 1.956 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.222      ;
; 1.956 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.222      ;
; 1.956 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.222      ;
; 1.974 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.240      ;
; 1.993 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.259      ;
; 2.023 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.289      ;
; 2.033 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.299      ;
; 2.063 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.329      ;
; 2.071 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.337      ;
; 2.071 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.337      ;
; 2.071 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.337      ;
; 2.071 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.337      ;
; 2.071 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.337      ;
; 2.071 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.337      ;
; 2.071 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.337      ;
; 2.078 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.344      ;
+-------+------------------------------------+------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'SPI_SCK'                                                                                                                           ;
+-------+---------------------------------------+------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                  ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.675 ; user_io:my_user_io|sbuf[1]            ; user_io:my_user_io|joystick_analog_0[2]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.942      ;
; 0.676 ; user_io:my_user_io|sbuf[6]            ; user_io:my_user_io|joystick_analog_0[7]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.943      ;
; 0.686 ; user_io:my_user_io|sbuf[3]            ; user_io:my_user_io|joystick_analog_0[4]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.953      ;
; 0.687 ; user_io:my_user_io|sbuf[3]            ; user_io:my_user_io|sbuf[4]               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.954      ;
; 0.718 ; user_io:my_user_io|sbuf[4]            ; user_io:my_user_io|sbuf[5]               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.985      ;
; 0.859 ; user_io:my_user_io|sbuf[0]            ; user_io:my_user_io|sbuf[1]               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 1.126      ;
; 0.866 ; user_io:my_user_io|sbuf[4]            ; user_io:my_user_io|joystick_analog_0[5]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 1.133      ;
; 0.878 ; user_io:my_user_io|sbuf[5]            ; user_io:my_user_io|sbuf[6]               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 1.145      ;
; 0.879 ; user_io:my_user_io|sbuf[2]            ; user_io:my_user_io|sbuf[3]               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 1.146      ;
; 0.880 ; user_io:my_user_io|sbuf[5]            ; user_io:my_user_io|joystick_analog_0[6]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 1.147      ;
; 0.881 ; user_io:my_user_io|sbuf[2]            ; user_io:my_user_io|joystick_analog_0[3]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 1.148      ;
; 0.943 ; user_io:my_user_io|serial_out_rptr[5] ; user_io:my_user_io|serial_out_rptr[5]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 1.207      ;
; 1.046 ; user_io:my_user_io|sbuf[0]            ; user_io:my_user_io|joystick_analog_0[1]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 1.313      ;
; 1.065 ; user_io:my_user_io|sbuf[1]            ; user_io:my_user_io|sbuf[2]               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 1.332      ;
; 1.068 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|byte_cnt[4]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.334      ;
; 1.071 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|serial_out_rptr[0]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 1.335      ;
; 1.077 ; user_io:my_user_io|status[0]          ; user_io:my_user_io|status[0]             ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 1.344      ;
; 1.203 ; user_io:my_user_io|serial_out_rptr[3] ; user_io:my_user_io|serial_out_rptr[3]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 1.467      ;
; 1.239 ; user_io:my_user_io|ps2_wptr[1]        ; user_io:my_user_io|ps2_wptr[1]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 1.506      ;
; 1.261 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|bit_cnt[2]            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.527      ;
; 1.261 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|byte_cnt[5]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.527      ;
; 1.274 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|bit_cnt[0]            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.540      ;
; 1.301 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_wptr[0]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 1.568      ;
; 1.302 ; user_io:my_user_io|sbuf[6]            ; user_io:my_user_io|joystick_analog_1[7]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 1.569      ;
; 1.315 ; user_io:my_user_io|sbuf[0]            ; user_io:my_user_io|joystick_analog_1[9]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.074      ; 1.584      ;
; 1.332 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_wptr[1]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 1.599      ;
; 1.348 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|byte_cnt[7]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.614      ;
; 1.366 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|byte_cnt[4]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.632      ;
; 1.387 ; user_io:my_user_io|sbuf[6]            ; user_io:my_user_io|joystick_analog_1[15] ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.074      ; 1.656      ;
; 1.418 ; user_io:my_user_io|sbuf[5]            ; user_io:my_user_io|joystick_analog_1[14] ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.074      ; 1.687      ;
; 1.419 ; user_io:my_user_io|sbuf[5]            ; user_io:my_user_io|cmd[6]                ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.074      ; 1.688      ;
; 1.427 ; user_io:my_user_io|sbuf[6]            ; user_io:my_user_io|cmd[7]                ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.074      ; 1.696      ;
; 1.430 ; user_io:my_user_io|serial_out_rptr[4] ; user_io:my_user_io|serial_out_rptr[4]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 1.694      ;
; 1.432 ; user_io:my_user_io|serial_out_rptr[2] ; user_io:my_user_io|serial_out_rptr[2]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 1.696      ;
; 1.433 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_wptr[2]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 1.700      ;
; 1.444 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|bit_cnt[2]            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.710      ;
; 1.466 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|serial_out_rptr[1]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 1.730      ;
; 1.474 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|byte_cnt[3]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.740      ;
; 1.478 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|byte_cnt[6]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.744      ;
; 1.489 ; user_io:my_user_io|sbuf[3]            ; user_io:my_user_io|cmd[4]                ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.074      ; 1.758      ;
; 1.490 ; user_io:my_user_io|sbuf[3]            ; user_io:my_user_io|joystick_analog_1[12] ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.074      ; 1.759      ;
; 1.518 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|byte_cnt[4]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.784      ;
; 1.518 ; user_io:my_user_io|serial_out_rptr[2] ; user_io:my_user_io|serial_out_rptr[3]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 1.782      ;
; 1.519 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_wptr[2]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 1.786      ;
; 1.519 ; user_io:my_user_io|serial_out_rptr[4] ; user_io:my_user_io|serial_out_rptr[5]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 1.783      ;
; 1.524 ; user_io:my_user_io|serial_out_rptr[3] ; user_io:my_user_io|serial_out_rptr[5]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 1.788      ;
; 1.530 ; user_io:my_user_io|sbuf[2]            ; user_io:my_user_io|joystick_analog_1[3]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 1.797      ;
; 1.534 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|serial_out_rptr[3]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 1.798      ;
; 1.538 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|byte_cnt[1]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.804      ;
; 1.576 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|bit_cnt[2]            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.842      ;
; 1.580 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|byte_cnt[5]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.846      ;
; 1.594 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|byte_cnt[5]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.860      ;
; 1.596 ; user_io:my_user_io|sbuf[3]            ; user_io:my_user_io|joystick_0[4]         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.077      ; 1.868      ;
; 1.602 ; user_io:my_user_io|serial_out_rptr[1] ; user_io:my_user_io|serial_out_rptr[1]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 1.866      ;
; 1.609 ; user_io:my_user_io|sbuf[4]            ; user_io:my_user_io|joystick_analog_1[13] ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.074      ; 1.878      ;
; 1.616 ; user_io:my_user_io|ps2_wptr[1]        ; user_io:my_user_io|ps2_wptr[2]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 1.883      ;
; 1.638 ; user_io:my_user_io|serial_out_rptr[2] ; user_io:my_user_io|serial_out_rptr[5]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 1.902      ;
; 1.645 ; user_io:my_user_io|sbuf[4]            ; user_io:my_user_io|cmd[5]                ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.074      ; 1.914      ;
; 1.654 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|serial_out_rptr[5]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 1.918      ;
; 1.671 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|byte_cnt[4]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.937      ;
; 1.674 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|byte_cnt[2]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.940      ;
; 1.679 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|bit_cnt[1]            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.945      ;
; 1.717 ; user_io:my_user_io|serial_out_rptr[3] ; user_io:my_user_io|serial_out_rptr[4]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 1.981      ;
; 1.721 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~7            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.987      ;
; 1.721 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~6            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.987      ;
; 1.721 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~5            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.987      ;
; 1.721 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~4            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.987      ;
; 1.721 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~3            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.987      ;
; 1.721 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~2            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.987      ;
; 1.721 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~1            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.987      ;
; 1.721 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~0            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.987      ;
; 1.728 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~23           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.994      ;
; 1.728 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~22           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.994      ;
; 1.728 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~21           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.994      ;
; 1.728 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~20           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.994      ;
; 1.728 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~19           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.994      ;
; 1.728 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~18           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.994      ;
; 1.728 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~17           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.994      ;
; 1.728 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~16           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 1.994      ;
; 1.730 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|serial_out_rptr[2]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 1.994      ;
; 1.746 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|byte_cnt[7]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 2.012      ;
; 1.746 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|byte_cnt[5]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 2.012      ;
; 1.748 ; user_io:my_user_io|serial_out_rptr[1] ; user_io:my_user_io|serial_out_rptr[3]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 2.012      ;
; 1.756 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|byte_cnt[7]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 2.022      ;
; 1.759 ; user_io:my_user_io|sbuf[4]            ; user_io:my_user_io|joystick_analog_1[5]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 2.026      ;
; 1.770 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|byte_cnt[6]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 2.036      ;
; 1.775 ; user_io:my_user_io|sbuf[6]            ; user_io:my_user_io|joystick_analog_0[15] ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.064      ; 2.034      ;
; 1.802 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|byte_cnt[2]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 2.068      ;
; 1.812 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~23           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 2.078      ;
; 1.812 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~22           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 2.078      ;
; 1.812 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~21           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 2.078      ;
; 1.812 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~20           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 2.078      ;
; 1.812 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~19           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 2.078      ;
; 1.812 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~18           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 2.078      ;
; 1.812 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~17           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 2.078      ;
; 1.812 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~16           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 2.078      ;
; 1.830 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|byte_cnt[3]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 2.096      ;
; 1.831 ; user_io:my_user_io|serial_out_rptr[2] ; user_io:my_user_io|serial_out_rptr[4]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 2.095      ;
; 1.847 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|serial_out_rptr[4]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 2.111      ;
; 1.863 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|byte_cnt[7]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 2.129      ;
+-------+---------------------------------------+------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 9.330 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -6.853       ; -1.565     ; 1.014      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'CLOCK_27[0]'                                                                                                                                                                                                                               ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                   ; Launch Clock                                                          ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.827 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.138      ; 4.036      ;
; -0.826 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.139      ; 4.036      ;
; -0.826 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.139      ; 4.036      ;
; -0.826 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.139      ; 4.036      ;
; -0.826 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.139      ; 4.036      ;
; -0.826 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.139      ; 4.036      ;
; -0.826 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.139      ; 4.036      ;
; -0.826 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.139      ; 4.036      ;
; -0.826 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.139      ; 4.036      ;
; -0.680 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.141      ; 3.892      ;
; -0.679 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.142      ; 3.892      ;
; -0.679 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.142      ; 3.892      ;
; -0.679 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.142      ; 3.892      ;
; -0.679 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.142      ; 3.892      ;
; -0.679 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.142      ; 3.892      ;
; -0.679 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.142      ; 3.892      ;
; -0.679 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.142      ; 3.892      ;
; -0.679 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.142      ; 3.892      ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                 ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                      ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 4.551 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.290     ; 3.834      ;
; 4.551 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.290     ; 3.834      ;
; 4.552 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.290     ; 3.833      ;
; 4.552 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.290     ; 3.833      ;
; 4.568 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.344     ; 3.763      ;
; 4.568 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.344     ; 3.763      ;
; 4.569 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.347     ; 3.759      ;
; 4.570 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.328     ; 3.777      ;
; 4.570 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.351     ; 3.754      ;
; 4.570 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.328     ; 3.777      ;
; 4.570 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 3.901      ;
; 4.572 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.218     ; 3.896      ;
; 4.573 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.210     ; 3.903      ;
; 4.573 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.216     ; 3.897      ;
; 4.575 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.337     ; 3.763      ;
; 4.575 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.337     ; 3.763      ;
; 4.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.342     ; 3.757      ;
; 4.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.342     ; 3.757      ;
; 4.578 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.338     ; 3.759      ;
; 4.578 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.338     ; 3.759      ;
; 4.586 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.208     ; 3.892      ;
; 4.588 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.170     ; 3.928      ;
; 4.588 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.170     ; 3.928      ;
; 4.588 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.174     ; 3.924      ;
; 4.588 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.171     ; 3.927      ;
; 4.588 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.171     ; 3.927      ;
; 4.588 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 3.926      ;
; 4.588 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.171     ; 3.927      ;
; 4.589 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.170     ; 3.927      ;
; 4.589 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.170     ; 3.927      ;
; 4.589 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 3.925      ;
; 4.589 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.174     ; 3.923      ;
; 4.589 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 3.924      ;
; 4.589 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 3.924      ;
; 4.589 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.171     ; 3.926      ;
; 4.589 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 3.925      ;
; 4.590 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.224     ; 3.872      ;
; 4.590 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.224     ; 3.872      ;
; 4.591 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.227     ; 3.868      ;
; 4.591 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|udqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.224     ; 3.871      ;
; 4.592 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.231     ; 3.863      ;
; 4.592 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.208     ; 3.886      ;
; 4.592 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.208     ; 3.886      ;
; 4.595 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.211     ; 3.880      ;
; 4.595 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.211     ; 3.880      ;
; 4.597 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.217     ; 3.872      ;
; 4.597 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.217     ; 3.872      ;
; 4.598 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.222     ; 3.866      ;
; 4.598 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.222     ; 3.866      ;
; 4.600 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.218     ; 3.868      ;
; 4.600 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.218     ; 3.868      ;
; 4.650 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.182     ; 3.980      ;
; 4.650 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.182     ; 3.980      ;
; 4.775 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.183     ; 3.692      ;
; 4.775 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.183     ; 3.692      ;
; 4.776 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.183     ; 3.691      ;
; 4.776 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.183     ; 3.691      ;
; 4.807 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.240     ; 3.603      ;
; 4.807 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.237     ; 3.606      ;
; 4.807 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.237     ; 3.606      ;
; 4.808 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.244     ; 3.598      ;
; 4.812 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.221     ; 3.617      ;
; 4.812 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.221     ; 3.617      ;
; 4.813 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.230     ; 3.607      ;
; 4.813 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.230     ; 3.607      ;
; 4.814 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.235     ; 3.601      ;
; 4.814 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.235     ; 3.601      ;
; 4.814 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.231     ; 3.605      ;
; 4.814 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.231     ; 3.605      ;
; 5.096 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 3.544      ;
; 5.096 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 3.544      ;
; 5.096 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 3.544      ;
; 5.096 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 3.544      ;
; 5.096 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 3.544      ;
; 5.096 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.170     ; 3.546      ;
; 5.096 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.170     ; 3.546      ;
; 5.096 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 3.544      ;
; 5.096 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.170     ; 3.546      ;
; 5.096 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 3.544      ;
; 5.096 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 3.544      ;
; 5.096 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 3.544      ;
; 5.096 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 3.544      ;
; 5.096 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 3.544      ;
; 5.096 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 3.544      ;
; 5.096 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 3.544      ;
; 5.096 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.170     ; 3.546      ;
; 5.096 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 3.544      ;
; 5.096 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 3.544      ;
; 5.102 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.157     ; 3.553      ;
; 5.102 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.158     ; 3.552      ;
; 5.102 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.157     ; 3.553      ;
; 5.102 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.158     ; 3.552      ;
; 5.102 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.157     ; 3.553      ;
; 5.102 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.158     ; 3.552      ;
; 5.102 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.158     ; 3.552      ;
; 5.102 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.162     ; 3.548      ;
; 5.102 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.162     ; 3.548      ;
; 5.103 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.161     ; 3.548      ;
; 5.103 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.161     ; 3.548      ;
; 5.103 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.161     ; 3.548      ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                           ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 11.511 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[1]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 6.039      ;
; 11.520 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.064     ; 6.039      ;
; 11.520 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.064     ; 6.039      ;
; 11.587 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[1]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.158     ; 5.878      ;
; 11.596 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.149     ; 5.878      ;
; 11.596 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.149     ; 5.878      ;
; 11.632 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[1]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 5.918      ;
; 11.641 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.064     ; 5.918      ;
; 11.641 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.064     ; 5.918      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[1]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 5.618      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|clock_sync_reg                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[4]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|latch_delay_line:stimer_delay|shift_reg[2]                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|latch_delay_line:stimer_delay|shift_reg[1]                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|latch_delay_line:stimer_delay|shift_reg[0]                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[5]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audctl_reg[3]                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audctl_reg[5]                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audctl_reg[0]                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[2]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[3]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_clock_reg                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_control_reg[2]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 5.618      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_input_reg[4]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 5.618      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 5.615      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[6]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audctl_reg[4]                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[7]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[3]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|latch_delay_line:twotone_del|shift_reg[1]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|latch_delay_line:twotone_del|shift_reg[0]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audctl_reg[6]                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[3]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 5.625      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[0]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 5.625      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[0]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 5.625      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[1]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 5.625      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[1]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 5.625      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[2]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 5.625      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[2]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 5.625      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[3]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 5.625      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[4]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 5.625      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[4]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 5.625      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[5]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 5.625      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[6]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 5.625      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[6]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 5.625      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[7]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 5.625      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_reg[4]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 5.615      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_full_reg                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 5.625      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_active_reg                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 5.625      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[9]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 5.625      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serial_out_reg                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 5.625      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_clock_last_reg                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 5.625      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqen_reg[4]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 5.625      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[4]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 5.625      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 5.615      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_reg[5]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 5.615      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_input_reg[5]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 5.618      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[1]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 5.624      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[2]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 5.624      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[3]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 5.624      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[4]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 5.624      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[0]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.064     ; 5.629      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[0]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.064     ; 5.629      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[2]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.064     ; 5.629      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[4]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 5.622      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[5]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.064     ; 5.629      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[5]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.064     ; 5.629      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[6]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 5.622      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[6]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 5.622      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[7]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 5.622      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[7]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 5.622      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|consol_output_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.066     ; 5.627      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|consol_output_reg[0]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.066     ; 5.627      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|consol_output_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.066     ; 5.627      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf3_raw_reg[7]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 5.624      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf1_raw_reg[7]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 5.618      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf3_raw_reg[6]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 5.624      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm3_raw_reg[6]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 5.618      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf1_raw_reg[6]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 5.618      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf3_raw_reg[5]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 5.624      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf3_raw_reg[4]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 5.624      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm3_raw_reg[4]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 5.618      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf1_raw_reg[4]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 5.618      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm1_raw_reg[3]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.065     ; 5.628      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf1_raw_reg[3]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 5.618      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm3_raw_reg[3]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 5.618      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf3_raw_reg[2]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 5.624      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf1_raw_reg[2]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 5.618      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf3_raw_reg[1]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.066     ; 5.627      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf1_raw_reg[1]                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 5.618      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|consol_output_reg[3]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.064     ; 5.629      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|noise_4_reg[0]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audctl_reg[1]                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|noise_4_reg[1]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
; 11.930 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|noise_4_reg[2]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 5.626      ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'SPI_SCK'                                                                                                            ;
+--------+------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                    ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 14.873 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.693     ; 2.302      ;
; 14.873 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.693     ; 2.302      ;
; 14.873 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.693     ; 2.302      ;
; 14.873 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.693     ; 2.302      ;
; 14.873 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.693     ; 2.302      ;
; 14.873 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -3.693     ; 2.302      ;
+--------+------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'CLOCK_27[0]'                                                                                                                                                                                                                                ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                   ; Launch Clock                                                          ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.608 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.949      ; 3.655      ;
; -0.607 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.949      ; 3.656      ;
; -0.607 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.949      ; 3.656      ;
; -0.607 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.949      ; 3.656      ;
; -0.607 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.949      ; 3.656      ;
; -0.607 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.949      ; 3.656      ;
; -0.607 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.949      ; 3.656      ;
; -0.607 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.949      ; 3.656      ;
; -0.607 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.949      ; 3.656      ;
; -0.452 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.946      ; 3.808      ;
; -0.451 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.946      ; 3.809      ;
; -0.451 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.946      ; 3.809      ;
; -0.451 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.946      ; 3.809      ;
; -0.451 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.946      ; 3.809      ;
; -0.451 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.946      ; 3.809      ;
; -0.451 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.946      ; 3.809      ;
; -0.451 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.946      ; 3.809      ;
; -0.451 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.946      ; 3.809      ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.467 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|dffe4                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.382      ; 2.039      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a63 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a62 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a61 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a60 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a59 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a58 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a57 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a56 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a31 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a29 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a28 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a27 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a26 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a25 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a24 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.290      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a55 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a54 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a53 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a52 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a51 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a50 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a49 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a48 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a47 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a46 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a45 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a44 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a43 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a42 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a41 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a40 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a39 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a38 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a37 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a36 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a35 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a34 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a33 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a32 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a23 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a22 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a21 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a20 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a19 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a18 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a17 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a16 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 1.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 2.313      ;
; 2.498 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|request_sreg                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.657      ; 3.350      ;
; 2.874 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.594      ; 3.663      ;
; 2.876 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.587      ; 3.658      ;
; 2.900 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.569      ; 3.664      ;
; 2.900 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.569      ; 3.664      ;
; 2.917 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[10]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.547      ; 3.659      ;
; 2.917 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[14]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.547      ; 3.659      ;
; 2.945 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[3]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.514      ; 3.654      ;
; 2.945 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.514      ; 3.654      ;
; 2.945 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[7]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.514      ; 3.654      ;
; 2.948 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.673      ; 3.816      ;
; 2.950 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.666      ; 3.811      ;
; 2.951 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[19]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 3.317      ;
; 2.951 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[31]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 3.317      ;
; 2.951 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[24]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 3.317      ;
; 2.951 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[28]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 3.317      ;
; 2.951 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[21]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 3.317      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[0]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 3.324      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[1]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 3.324      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|enable_divider:enable_div|count_reg[2]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 3.324      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|enable_divider:enable_div|count_reg[3]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 3.324      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|enable_divider:enable_div|count_reg[4]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 3.324      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|enable_divider:enable_div|count_reg[5]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 3.324      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|enable_divider:enable_div|count_reg[6]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 3.324      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|enable_divider:enable_div|count_reg[7]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 3.324      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|enable_divider:enable_div|enabled_out_reg                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 3.324      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 3.324      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 3.324      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[4]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 3.324      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; enable_divider:enable_179_clock_div_zpu_pokey|enabled_out_reg                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 3.324      ;
; 2.956 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[23]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.166      ; 3.317      ;
; 2.956 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[29]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.166      ; 3.317      ;
; 2.956 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[17]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.166      ; 3.317      ;
; 2.956 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[20]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.166      ; 3.317      ;
; 2.956 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[25]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.166      ; 3.317      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                   ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 2.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.325      ;
; 2.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.325      ;
; 2.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.325      ;
; 2.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.325      ;
; 2.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.325      ;
; 2.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.325      ;
; 2.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.325      ;
; 2.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.325      ;
; 2.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.325      ;
; 2.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.325      ;
; 2.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.325      ;
; 2.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.325      ;
; 2.941 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cke_reg                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 3.336      ;
; 2.947 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.188      ; 3.349      ;
; 2.947 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.340      ;
; 2.947 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.340      ;
; 2.947 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.340      ;
; 2.947 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.340      ;
; 2.947 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.340      ;
; 2.947 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.340      ;
; 2.947 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.340      ;
; 2.947 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.340      ;
; 2.947 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.340      ;
; 2.947 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.340      ;
; 2.947 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.340      ;
; 2.949 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 3.317      ;
; 2.949 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 3.317      ;
; 2.949 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 3.317      ;
; 2.949 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 3.317      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.346      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.346      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 3.350      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 3.350      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 3.350      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 3.350      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.346      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.346      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.346      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.346      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.346      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.346      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.346      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.346      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.346      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.346      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.346      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.346      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.346      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.346      ;
; 2.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.344      ;
; 2.956 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 3.351      ;
; 2.956 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 3.351      ;
; 2.956 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 3.351      ;
; 2.962 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.344      ;
; 2.962 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.344      ;
; 2.962 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.344      ;
; 2.963 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.343      ;
; 2.963 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.343      ;
; 2.963 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.343      ;
; 2.963 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.343      ;
; 2.963 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.343      ;
; 2.963 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.345      ;
; 2.963 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.343      ;
; 2.963 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.343      ;
; 2.963 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.343      ;
; 2.963 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.343      ;
; 2.963 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.343      ;
; 2.963 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.343      ;
; 2.963 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.343      ;
; 2.963 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.343      ;
; 2.963 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.343      ;
; 2.963 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.343      ;
; 3.135 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.443      ;
; 3.135 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.443      ;
; 3.135 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.443      ;
; 3.135 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.442      ;
; 3.149 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.110      ; 3.407      ;
; 3.149 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.110      ; 3.407      ;
; 3.152 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.105      ; 3.405      ;
; 3.152 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.105      ; 3.405      ;
; 3.152 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.111      ; 3.411      ;
; 3.152 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.111      ; 3.411      ;
; 3.156 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.120      ; 3.424      ;
; 3.156 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.120      ; 3.424      ;
; 3.157 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 3.402      ;
; 3.158 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.101      ; 3.407      ;
; 3.159 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.104      ; 3.411      ;
; 3.159 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.104      ; 3.411      ;
; 3.338 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.708      ;
; 3.338 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.708      ;
; 3.457 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.124      ; 3.712      ;
; 3.457 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.124      ; 3.712      ;
; 3.457 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[7]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.131      ; 3.719      ;
; 3.457 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[8]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.131      ; 3.719      ;
; 3.458 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.119      ; 3.708      ;
; 3.458 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.119      ; 3.708      ;
; 3.458 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.134      ; 3.723      ;
; 3.458 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.134      ; 3.723      ;
; 3.458 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.125      ; 3.714      ;
; 3.458 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.125      ; 3.714      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'SPI_SCK'                                                                                                             ;
+--------+------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                    ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 19.144 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; -20.800      ; 3.572      ; 2.131      ;
; 19.144 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; -20.800      ; 3.572      ; 2.131      ;
; 19.144 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; -20.800      ; 3.572      ; 2.131      ;
; 19.144 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; -20.800      ; 3.572      ; 2.131      ;
; 19.144 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; -20.800      ; 3.572      ; 2.131      ;
; 19.144 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; -20.800      ; 3.572      ; 2.131      ;
+--------+------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                             ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cke_reg                      ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ;
; 4.100 ; 4.316        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ;
; 4.100 ; 4.316        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ;
; 4.100 ; 4.316        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|reply_reg                    ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[7]                  ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[8]                  ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]               ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[5]                  ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[6]                  ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[11]                 ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[4]                  ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|udqm_reg                     ;
; 4.209 ; 4.359        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[9]                  ;
; 4.210 ; 4.365        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                ;
; 4.210 ; 4.365        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                ;
; 4.211 ; 4.361        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[10]                 ;
; 4.211 ; 4.361        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[1]                  ;
; 4.211 ; 4.361        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[3]                  ;
; 4.211 ; 4.361        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ;
; 4.211 ; 4.361        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ;
; 4.211 ; 4.361        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                     ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 4.243 ; 4.369        ; 0.126          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.331 ; 4.440        ; 0.109          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.369 ; 4.369        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.440 ; 4.440        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                                                   ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                     ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                     ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                     ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                     ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                     ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                     ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                     ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                     ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                     ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                     ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                     ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                      ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                      ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                      ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                      ;
; 8.403 ; 8.785        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                      ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                     ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                     ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                     ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                     ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                     ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                     ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                     ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                     ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                     ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                     ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                     ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                      ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                      ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                      ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                      ;
; 8.441 ; 8.823        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                      ;
; 8.446 ; 8.662        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theOpcode[7]                                                 ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[4]                                                         ;
; 8.449 ; 8.665        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[4]                                                         ;
; 8.449 ; 8.665        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[5]                                                         ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[3]                                                         ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Nreg                                                         ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[1]                                                         ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[4]                                                         ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                                                         ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Zreg                                                         ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]                                                  ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]                                                  ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[34]                                                  ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[43]                                                  ;
; 8.451 ; 8.667        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[6]                                                         ;
; 8.451 ; 8.667        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[15]                                                  ;
; 8.451 ; 8.667        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19]                                                  ;
; 8.451 ; 8.667        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]                                                  ;
; 8.451 ; 8.667        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28]                                                  ;
; 8.451 ; 8.667        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                                  ;
; 8.451 ; 8.667        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                                  ;
; 8.451 ; 8.667        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[3]                                                   ;
; 8.451 ; 8.667        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                   ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[1]                                                         ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[2]                                                         ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[3]                                                         ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[6]                                                         ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[0]                                                         ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[1]                                                         ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[2]                                                         ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[3]                                                         ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[4]                                                         ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[6]                                                         ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[7]                                                         ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[6]                                                         ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[2]                                                         ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[3]                                                         ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[5]                                                         ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[5]                                                         ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|ram_bank[12]                                           ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                                                         ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[1]                                                         ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[2]                                                         ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[7]                                                         ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[0]                                                         ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[7]                                                         ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|irqActive                                                    ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[16]                                                  ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[21]                                                  ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26]                                                  ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[33]                                                  ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theOpcode[6]                                                 ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|break_irq_reg       ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|break_pressed_reg   ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|control_pressed_reg ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|shift_pressed_reg   ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                                                                                                       ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                                                                                                       ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                           ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                ; Clock Edge ; Target                                                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; 16.279 ; 16.279       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.279 ; 16.279       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.282 ; 16.282       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.295 ; 16.295       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.295 ; 16.295       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.295 ; 16.295       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.295 ; 16.295       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 16.295 ; 16.295       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.334 ; 16.334       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.334 ; 16.334       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.334 ; 16.334       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.334 ; 16.334       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 16.334 ; 16.334       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.348 ; 16.348       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.351 ; 16.351       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.351 ; 16.351       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'SPI_SCK'                                                                         ;
+--------+--------------+----------------+------------------+---------+------------+------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                   ;
+--------+--------------+----------------+------------------+---------+------------+------------------------------------------+
; 16.988 ; 17.204       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|sd_dout[2]            ;
; 16.988 ; 17.204       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|sd_dout[5]            ;
; 16.988 ; 17.204       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|sd_dout[7]            ;
; 16.988 ; 17.204       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|status[0]             ;
; 16.989 ; 17.205       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~10           ;
; 16.989 ; 17.205       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~11           ;
; 16.989 ; 17.205       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~12           ;
; 16.989 ; 17.205       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~13           ;
; 16.989 ; 17.205       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~14           ;
; 16.989 ; 17.205       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~15           ;
; 16.989 ; 17.205       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~16           ;
; 16.989 ; 17.205       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~17           ;
; 16.989 ; 17.205       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~18           ;
; 16.989 ; 17.205       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~19           ;
; 16.989 ; 17.205       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~20           ;
; 16.989 ; 17.205       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~21           ;
; 16.989 ; 17.205       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~22           ;
; 16.989 ; 17.205       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~23           ;
; 16.989 ; 17.205       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~8            ;
; 16.989 ; 17.205       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~9            ;
; 16.989 ; 17.205       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_wptr[0]           ;
; 16.989 ; 17.205       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_wptr[1]           ;
; 16.989 ; 17.205       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_wptr[2]           ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[10] ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[11] ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[12] ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[13] ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[14] ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[15] ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[8]  ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[9]  ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~0            ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~1            ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~2            ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~24           ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~25           ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~26           ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~27           ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~28           ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~29           ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~3            ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~30           ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~31           ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~4            ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~5            ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~6            ;
; 16.990 ; 17.206       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~7            ;
; 16.991 ; 17.207       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[2]                ;
; 16.991 ; 17.207       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[3]                ;
; 16.991 ; 17.207       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[4]                ;
; 16.991 ; 17.207       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[5]                ;
; 16.991 ; 17.207       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[6]                ;
; 16.991 ; 17.207       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[7]                ;
; 16.991 ; 17.207       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[10] ;
; 16.991 ; 17.207       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[11] ;
; 16.991 ; 17.207       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[12] ;
; 16.991 ; 17.207       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[13] ;
; 16.991 ; 17.207       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[14] ;
; 16.991 ; 17.207       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[15] ;
; 16.991 ; 17.207       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[8]  ;
; 16.991 ; 17.207       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[9]  ;
; 16.991 ; 17.207       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|sd_dout[1]            ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|but_sw[0]             ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|but_sw[1]             ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_1[0]         ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_1[1]         ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_1[2]         ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_1[3]         ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_1[4]         ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_1[5]         ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[0]  ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[1]  ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[2]  ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[3]  ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[4]  ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[5]  ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[6]  ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[7]  ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[0]  ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[1]  ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[2]  ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[3]  ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[4]  ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[5]  ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[6]  ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[7]  ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[0]               ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[1]               ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[2]               ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[3]               ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[4]               ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[5]               ;
; 16.992 ; 17.208       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[6]               ;
; 16.993 ; 17.209       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[0]                ;
; 16.993 ; 17.209       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[1]                ;
; 16.993 ; 17.209       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_0[0]         ;
; 16.993 ; 17.209       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_0[1]         ;
; 16.993 ; 17.209       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_0[2]         ;
; 16.993 ; 17.209       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_0[3]         ;
; 16.993 ; 17.209       ; 0.216          ; High Pulse Width ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_0[4]         ;
+--------+--------------+----------------+------------------+---------+------------+------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_27[0]'                                                                                                               ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock       ; Clock Edge ; Target                                                                         ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+
; 18.273 ; 18.457       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.273 ; 18.457       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.273 ; 18.457       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.273 ; 18.457       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.273 ; 18.457       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.273 ; 18.457       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.273 ; 18.457       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.273 ; 18.457       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.273 ; 18.457       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.344 ; 18.344       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.344 ; 18.344       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 18.351 ; 18.351       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.351 ; 18.351       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.359 ; 18.575       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.400 ; 18.400       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.406 ; 18.406       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.406 ; 18.406       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.406 ; 18.406       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.406 ; 18.406       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.406 ; 18.406       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.406 ; 18.406       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.406 ; 18.406       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.406 ; 18.406       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.406 ; 18.406       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.423 ; 18.423       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.430 ; 18.430       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.606 ; 18.606       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.613 ; 18.613       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.629 ; 18.629       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.633 ; 18.633       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.633 ; 18.633       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.637 ; 18.637       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.684 ; 18.684       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.684 ; 18.684       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.691 ; 18.691       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.691 ; 18.691       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 33.037 ; 37.037       ; 4.000          ; Port Rate        ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]                                                                    ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                            ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                                                                                                                      ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 40.596 ; 41.606       ; 1.010          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ;
; 40.713 ; 41.723       ; 1.010          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                      ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                      ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                      ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                      ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                      ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                      ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                      ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                      ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                      ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                      ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                      ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                      ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                      ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                 ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                            ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                                    ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                        ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                        ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                       ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                      ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                      ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                       ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                       ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                       ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                       ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                       ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                       ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                       ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                       ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                       ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                        ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_ena_state                                                                  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_ena_state                                                                  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_ena_state                                                                  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_ena_state                                                                  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                           ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate_state                                                            ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0]                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5]                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0]                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                       ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_ena_state                                                        ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|tmp_seq_ena_state                                                             ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_ena_state                                                  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_ena_state                                                  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_ena_state                                                  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_ena_state                                                  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate2_state                                           ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate_state                                            ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0] ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6] ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4] ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0] ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1] ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2] ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                         ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack     ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ;
; 44052.658 ; 44052.784    ; 0.126          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ;
; 44052.744 ; 44052.853    ; 0.109          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_kbd_data|clk                                                                                                           ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_parity|clk                                                                                                             ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_r_inc|clk                                                                                                              ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[0]|clk                                                                                                            ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[1]|clk                                                                                                            ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[2]|clk                                                                                                            ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[0]|clk                                                                                                         ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[1]|clk                                                                                                         ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[2]|clk                                                                                                         ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[3]|clk                                                                                                         ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[4]|clk                                                                                                         ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[5]|clk                                                                                                         ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[6]|clk                                                                                                         ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[7]|clk                                                                                                         ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[0]|clk                                                                                                        ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[1]|clk                                                                                                        ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[2]|clk                                                                                                        ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[3]|clk                                                                                                        ;
; 44052.784 ; 44052.784    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 44052.784 ; 44052.784    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 44052.853 ; 44052.853    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 44052.853 ; 44052.853    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_kbd_data|clk                                                                                                           ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_parity|clk                                                                                                             ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_r_inc|clk                                                                                                              ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[0]|clk                                                                                                            ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[1]|clk                                                                                                            ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[2]|clk                                                                                                            ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[0]|clk                                                                                                         ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[1]|clk                                                                                                         ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[2]|clk                                                                                                         ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[3]|clk                                                                                                         ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[4]|clk                                                                                                         ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[5]|clk                                                                                                         ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[6]|clk                                                                                                         ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[7]|clk                                                                                                         ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[0]|clk                                                                                                        ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[1]|clk                                                                                                        ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[2]|clk                                                                                                        ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[3]|clk                                                                                                        ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                      ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK     ; 3.470 ; 4.466 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK     ; 3.818 ; 4.734 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.637 ; 2.750 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.632 ; 2.745 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.636 ; 2.749 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.637 ; 2.750 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.637 ; 2.750 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.581 ; 2.698 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.591 ; 2.708 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.581 ; 2.698 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.581 ; 2.698 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.619 ; 2.732 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.619 ; 2.732 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.613 ; 2.726 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.613 ; 2.726 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.622 ; 2.735 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.622 ; 2.735 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.633 ; 2.746 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.633 ; 2.746 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                         ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK     ; 5.590  ; 5.476  ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK     ; 8.973  ; 8.667  ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; -1.685 ; -1.803 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; -1.738 ; -1.852 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; -1.742 ; -1.856 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; -1.744 ; -1.858 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; -1.744 ; -1.858 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; -1.685 ; -1.803 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; -1.695 ; -1.813 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; -1.685 ; -1.803 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; -1.686 ; -1.804 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; -1.725 ; -1.839 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; -1.725 ; -1.839 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; -1.719 ; -1.833 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; -1.719 ; -1.833 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; -1.728 ; -1.842 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; -1.728 ; -1.842 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; -1.739 ; -1.853 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; -1.739 ; -1.853 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                              ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK     ; 17.087 ; 16.439 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; CLOCK_27[0] ; 2.751  ; 2.413  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 2.526  ; 2.239  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 2.528  ; 2.241  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 2.528  ; 2.241  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 2.539  ; 2.252  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 2.450  ; 2.189  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 2.751  ; 2.413  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 2.735  ; 2.397  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 2.740  ; 2.402  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 2.740  ; 2.402  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 2.736  ; 2.398  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 2.527  ; 2.240  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 2.743  ; 2.405  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 2.526  ; 2.239  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 2.526  ; 2.239  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 2.517  ; 2.230  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 2.787  ; 2.520  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.743  ; 2.405  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.724  ; 2.386  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.720  ; 2.382  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.435  ; 2.174  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.435  ; 2.174  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.540  ; 2.253  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.550  ; 2.263  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.540  ; 2.253  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.539  ; 2.252  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.717  ; 2.379  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.717  ; 2.379  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.743  ; 2.405  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.743  ; 2.405  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.431  ; 2.170  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.734  ; 2.396  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.743  ; 2.405  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.440  ; 2.179  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 2.716  ; 2.378  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 2.539  ; 2.252  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 2.526  ; 2.239  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 2.526  ; 2.239  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 2.539  ; 2.252  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 8.921  ; 7.888  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 6.313  ; 5.631  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 5.728  ; 6.526  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 26.890 ; 26.124 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 26.466 ; 25.736 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 26.890 ; 26.124 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 26.471 ; 25.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 23.709 ; 23.302 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 25.327 ; 24.763 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 25.541 ; 24.815 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 23.341 ; 22.469 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 22.790 ; 22.119 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 23.341 ; 22.469 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 23.220 ; 22.418 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 21.878 ; 21.263 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 22.501 ; 21.498 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 17.941 ; 17.196 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 6.008  ; 5.275  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 27.428 ; 26.696 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 26.815 ; 26.119 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 27.428 ; 26.696 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 26.750 ; 26.117 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 24.961 ; 24.324 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 25.740 ; 25.284 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 25.510 ; 24.661 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 5.620  ; 4.925  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -0.556 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -0.944 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                      ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK     ; 13.313 ; 12.672 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; CLOCK_27[0] ; 1.724  ; 1.464  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 1.799  ; 1.513  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 1.800  ; 1.514  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 1.801  ; 1.515  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 1.811  ; 1.525  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 1.724  ; 1.464  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 2.025  ; 1.688  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 2.009  ; 1.672  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 2.014  ; 1.677  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 2.014  ; 1.677  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 2.010  ; 1.673  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 1.800  ; 1.514  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 2.017  ; 1.680  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 1.790  ; 1.504  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 1.798  ; 1.512  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 1.790  ; 1.504  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 2.054  ; 1.787  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.705  ; 1.445  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.998  ; 1.661  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.994  ; 1.657  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.710  ; 1.450  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.710  ; 1.450  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.812  ; 1.526  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.822  ; 1.536  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.812  ; 1.526  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.812  ; 1.526  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.991  ; 1.654  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.991  ; 1.654  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.017  ; 1.680  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.017  ; 1.680  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.705  ; 1.445  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.008  ; 1.671  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.017  ; 1.680  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.714  ; 1.454  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 1.991  ; 1.654  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 1.811  ; 1.525  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 1.799  ; 1.513  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 1.798  ; 1.512  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 1.811  ; 1.525  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 8.019  ; 7.008  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 5.514  ; 4.841  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 4.934  ; 5.719  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 5.084  ; 4.432  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 5.908  ; 5.240  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 5.988  ; 5.195  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 5.788  ; 5.285  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 5.607  ; 5.179  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 5.084  ; 4.432  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 5.616  ; 5.070  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 5.431  ; 4.809  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 5.431  ; 4.809  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 6.246  ; 5.361  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 5.893  ; 5.258  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 6.003  ; 5.405  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 6.033  ; 5.404  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 6.171  ; 5.539  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 5.222  ; 4.500  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 5.246  ; 4.681  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 5.762  ; 5.297  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 5.246  ; 4.681  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 5.801  ; 5.258  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 6.150  ; 5.480  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 6.073  ; 5.289  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 5.848  ; 5.136  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 4.850  ; 4.164  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -1.242 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -1.626 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+----------------------------------------------------------+
; Propagation Delay                                        ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 8.396 ; 8.325 ; 8.771 ; 8.771 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------+
; Minimum Propagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 7.996 ; 7.860 ; 8.204 ; 8.204 ;
+------------+-------------+-------+-------+-------+-------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK     ; 15.797 ; 15.797 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.528  ; 2.528  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.535  ; 2.535  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.531  ; 2.531  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.549  ; 2.549  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.549  ; 2.549  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.636  ; 2.636  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.646  ; 2.646  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.636  ; 2.636  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.635  ; 2.635  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.528  ; 2.528  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.528  ; 2.528  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.554  ; 2.554  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.554  ; 2.554  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.545  ; 2.545  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.545  ; 2.545  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.554  ; 2.554  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.554  ; 2.554  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                        ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK     ; 11.683 ; 11.683 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.280  ; 1.314  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.287  ; 1.321  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.283  ; 1.317  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.302  ; 1.336  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.302  ; 1.336  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.353  ; 1.386  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.363  ; 1.396  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.353  ; 1.386  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.353  ; 1.386  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.280  ; 1.314  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.280  ; 1.314  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.306  ; 1.340  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.306  ; 1.340  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.297  ; 1.331  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.297  ; 1.331  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.306  ; 1.340  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.306  ; 1.340  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                     ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK     ; 15.341    ; 15.412    ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.207     ; 2.604     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.214     ; 2.611     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.210     ; 2.607     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.228     ; 2.625     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.228     ; 2.625     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.291     ; 2.712     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.301     ; 2.722     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.291     ; 2.712     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.290     ; 2.711     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.207     ; 2.604     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.207     ; 2.604     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.233     ; 2.630     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.233     ; 2.630     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.224     ; 2.621     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.224     ; 2.621     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.233     ; 2.630     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.233     ; 2.630     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                             ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK     ; 11.313    ; 11.449    ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.353     ; 1.353     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.360     ; 1.360     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.356     ; 1.356     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.375     ; 1.375     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.375     ; 1.375     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.426     ; 1.426     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.436     ; 1.436     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.426     ; 1.426     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.426     ; 1.426     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.353     ; 1.353     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.353     ; 1.353     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.379     ; 1.379     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.379     ; 1.379     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.370     ; 1.370     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.370     ; 1.370     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.379     ; 1.379     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.379     ; 1.379     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                              ;
+-----------------------------------------------------------------------+---------+---------------+
; Clock                                                                 ; Slack   ; End Point TNS ;
+-----------------------------------------------------------------------+---------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -10.797 ; -1499.814     ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; -7.317  ; -86.005       ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 0.064   ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0.394   ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.831   ; 0.000         ;
; SPI_SCK                                                               ; 15.998  ; 0.000         ;
; CLOCK_27[0]                                                           ; 35.237  ; 0.000         ;
+-----------------------------------------------------------------------+---------+---------------+


+------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                              ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; -0.876 ; -0.876        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.102  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.186  ; 0.000         ;
; CLOCK_27[0]                                                           ; 0.187  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.187  ; 0.000         ;
; SPI_SCK                                                               ; 0.285  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 8.103  ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                                          ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; CLOCK_27[0]                                                           ; -0.258 ; -2.314        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 6.571  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 14.527 ; 0.000         ;
; SPI_SCK                                                               ; 18.740 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                                           ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; CLOCK_27[0]                                                           ; -0.521 ; -4.681        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.686  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.492  ; 0.000         ;
; SPI_SCK                                                               ; 19.386 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                                  ;
+-----------------------------------------------------------------------+-----------+---------------+
; Clock                                                                 ; Slack     ; End Point TNS ;
+-----------------------------------------------------------------------+-----------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.186     ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 4.331     ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.558     ; 0.000         ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 16.300    ; 0.000         ;
; CLOCK_27[0]                                                           ; 17.785    ; 0.000         ;
; SPI_SCK                                                               ; 18.317    ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 40.631    ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 44052.599 ; 0.000         ;
+-----------------------------------------------------------------------+-----------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                  ;
+---------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                        ; To Node                                                                                                                 ; Launch Clock ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -10.797 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.958     ; 4.747      ;
; -10.765 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.958     ; 4.715      ;
; -10.728 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.958     ; 4.678      ;
; -10.719 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.674      ;
; -10.718 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.670      ;
; -10.706 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.958     ; 4.656      ;
; -10.701 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.653      ;
; -10.696 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.958     ; 4.646      ;
; -10.681 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.958     ; 4.631      ;
; -10.674 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.958     ; 4.624      ;
; -10.663 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.958     ; 4.613      ;
; -10.653 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.958     ; 4.603      ;
; -10.650 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.605      ;
; -10.649 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.601      ;
; -10.649 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.958     ; 4.599      ;
; -10.642 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.766     ; 4.784      ;
; -10.632 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.584      ;
; -10.631 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.958     ; 4.581      ;
; -10.629 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.581      ;
; -10.629 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.959     ; 4.578      ;
; -10.628 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.583      ;
; -10.627 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.579      ;
; -10.622 ; user_io:my_user_io|joystick_1[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.766     ; 4.764      ;
; -10.621 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.958     ; 4.571      ;
; -10.616 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.571      ;
; -10.615 ; user_io:my_user_io|joystick_1[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.766     ; 4.757      ;
; -10.610 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.562      ;
; -10.603 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.558      ;
; -10.602 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.554      ;
; -10.600 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.958     ; 4.550      ;
; -10.585 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.540      ;
; -10.585 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.537      ;
; -10.584 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.536      ;
; -10.575 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.530      ;
; -10.574 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.526      ;
; -10.573 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.766     ; 4.715      ;
; -10.568 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.958     ; 4.518      ;
; -10.567 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.519      ;
; -10.561 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[22]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.516      ;
; -10.560 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.512      ;
; -10.560 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.959     ; 4.509      ;
; -10.557 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.509      ;
; -10.553 ; user_io:my_user_io|joystick_1[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.766     ; 4.695      ;
; -10.551 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.766     ; 4.693      ;
; -10.547 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.502      ;
; -10.546 ; user_io:my_user_io|joystick_1[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.766     ; 4.688      ;
; -10.538 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.490      ;
; -10.538 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.959     ; 4.487      ;
; -10.531 ; user_io:my_user_io|joystick_1[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.766     ; 4.673      ;
; -10.526 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.766     ; 4.668      ;
; -10.525 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.480      ;
; -10.524 ; user_io:my_user_io|joystick_1[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.766     ; 4.666      ;
; -10.522 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.477      ;
; -10.521 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.473      ;
; -10.518 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[20]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.470      ;
; -10.513 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.465      ;
; -10.513 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.959     ; 4.462      ;
; -10.508 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.766     ; 4.650      ;
; -10.504 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.456      ;
; -10.500 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.455      ;
; -10.498 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.766     ; 4.640      ;
; -10.495 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.447      ;
; -10.495 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.959     ; 4.444      ;
; -10.492 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[22]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.447      ;
; -10.488 ; user_io:my_user_io|joystick_1[5] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.766     ; 4.630      ;
; -10.486 ; user_io:my_user_io|joystick_1[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.759     ; 4.635      ;
; -10.485 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.437      ;
; -10.485 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.959     ; 4.434      ;
; -10.482 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.437      ;
; -10.481 ; user_io:my_user_io|joystick_1[5] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.766     ; 4.623      ;
; -10.478 ; user_io:my_user_io|joystick_1[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.766     ; 4.620      ;
; -10.477 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[21]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.432      ;
; -10.472 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.427      ;
; -10.471 ; user_io:my_user_io|joystick_1[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.766     ; 4.613      ;
; -10.470 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[22]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.425      ;
; -10.469 ; user_io:my_user_io|joystick_1[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.767     ; 4.610      ;
; -10.466 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                         ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.752     ; 4.622      ;
; -10.463 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[18]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.959     ; 4.412      ;
; -10.449 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[20]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.401      ;
; -10.445 ; user_io:my_user_io|joystick_1[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.766     ; 4.587      ;
; -10.445 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.766     ; 4.587      ;
; -10.445 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[22]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.400      ;
; -10.432 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.384      ;
; -10.432 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.959     ; 4.381      ;
; -10.427 ; user_io:my_user_io|joystick_1[5] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[22]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.382      ;
; -10.427 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[20]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.379      ;
; -10.426 ; user_io:my_user_io|joystick_1[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.759     ; 4.575      ;
; -10.425 ; user_io:my_user_io|joystick_1[3] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.766     ; 4.567      ;
; -10.419 ; user_io:my_user_io|joystick_1[3] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.374      ;
; -10.418 ; user_io:my_user_io|joystick_1[3] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.766     ; 4.560      ;
; -10.417 ; user_io:my_user_io|joystick_1[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[22]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.372      ;
; -10.417 ; user_io:my_user_io|joystick_1[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.759     ; 4.566      ;
; -10.408 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[21]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.363      ;
; -10.404 ; user_io:my_user_io|joystick_1[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.767     ; 4.545      ;
; -10.402 ; user_io:my_user_io|joystick_1[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[16]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.954     ; 4.356      ;
; -10.402 ; user_io:my_user_io|but_sw[0]     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[20]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.956     ; 4.354      ;
; -10.397 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                         ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.752     ; 4.553      ;
; -10.395 ; user_io:my_user_io|joystick_1[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.759     ; 4.544      ;
; -10.394 ; user_io:my_user_io|joystick_1[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[18]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.959     ; 4.343      ;
; -10.386 ; user_io:my_user_io|joystick_1[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[21]                                                           ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; -5.953     ; 4.341      ;
+---------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                          ;
+--------+--------------------------------+------------------------------------+--------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                      ; To Node                            ; Launch Clock ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------+------------------------------------+--------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -7.317 ; user_io:my_user_io|ps2_fifo~54 ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.953     ; 1.272      ;
; -7.268 ; user_io:my_user_io|ps2_fifo~53 ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.953     ; 1.223      ;
; -7.264 ; user_io:my_user_io|ps2_fifo~45 ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.953     ; 1.219      ;
; -7.262 ; user_io:my_user_io|ps2_fifo~47 ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.953     ; 1.217      ;
; -7.256 ; user_io:my_user_io|ps2_fifo~46 ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.953     ; 1.211      ;
; -7.252 ; user_io:my_user_io|ps2_fifo~42 ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.953     ; 1.207      ;
; -7.252 ; user_io:my_user_io|ps2_fifo~55 ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.953     ; 1.207      ;
; -7.238 ; user_io:my_user_io|ps2_fifo~50 ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.953     ; 1.193      ;
; -7.226 ; user_io:my_user_io|ps2_fifo~9  ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 1.188      ;
; -7.222 ; user_io:my_user_io|ps2_fifo~38 ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.954     ; 1.176      ;
; -7.210 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.171      ;
; -7.210 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.171      ;
; -7.210 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.171      ;
; -7.210 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.171      ;
; -7.210 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.171      ;
; -7.210 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.171      ;
; -7.210 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.171      ;
; -7.210 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_parity      ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.171      ;
; -7.177 ; user_io:my_user_io|ps2_fifo~49 ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.954     ; 1.131      ;
; -7.176 ; user_io:my_user_io|ps2_fifo~12 ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 1.138      ;
; -7.170 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.131      ;
; -7.170 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.131      ;
; -7.170 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.131      ;
; -7.170 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.131      ;
; -7.170 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.131      ;
; -7.170 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.131      ;
; -7.170 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.131      ;
; -7.170 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_parity      ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.131      ;
; -7.161 ; user_io:my_user_io|ps2_fifo~37 ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.954     ; 1.115      ;
; -7.155 ; user_io:my_user_io|ps2_fifo~39 ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.954     ; 1.109      ;
; -7.147 ; user_io:my_user_io|ps2_fifo~15 ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 1.109      ;
; -7.144 ; user_io:my_user_io|ps2_fifo~34 ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.954     ; 1.098      ;
; -7.142 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.103      ;
; -7.142 ; user_io:my_user_io|ps2_fifo~23 ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 1.104      ;
; -7.111 ; user_io:my_user_io|ps2_fifo~51 ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.954     ; 1.065      ;
; -7.108 ; user_io:my_user_io|ps2_fifo~41 ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.954     ; 1.062      ;
; -7.101 ; user_io:my_user_io|ps2_fifo~48 ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.953     ; 1.056      ;
; -7.100 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.061      ;
; -7.100 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.061      ;
; -7.100 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.061      ;
; -7.100 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.061      ;
; -7.100 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.061      ;
; -7.100 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.061      ;
; -7.100 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.061      ;
; -7.100 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_parity      ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.061      ;
; -7.094 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.055      ;
; -7.094 ; user_io:my_user_io|ps2_fifo~43 ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.954     ; 1.048      ;
; -7.090 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_tx_state[0] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.051      ;
; -7.090 ; user_io:my_user_io|ps2_fifo~40 ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.953     ; 1.045      ;
; -7.077 ; user_io:my_user_io|ps2_fifo~8  ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 1.039      ;
; -7.074 ; user_io:my_user_io|ps2_fifo~33 ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.954     ; 1.028      ;
; -7.074 ; user_io:my_user_io|ps2_fifo~19 ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 1.036      ;
; -7.073 ; user_io:my_user_io|ps2_fifo~16 ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 1.035      ;
; -7.072 ; user_io:my_user_io|ps2_fifo~11 ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 1.034      ;
; -7.069 ; user_io:my_user_io|ps2_fifo~20 ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 1.031      ;
; -7.068 ; user_io:my_user_io|ps2_fifo~52 ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.953     ; 1.023      ;
; -7.067 ; user_io:my_user_io|ps2_fifo~17 ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 1.029      ;
; -7.066 ; user_io:my_user_io|ps2_fifo~44 ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.953     ; 1.021      ;
; -7.048 ; user_io:my_user_io|ps2_fifo~7  ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 1.010      ;
; -7.042 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.003      ;
; -7.042 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_tx_state[0] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 1.003      ;
; -7.027 ; user_io:my_user_io|ps2_fifo~14 ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 0.989      ;
; -7.025 ; user_io:my_user_io|ps2_fifo~22 ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 0.987      ;
; -7.023 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_kbd_data    ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 0.984      ;
; -6.993 ; user_io:my_user_io|ps2_fifo~32 ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.954     ; 0.947      ;
; -6.992 ; user_io:my_user_io|ps2_fifo~35 ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.954     ; 0.946      ;
; -6.990 ; user_io:my_user_io|ps2_fifo~10 ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 0.952      ;
; -6.989 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_tx_state[0] ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 0.950      ;
; -6.987 ; user_io:my_user_io|ps2_fifo~61 ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.954     ; 0.941      ;
; -6.984 ; user_io:my_user_io|ps2_fifo~63 ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.954     ; 0.938      ;
; -6.980 ; user_io:my_user_io|ps2_fifo~13 ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 0.942      ;
; -6.978 ; user_io:my_user_io|ps2_fifo~0  ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 0.940      ;
; -6.977 ; user_io:my_user_io|ps2_fifo~3  ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 0.939      ;
; -6.974 ; user_io:my_user_io|ps2_fifo~62 ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.954     ; 0.928      ;
; -6.974 ; user_io:my_user_io|ps2_fifo~58 ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.954     ; 0.928      ;
; -6.973 ; user_io:my_user_io|ps2_fifo~36 ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.954     ; 0.927      ;
; -6.965 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_kbd_data    ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 0.926      ;
; -6.959 ; user_io:my_user_io|ps2_fifo~1  ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 0.921      ;
; -6.959 ; user_io:my_user_io|ps2_fifo~4  ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 0.921      ;
; -6.953 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_kbd_data    ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 0.914      ;
; -6.916 ; user_io:my_user_io|ps2_fifo~6  ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 0.878      ;
; -6.914 ; user_io:my_user_io|ps2_fifo~18 ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 0.876      ;
; -6.913 ; user_io:my_user_io|ps2_fifo~21 ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 0.875      ;
; -6.883 ; user_io:my_user_io|ps2_fifo~2  ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 0.845      ;
; -6.883 ; user_io:my_user_io|ps2_fifo~5  ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 0.845      ;
; -6.875 ; user_io:my_user_io|ps2_fifo~31 ; user_io:my_user_io|ps2_tx_byte[7]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 0.837      ;
; -6.823 ; user_io:my_user_io|ps2_fifo~57 ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.954     ; 0.777      ;
; -6.823 ; user_io:my_user_io|ps2_fifo~56 ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.954     ; 0.777      ;
; -6.822 ; user_io:my_user_io|ps2_fifo~59 ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.954     ; 0.776      ;
; -6.809 ; user_io:my_user_io|ps2_fifo~24 ; user_io:my_user_io|ps2_tx_byte[0]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 0.771      ;
; -6.806 ; user_io:my_user_io|ps2_fifo~27 ; user_io:my_user_io|ps2_tx_byte[3]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 0.768      ;
; -6.802 ; user_io:my_user_io|ps2_fifo~60 ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.954     ; 0.756      ;
; -6.788 ; user_io:my_user_io|ps2_fifo~28 ; user_io:my_user_io|ps2_tx_byte[4]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 0.750      ;
; -6.786 ; user_io:my_user_io|ps2_fifo~25 ; user_io:my_user_io|ps2_tx_byte[1]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 0.748      ;
; -6.744 ; user_io:my_user_io|ps2_fifo~30 ; user_io:my_user_io|ps2_tx_byte[6]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 0.706      ;
; -6.727 ; user_io:my_user_io|ps2_wptr[0] ; user_io:my_user_io|ps2_r_inc       ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 0.688      ;
; -6.662 ; user_io:my_user_io|ps2_wptr[1] ; user_io:my_user_io|ps2_r_inc       ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 0.623      ;
; -6.634 ; user_io:my_user_io|ps2_fifo~26 ; user_io:my_user_io|ps2_tx_byte[2]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 0.596      ;
; -6.633 ; user_io:my_user_io|ps2_fifo~29 ; user_io:my_user_io|ps2_tx_byte[5]  ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.946     ; 0.595      ;
; -6.630 ; user_io:my_user_io|ps2_wptr[2] ; user_io:my_user_io|ps2_r_inc       ; SPI_SCK      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.001        ; -5.947     ; 0.591      ;
+--------+--------------------------------+------------------------------------+--------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                                                     ; Launch Clock                                                          ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.064  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.371        ; 0.643      ; 0.777      ;
; 39.005 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.330     ; 3.517      ;
; 39.247 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|altsyncram:altsyncram4|altsyncram_cul3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.329     ; 3.276      ;
; 39.731 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.150     ; 2.971      ;
; 39.755 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.147     ; 2.950      ;
; 39.761 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.147     ; 2.944      ;
; 39.777 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.145     ; 2.930      ;
; 39.784 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.145     ; 2.923      ;
; 39.854 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.147     ; 2.851      ;
; 39.862 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                                               ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.145     ; 2.845      ;
; 39.884 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.145     ; 2.823      ;
; 39.905 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.147     ; 2.800      ;
; 39.933 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.145     ; 2.774      ;
; 40.095 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.967      ; 3.526      ;
; 40.111 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.145     ; 2.596      ;
; 40.207 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.147     ; 2.498      ;
; 40.244 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.145     ; 2.463      ;
; 40.245 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.967      ; 3.376      ;
; 40.252 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.965      ; 3.367      ;
; 40.260 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.967      ; 3.361      ;
; 40.264 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.144     ; 2.444      ;
; 40.270 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.144     ; 2.438      ;
; 40.296 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.965      ; 3.323      ;
; 40.306 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.965      ; 3.313      ;
; 40.349 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.144     ; 2.359      ;
; 40.369 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.148     ; 2.335      ;
; 40.371 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                                               ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.148     ; 2.333      ;
; 40.421 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.144     ; 2.287      ;
; 40.444 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.148     ; 2.260      ;
; 40.450 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.981      ; 3.185      ;
; 40.484 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.144     ; 2.224      ;
; 40.529 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.148     ; 2.175      ;
; 40.595 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.148     ; 2.109      ;
; 40.598 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.147     ; 2.107      ;
; 40.602 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.148     ; 2.102      ;
; 41.193 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate2_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate3_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.019     ; 0.441      ;
; 41.196 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate3_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.019     ; 0.438      ;
; 78.949 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.021     ; 5.549      ;
; 79.024 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.049     ; 4.247      ;
; 79.178 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.051     ; 4.091      ;
; 79.195 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.049     ; 4.076      ;
; 79.208 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.049     ; 4.063      ;
; 79.242 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.051     ; 4.027      ;
; 79.271 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.051     ; 3.998      ;
; 79.415 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.035     ; 3.870      ;
; 79.457 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.041     ; 3.822      ;
; 79.566 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.041     ; 3.713      ;
; 79.614 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.041     ; 3.665      ;
; 79.706 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.041     ; 3.573      ;
; 79.748 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 3.538      ;
; 79.887 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.397      ;
; 79.898 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 3.388      ;
; 79.905 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.379      ;
; 79.913 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 3.373      ;
; 79.949 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.335      ;
; 79.959 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.325      ;
; 79.981 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.061     ; 3.278      ;
; 80.037 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.247      ;
; 80.042 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.038     ; 3.240      ;
; 80.052 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.232      ;
; 80.088 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.038     ; 3.194      ;
; 80.093 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.030     ; 3.197      ;
; 80.098 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.038     ; 3.184      ;
; 80.131 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.061     ; 3.128      ;
; 80.138 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.063     ; 3.119      ;
; 80.146 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.061     ; 3.113      ;
; 80.182 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.063     ; 3.075      ;
; 80.192 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.063     ; 3.065      ;
; 80.232 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.032     ; 3.056      ;
; 80.265 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.046     ; 3.009      ;
; 80.341 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.063     ; 2.916      ;
; 80.346 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 2.937      ;
; 80.360 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.048     ; 2.912      ;
; 80.374 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.046     ; 2.900      ;
; 80.413 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.044     ; 2.863      ;
; 80.422 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.046     ; 2.852      ;
; 80.450 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.063     ; 2.807      ;
; 80.468 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.044     ; 2.808      ;
; 80.469 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.048     ; 2.803      ;
; 80.493 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.044     ; 2.783      ;
; 80.498 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.063     ; 2.759      ;
; 80.514 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.046     ; 2.760      ;
; 80.517 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.048     ; 2.755      ;
; 80.534 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.044     ; 2.742      ;
; 80.548 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.044     ; 2.728      ;
; 80.555 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.044     ; 2.721      ;
; 80.590 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.063     ; 2.667      ;
; 80.609 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.048     ; 2.663      ;
; 80.614 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.044     ; 2.662      ;
; 80.635 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.044     ; 2.641      ;
; 80.675 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.046     ; 2.599      ;
; 80.730 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.046     ; 2.544      ;
; 80.796 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.046     ; 2.478      ;
; 80.817 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.046     ; 2.457      ;
; 80.835 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.046     ; 2.439      ;
; 80.890 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.046     ; 2.384      ;
; 80.956 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.046     ; 2.318      ;
; 80.977 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.046     ; 2.297      ;
; 81.167 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.117      ;
; 81.167 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.117      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.394 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.958        ; -0.962     ; 0.540      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 2.831 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.405        ; -0.962     ; 0.540      ;
; 5.734 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.080     ; 2.936      ;
; 5.771 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.080     ; 2.899      ;
; 5.773 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.080     ; 2.897      ;
; 5.822 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.080     ; 2.848      ;
; 5.836 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.830      ;
; 5.839 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.827      ;
; 5.840 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.826      ;
; 5.884 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 2.809      ;
; 5.890 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.776      ;
; 5.895 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.771      ;
; 5.918 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.080     ; 2.752      ;
; 5.923 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 2.770      ;
; 5.931 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.735      ;
; 5.932 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.734      ;
; 5.933 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.080     ; 2.737      ;
; 5.934 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.732      ;
; 5.953 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.079     ; 2.718      ;
; 5.955 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 2.738      ;
; 5.958 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 2.735      ;
; 5.959 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 2.734      ;
; 5.965 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.056     ; 2.729      ;
; 5.973 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 2.720      ;
; 5.973 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.073     ; 2.704      ;
; 5.983 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.683      ;
; 5.988 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.080     ; 2.682      ;
; 5.991 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.080     ; 2.679      ;
; 5.992 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.080     ; 2.678      ;
; 5.997 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|ldqm_reg                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.058     ; 2.695      ;
; 6.001 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.665      ;
; 6.004 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.056     ; 2.690      ;
; 6.009 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 2.684      ;
; 6.012 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 2.655      ;
; 6.021 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 2.646      ;
; 6.023 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                    ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.034     ; 2.740      ;
; 6.026 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|udqm_reg                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.086     ; 2.638      ;
; 6.032 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                    ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.034     ; 2.731      ;
; 6.034 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.080     ; 2.636      ;
; 6.035 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 2.658      ;
; 6.041 ; sdram_statemachine:sdram_adaptor|request_sreg                               ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.298     ; 2.458      ;
; 6.042 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.080     ; 2.628      ;
; 6.042 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.624      ;
; 6.044 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.034     ; 2.719      ;
; 6.052 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.059     ; 2.639      ;
; 6.053 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.613      ;
; 6.054 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.072     ; 2.624      ;
; 6.065 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.058     ; 2.627      ;
; 6.066 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.600      ;
; 6.067 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.059     ; 2.624      ;
; 6.068 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.058     ; 2.624      ;
; 6.069 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.058     ; 2.623      ;
; 6.074 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.073     ; 2.603      ;
; 6.079 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.587      ;
; 6.081 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.058     ; 2.611      ;
; 6.091 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.079     ; 2.580      ;
; 6.091 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 2.602      ;
; 6.100 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.034     ; 2.663      ;
; 6.104 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.059     ; 2.587      ;
; 6.104 ; sdram_statemachine:sdram_adaptor|reply_reg                                  ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.046     ; 2.647      ;
; 6.106 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.059     ; 2.585      ;
; 6.107 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.034     ; 2.656      ;
; 6.108 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.081     ; 2.561      ;
; 6.113 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.073     ; 2.564      ;
; 6.114 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 2.553      ;
; 6.119 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.058     ; 2.573      ;
; 6.119 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.058     ; 2.573      ;
; 6.120 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 2.573      ;
; 6.120 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.065     ; 2.565      ;
; 6.126 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.058     ; 2.566      ;
; 6.126 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                    ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.034     ; 2.637      ;
; 6.127 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.058     ; 2.565      ;
; 6.127 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.034     ; 2.636      ;
; 6.130 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.092     ; 2.528      ;
; 6.130 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 2.563      ;
; 6.132 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.534      ;
; 6.135 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.531      ;
; 6.135 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                    ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.034     ; 2.628      ;
; 6.138 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.528      ;
; 6.140 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.056     ; 2.554      ;
; 6.142 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.059     ; 2.549      ;
; 6.144 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|ba_reg[0]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 2.545      ;
; 6.145 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.081     ; 2.524      ;
; 6.147 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.081     ; 2.522      ;
; 6.147 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                    ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.034     ; 2.616      ;
; 6.147 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.034     ; 2.616      ;
; 6.149 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.065     ; 2.536      ;
; 6.153 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.080     ; 2.517      ;
; 6.154 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.079     ; 2.517      ;
; 6.155 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.059     ; 2.536      ;
; 6.155 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.072     ; 2.523      ;
; 6.156 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                    ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.034     ; 2.607      ;
; 6.166 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]                           ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.113     ; 2.471      ;
; 6.168 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.080     ; 2.502      ;
; 6.168 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.034     ; 2.595      ;
; 6.173 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.079     ; 2.498      ;
; 6.177 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.058     ; 2.515      ;
; 6.180 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.073     ; 2.497      ;
; 6.183 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 2.489      ;
; 6.185 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.079     ; 2.486      ;
; 6.187 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]                     ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.034     ; 2.576      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'SPI_SCK'                                                                                                                 ;
+--------+--------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                      ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 15.998 ; user_io:my_user_io|bit_cnt[2]  ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.974     ; 3.881      ;
; 16.092 ; user_io:my_user_io|cmd[1]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.983     ; 3.778      ;
; 16.108 ; user_io:my_user_io|bit_cnt[1]  ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.974     ; 3.771      ;
; 16.314 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.974     ; 3.565      ;
; 16.464 ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.983     ; 3.406      ;
; 16.481 ; user_io:my_user_io|cmd[4]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.386      ;
; 16.481 ; user_io:my_user_io|cmd[4]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.386      ;
; 16.481 ; user_io:my_user_io|cmd[4]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.386      ;
; 16.481 ; user_io:my_user_io|cmd[4]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.386      ;
; 16.481 ; user_io:my_user_io|cmd[4]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.386      ;
; 16.516 ; user_io:my_user_io|cmd[4]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.351      ;
; 16.542 ; user_io:my_user_io|bit_cnt[0]  ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.974     ; 3.337      ;
; 16.543 ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.324      ;
; 16.543 ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.324      ;
; 16.543 ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.324      ;
; 16.543 ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.324      ;
; 16.543 ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.324      ;
; 16.578 ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.289      ;
; 16.682 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.185      ;
; 16.682 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.185      ;
; 16.682 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.185      ;
; 16.682 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.185      ;
; 16.682 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.185      ;
; 16.696 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.171      ;
; 16.696 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.171      ;
; 16.696 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.171      ;
; 16.696 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.171      ;
; 16.696 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.171      ;
; 16.717 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.150      ;
; 16.731 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 3.136      ;
; 16.842 ; user_io:my_user_io|cmd[4]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.985     ; 3.026      ;
; 16.904 ; user_io:my_user_io|cmd[6]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.985     ; 2.964      ;
; 16.916 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 2.951      ;
; 16.916 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 2.951      ;
; 16.916 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 2.951      ;
; 16.916 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 2.951      ;
; 16.916 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 2.951      ;
; 16.951 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 2.916      ;
; 17.043 ; user_io:my_user_io|cmd[7]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.985     ; 2.825      ;
; 17.057 ; user_io:my_user_io|cmd[5]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.985     ; 2.811      ;
; 17.102 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 2.765      ;
; 17.102 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 2.765      ;
; 17.102 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 2.765      ;
; 17.102 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 2.765      ;
; 17.102 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 2.765      ;
; 17.137 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.986     ; 2.730      ;
; 17.162 ; user_io:my_user_io|cmd[3]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.985     ; 2.706      ;
; 17.189 ; user_io:my_user_io|cmd[2]      ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.985     ; 2.679      ;
; 17.189 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.979     ; 2.685      ;
; 17.190 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.979     ; 2.684      ;
; 17.278 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.979     ; 2.596      ;
; 17.319 ; user_io:my_user_io|byte_cnt[1] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.979     ; 2.555      ;
; 17.332 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.979     ; 2.542      ;
; 17.353 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.520      ;
; 17.353 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.520      ;
; 17.353 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.520      ;
; 17.353 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.520      ;
; 17.353 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.520      ;
; 17.354 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.519      ;
; 17.354 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.519      ;
; 17.354 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.519      ;
; 17.354 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.519      ;
; 17.354 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.519      ;
; 17.364 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.975     ; 2.514      ;
; 17.364 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.975     ; 2.514      ;
; 17.364 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.975     ; 2.514      ;
; 17.364 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.975     ; 2.514      ;
; 17.364 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.975     ; 2.514      ;
; 17.399 ; user_io:my_user_io|byte_cnt[0] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.975     ; 2.479      ;
; 17.401 ; user_io:my_user_io|byte_cnt[5] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.472      ;
; 17.402 ; user_io:my_user_io|byte_cnt[4] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.471      ;
; 17.442 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.431      ;
; 17.442 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.431      ;
; 17.442 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.431      ;
; 17.442 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.431      ;
; 17.442 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.431      ;
; 17.490 ; user_io:my_user_io|byte_cnt[6] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.383      ;
; 17.496 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.377      ;
; 17.496 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.377      ;
; 17.496 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.377      ;
; 17.496 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.377      ;
; 17.496 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.377      ;
; 17.530 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.979     ; 2.344      ;
; 17.544 ; user_io:my_user_io|byte_cnt[3] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.329      ;
; 17.554 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.319      ;
; 17.554 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.319      ;
; 17.554 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.319      ;
; 17.554 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.319      ;
; 17.554 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.319      ;
; 17.568 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|SPI_MISO~reg0      ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.979     ; 2.306      ;
; 17.585 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.288      ;
; 17.585 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.288      ;
; 17.585 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.288      ;
; 17.585 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.288      ;
; 17.585 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.288      ;
; 17.602 ; user_io:my_user_io|byte_cnt[7] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.271      ;
; 17.632 ; user_io:my_user_io|byte_cnt[2] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 2.241      ;
; 17.915 ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.984     ; 1.954      ;
; 17.915 ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.984     ; 1.954      ;
; 17.915 ; user_io:my_user_io|cmd[0]      ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.984     ; 1.954      ;
+--------+--------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'CLOCK_27[0]'                                                                                                                                                            ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 35.237 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.750      ;
; 35.285 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.702      ;
; 35.287 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.700      ;
; 35.517 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.470      ;
; 35.535 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 1.453      ;
; 35.675 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 1.313      ;
; 35.691 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 1.297      ;
; 35.695 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.292      ;
; 35.701 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.286      ;
; 35.713 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 1.275      ;
; 35.751 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 1.237      ;
; 35.771 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 1.217      ;
; 35.776 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.211      ;
; 35.815 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 1.173      ;
; 35.830 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 1.158      ;
; 35.845 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 1.143      ;
; 35.852 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.135      ;
; 35.893 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 1.095      ;
; 35.897 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 1.091      ;
; 35.911 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 1.077      ;
; 35.921 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 1.067      ;
; 35.927 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 1.061      ;
; 35.954 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 1.034      ;
; 35.985 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 1.003      ;
; 35.987 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 1.001      ;
; 36.010 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.978      ;
; 36.033 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.955      ;
; 36.066 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.922      ;
; 36.073 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.915      ;
; 36.073 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.915      ;
; 36.079 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.909      ;
; 36.079 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.909      ;
; 36.079 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.909      ;
; 36.086 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.902      ;
; 36.087 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.901      ;
; 36.088 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.900      ;
; 36.134 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.854      ;
; 36.150 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.838      ;
; 36.154 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.834      ;
; 36.154 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.834      ;
; 36.162 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.826      ;
; 36.166 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.822      ;
; 36.166 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.822      ;
; 36.168 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.820      ;
; 36.172 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.816      ;
; 36.174 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.814      ;
; 36.178 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.810      ;
; 36.179 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.809      ;
; 36.180 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.808      ;
; 36.181 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.807      ;
; 36.184 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.804      ;
; 36.185 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.803      ;
; 36.230 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.758      ;
; 36.230 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.758      ;
; 36.234 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.754      ;
; 36.284 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.704      ;
; 36.439 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.549      ;
; 36.446 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.542      ;
; 36.456 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.532      ;
; 36.629 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.359      ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                   ; To Node                                                                                                                                                                                                                                             ; Launch Clock                                                          ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -0.876 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.017        ; 1.299      ; 0.694      ;
; 0.166  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.218      ; 0.488      ;
; 0.167  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|altsyncram:altsyncram4|altsyncram_cul3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.221      ; 0.492      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.196  ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.316      ;
; 0.197  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.317      ;
; 0.197  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.317      ;
; 0.198  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.318      ;
; 0.200  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|tmp_seq_ena_state                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.320      ;
; 0.204  ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.324      ;
; 0.205  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.325      ;
; 0.205  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.325      ;
; 0.209  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reset_state                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.329      ;
; 0.209  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.329      ;
; 0.210  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.330      ;
; 0.213  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.333      ;
; 0.223  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.218      ; 0.545      ;
; 0.240  ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.360      ;
; 0.257  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|tmp_seq_ena_state                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.377      ;
; 0.257  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.377      ;
; 0.259  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_ena_state                                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.379      ;
; 0.262  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_counter_state                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.382      ;
; 0.263  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_counter_state                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.383      ;
; 0.264  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.218      ; 0.586      ;
; 0.265  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate_state                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.385      ;
; 0.266  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.218      ; 0.588      ;
; 0.267  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|tmp_seq_ena_state                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_ena_state                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.387      ;
; 0.269  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.218      ; 0.591      ;
; 0.271  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reset_state                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.391      ;
; 0.271  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reset_state                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.391      ;
; 0.273  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_counter_state                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.393      ;
; 0.276  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_ena_state                                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.396      ;
; 0.277  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.397      ;
; 0.292  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.412      ;
; 0.292  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.412      ;
; 0.293  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.293  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.293  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.295  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.296  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.298  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.299  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.300  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                   ; To Node                                                                                                                                                                                                                                  ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.102 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[4]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.226      ; 0.432      ;
; 0.111 ; sdram_statemachine:sdram_adaptor|data_out_reg[9]                                                                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[9]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 0.314      ;
; 0.112 ; sdram_statemachine:sdram_adaptor|data_out_reg[10]                                                                                                                                                           ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[10]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 0.315      ;
; 0.136 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]                                                                                                            ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a4~porta_datain_reg0                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.463      ;
; 0.138 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.463      ;
; 0.138 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.467      ;
; 0.143 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[4]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.470      ;
; 0.143 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.472      ;
; 0.145 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.473      ;
; 0.145 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]                                                                                                            ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a4~porta_datain_reg0                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.472      ;
; 0.146 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.471      ;
; 0.147 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[2]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.474      ;
; 0.148 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[0]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.473      ;
; 0.148 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.476      ;
; 0.148 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.477      ;
; 0.149 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[7]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.477      ;
; 0.149 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.477      ;
; 0.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.479      ;
; 0.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.477      ;
; 0.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.479      ;
; 0.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[4]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.477      ;
; 0.151 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[0]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.475      ;
; 0.151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.480      ;
; 0.152 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[4]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.481      ;
; 0.153 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe3a[0]                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~portb_address_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.478      ;
; 0.153 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.480      ;
; 0.153 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[7]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.475      ;
; 0.154 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[1] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|altsyncram_eg81:FIFOram|ram_block1a0~porta_address_reg0         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.477      ;
; 0.154 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[6] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|altsyncram_eg81:FIFOram|ram_block1a0~porta_address_reg0         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.477      ;
; 0.154 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]                                                                                                            ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a4~porta_datain_reg0                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.481      ;
; 0.155 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|altsyncram_eg81:FIFOram|ram_block1a0~porta_address_reg0         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.478      ;
; 0.155 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[0]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.482      ;
; 0.155 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.481      ;
; 0.155 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]                                                                                                            ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a4~porta_datain_reg0                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.482      ;
; 0.157 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[0]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.485      ;
; 0.157 ; scandoubler:scandoubler1|colour_reg[2]                                                                                                                                                                      ; scandoubler:scandoubler1|gtia_palette:palette4|altsyncram:Mux21_rtl_0|altsyncram_tt01:auto_generated|ram_block1a0~porta_address_reg0                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.484      ;
; 0.158 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[2]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.481      ;
; 0.158 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.487      ;
; 0.158 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.485      ;
; 0.158 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.481      ;
; 0.159 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[3] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|altsyncram_eg81:FIFOram|ram_block1a0~porta_address_reg0         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.482      ;
; 0.159 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[1]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.483      ;
; 0.159 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[4]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.483      ;
; 0.160 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[4]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.483      ;
; 0.160 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe3a[0]                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~portb_address_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.488      ;
; 0.160 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[1]                                                               ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.485      ;
; 0.161 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[5]                                                               ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.486      ;
; 0.161 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[1]                                                               ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.484      ;
; 0.162 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[5]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.485      ;
; 0.162 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[5]                                                               ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.485      ;
; 0.163 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[2]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.488      ;
; 0.165 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[3]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.489      ;
; 0.166 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.495      ;
; 0.169 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[6]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.492      ;
; 0.169 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[6]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.493      ;
; 0.170 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[0]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.493      ;
; 0.171 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[5]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.495      ;
; 0.172 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[7] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|altsyncram_eg81:FIFOram|ram_block1a0~porta_address_reg0         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.495      ;
; 0.173 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[3]                                                               ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.498      ;
; 0.174 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[3]                                                               ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.497      ;
; 0.175 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[6]                                                               ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.500      ;
; 0.176 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[2]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.500      ;
; 0.176 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[7]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.499      ;
; 0.176 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[4]                                                               ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.501      ;
; 0.176 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[6]                                                               ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.499      ;
; 0.177 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[1]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.500      ;
; 0.177 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[4]                                                               ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.500      ;
; 0.178 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 0.307      ;
; 0.179 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_add_sp2                                                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_add_sp2                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_resync                                                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_resync                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.502      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.180 ; sdram_statemachine:sdram_adaptor|data_out_reg[22]                                                                                                                                                           ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[22]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.099      ; 0.384      ;
; 0.180 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|control_pressed_reg                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|control_pressed_reg                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 0.307      ;
; 0.180 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|break_pressed_reg                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|break_pressed_reg                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 0.307      ;
; 0.180 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|shift_pressed_reg                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|shift_pressed_reg                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 0.307      ;
; 0.183 ; sdram_statemachine:sdram_adaptor|data_out_reg[23]                                                                                                                                                           ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[23]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 0.386      ;
; 0.183 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[0]                                                               ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.508      ;
; 0.184 ; sdram_statemachine:sdram_adaptor|data_out_reg[1]                                                                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[1]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 0.387      ;
; 0.184 ; sdram_statemachine:sdram_adaptor|data_out_reg[27]                                                                                                                                                           ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[27]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 0.387      ;
; 0.184 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[4]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.507      ;
; 0.184 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[0]                                                               ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.507      ;
; 0.185 ; sdram_statemachine:sdram_adaptor|data_out_reg[17]                                                                                                                                                           ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[17]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 0.388      ;
; 0.186 ; sdram_statemachine:sdram_adaptor|data_out_reg[3]                                                                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[3]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 0.389      ;
; 0.186 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                                                         ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[1]                                                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[1]                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[2]                                                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[2]                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[3]                                                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[3]                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[0]                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[0]                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[1]                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[1]                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[2]                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[2]                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[3]                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[3]                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleEnd                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleEnd                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchPage                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchPage                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                             ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                     ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.186 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.187 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.196 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.317      ;
; 0.294 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.295 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.296 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.417      ;
; 0.296 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.297 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.418      ;
; 0.297 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.418      ;
; 0.298 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.298 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.299 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.420      ;
; 0.299 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.420      ;
; 0.302 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.423      ;
; 0.303 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.424      ;
; 0.303 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.424      ;
; 0.303 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.424      ;
; 0.304 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.425      ;
; 0.304 ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.424      ;
; 0.306 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.427      ;
; 0.307 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.428      ;
; 0.307 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.428      ;
; 0.309 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.429      ;
; 0.309 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.429      ;
; 0.311 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.431      ;
; 0.311 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.432      ;
; 0.312 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.432      ;
; 0.314 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.435      ;
; 0.321 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.441      ;
; 0.324 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.444      ;
; 0.334 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 0.524      ;
; 0.336 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 0.526      ;
; 0.337 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 0.527      ;
; 0.364 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.485      ;
; 0.367 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.488      ;
; 0.370 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.491      ;
; 0.372 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.493      ;
; 0.373 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.494      ;
; 0.438 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 0.628      ;
; 0.442 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 0.632      ;
; 0.443 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.563      ;
; 0.444 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.564      ;
; 0.444 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.564      ;
; 0.445 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.565      ;
; 0.445 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.566      ;
; 0.445 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.566      ;
; 0.446 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.567      ;
; 0.446 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.567      ;
; 0.447 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.568      ;
; 0.447 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.568      ;
; 0.450 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.571      ;
; 0.450 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.571      ;
; 0.451 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.572      ;
; 0.452 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.572      ;
; 0.452 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 0.642      ;
; 0.454 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.574      ;
; 0.454 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.574      ;
; 0.454 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.574      ;
; 0.454 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.575      ;
; 0.454 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 0.644      ;
; 0.455 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.576      ;
; 0.455 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.575      ;
; 0.457 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.578      ;
; 0.457 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.578      ;
; 0.457 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.577      ;
; 0.457 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.577      ;
; 0.458 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.578      ;
; 0.458 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.579      ;
; 0.458 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.578      ;
; 0.460 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.581      ;
; 0.460 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.581      ;
; 0.461 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.582      ;
; 0.462 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.583      ;
; 0.462 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.583      ;
; 0.463 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.584      ;
; 0.465 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.586      ;
; 0.465 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.586      ;
; 0.465 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.586      ;
; 0.466 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.587      ;
; 0.468 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.589      ;
; 0.469 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.589      ;
; 0.470 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.590      ;
; 0.470 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.590      ;
; 0.471 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.591      ;
; 0.472 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.592      ;
; 0.473 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.593      ;
; 0.474 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.594      ;
; 0.506 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.626      ;
; 0.507 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.627      ;
; 0.507 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.627      ;
; 0.509 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.630      ;
; 0.509 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.630      ;
; 0.510 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.631      ;
; 0.510 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.630      ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'CLOCK_27[0]'                                                                                                                                                            ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.194 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.299 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.306 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.440 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.560      ;
; 0.442 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.562      ;
; 0.447 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.567      ;
; 0.453 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.573      ;
; 0.453 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.573      ;
; 0.461 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.581      ;
; 0.482 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.602      ;
; 0.501 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.621      ;
; 0.503 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.623      ;
; 0.504 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.624      ;
; 0.510 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.630      ;
; 0.517 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.637      ;
; 0.520 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.640      ;
; 0.527 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.647      ;
; 0.530 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.650      ;
; 0.543 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.663      ;
; 0.565 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.685      ;
; 0.567 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.687      ;
; 0.568 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.688      ;
; 0.570 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.690      ;
; 0.571 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.691      ;
; 0.573 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.693      ;
; 0.574 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.694      ;
; 0.574 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.694      ;
; 0.575 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.695      ;
; 0.576 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.696      ;
; 0.576 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.696      ;
; 0.577 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.697      ;
; 0.577 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.697      ;
; 0.609 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.729      ;
; 0.609 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.729      ;
; 0.610 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.730      ;
; 0.610 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.730      ;
; 0.612 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.732      ;
; 0.612 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.732      ;
; 0.617 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.737      ;
; 0.639 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.759      ;
; 0.639 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.759      ;
; 0.643 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.764      ;
; 0.645 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.765      ;
; 0.645 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.765      ;
; 0.649 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.770      ;
; 0.649 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.770      ;
; 0.676 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.797      ;
; 0.679 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.800      ;
; 0.685 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.806      ;
; 0.685 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.806      ;
; 0.884 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 1.004      ;
; 0.945 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 1.065      ;
; 1.019 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 1.139      ;
; 1.019 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 1.139      ;
; 1.150 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 1.270      ;
; 1.151 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 1.271      ;
; 1.153 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 1.273      ;
; 1.226 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 1.347      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                       ;
+-------+------------------------------------+------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                          ; To Node                            ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------+------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.187 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_rptr[0]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_rptr[1]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|ps2_tx_byte[7]  ; user_io:my_user_io|ps2_tx_byte[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|ps2_parity      ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.307      ;
; 0.194 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.314      ;
; 0.206 ; user_io:my_user_io|ps2_tx_byte[0]  ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.326      ;
; 0.216 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.336      ;
; 0.266 ; user_io:my_user_io|ps2_tx_byte[3]  ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.386      ;
; 0.267 ; user_io:my_user_io|ps2_tx_byte[5]  ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; user_io:my_user_io|ps2_tx_byte[2]  ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; user_io:my_user_io|ps2_tx_byte[1]  ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.387      ;
; 0.268 ; user_io:my_user_io|ps2_tx_byte[6]  ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.388      ;
; 0.269 ; user_io:my_user_io|ps2_tx_byte[4]  ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.389      ;
; 0.293 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.413      ;
; 0.294 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.414      ;
; 0.318 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.438      ;
; 0.320 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.440      ;
; 0.327 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.447      ;
; 0.329 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.449      ;
; 0.331 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.451      ;
; 0.331 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.451      ;
; 0.345 ; user_io:my_user_io|ps2_tx_byte[7]  ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.465      ;
; 0.347 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.467      ;
; 0.372 ; user_io:my_user_io|ps2_r_inc       ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.492      ;
; 0.373 ; user_io:my_user_io|ps2_r_inc       ; user_io:my_user_io|ps2_rptr[1]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.493      ;
; 0.374 ; user_io:my_user_io|ps2_r_inc       ; user_io:my_user_io|ps2_rptr[0]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.494      ;
; 0.421 ; user_io:my_user_io|ps2_parity      ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.541      ;
; 0.423 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.543      ;
; 0.424 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.544      ;
; 0.471 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.591      ;
; 0.483 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.603      ;
; 0.488 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.608      ;
; 0.488 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_rptr[1]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.608      ;
; 0.490 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.610      ;
; 0.513 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.633      ;
; 0.513 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.633      ;
; 0.513 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.633      ;
; 0.516 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.636      ;
; 0.576 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.696      ;
; 0.578 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.698      ;
; 0.581 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.701      ;
; 0.592 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.712      ;
; 0.620 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.740      ;
; 0.632 ; user_io:my_user_io|ps2_kbd_data    ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.752      ;
; 0.633 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.753      ;
; 0.644 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.764      ;
; 0.670 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.790      ;
; 0.683 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.803      ;
; 0.694 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.814      ;
; 0.698 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.818      ;
; 0.701 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.821      ;
; 0.701 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.821      ;
; 0.709 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.829      ;
; 0.716 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.836      ;
; 0.740 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.860      ;
; 0.748 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.868      ;
; 0.750 ; user_io:my_user_io|ps2_tx_byte[0]  ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.870      ;
; 0.758 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.878      ;
; 0.777 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.897      ;
; 0.777 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.897      ;
; 0.777 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.897      ;
; 0.777 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.897      ;
; 0.777 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.897      ;
; 0.777 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.897      ;
; 0.777 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.897      ;
; 0.808 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.928      ;
; 0.808 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.928      ;
; 0.809 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.929      ;
; 0.834 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.954      ;
; 0.834 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.954      ;
; 0.834 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.954      ;
; 0.834 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.954      ;
; 0.834 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.954      ;
; 0.834 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.954      ;
; 0.834 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.954      ;
; 0.837 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.957      ;
; 0.837 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.957      ;
; 0.849 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.969      ;
; 0.850 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.970      ;
; 0.850 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.970      ;
; 0.859 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.979      ;
; 0.861 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.981      ;
; 0.871 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.991      ;
; 0.881 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 1.001      ;
; 0.889 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 1.009      ;
; 0.891 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 1.011      ;
; 0.902 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 1.022      ;
; 0.902 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 1.022      ;
; 0.902 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 1.022      ;
; 0.902 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 1.022      ;
; 0.902 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 1.022      ;
; 0.902 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 1.022      ;
; 0.902 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 1.022      ;
; 0.902 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 1.022      ;
; 0.902 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 1.022      ;
; 0.902 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 1.022      ;
+-------+------------------------------------+------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'SPI_SCK'                                                                                                                           ;
+-------+---------------------------------------+------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                  ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.285 ; user_io:my_user_io|sbuf[6]            ; user_io:my_user_io|joystick_analog_0[7]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.406      ;
; 0.286 ; user_io:my_user_io|sbuf[1]            ; user_io:my_user_io|joystick_analog_0[2]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.407      ;
; 0.289 ; user_io:my_user_io|sbuf[3]            ; user_io:my_user_io|joystick_analog_0[4]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.410      ;
; 0.290 ; user_io:my_user_io|sbuf[3]            ; user_io:my_user_io|sbuf[4]               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.411      ;
; 0.310 ; user_io:my_user_io|sbuf[4]            ; user_io:my_user_io|sbuf[5]               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.431      ;
; 0.350 ; user_io:my_user_io|sbuf[4]            ; user_io:my_user_io|joystick_analog_0[5]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.471      ;
; 0.352 ; user_io:my_user_io|sbuf[5]            ; user_io:my_user_io|sbuf[6]               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.473      ;
; 0.354 ; user_io:my_user_io|sbuf[5]            ; user_io:my_user_io|joystick_analog_0[6]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.475      ;
; 0.356 ; user_io:my_user_io|sbuf[2]            ; user_io:my_user_io|sbuf[3]               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.477      ;
; 0.356 ; user_io:my_user_io|sbuf[2]            ; user_io:my_user_io|joystick_analog_0[3]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.477      ;
; 0.378 ; user_io:my_user_io|sbuf[0]            ; user_io:my_user_io|sbuf[1]               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.499      ;
; 0.420 ; user_io:my_user_io|serial_out_rptr[5] ; user_io:my_user_io|serial_out_rptr[5]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.541      ;
; 0.441 ; user_io:my_user_io|sbuf[0]            ; user_io:my_user_io|joystick_analog_0[1]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.562      ;
; 0.450 ; user_io:my_user_io|sbuf[1]            ; user_io:my_user_io|sbuf[2]               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.571      ;
; 0.458 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|byte_cnt[4]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.579      ;
; 0.460 ; user_io:my_user_io|status[0]          ; user_io:my_user_io|status[0]             ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.581      ;
; 0.474 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|serial_out_rptr[0]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.595      ;
; 0.517 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|bit_cnt[2]            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.638      ;
; 0.522 ; user_io:my_user_io|serial_out_rptr[3] ; user_io:my_user_io|serial_out_rptr[3]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.643      ;
; 0.528 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|byte_cnt[5]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.649      ;
; 0.533 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|bit_cnt[0]            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.654      ;
; 0.535 ; user_io:my_user_io|ps2_wptr[1]        ; user_io:my_user_io|ps2_wptr[1]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.655      ;
; 0.544 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_wptr[0]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.664      ;
; 0.567 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|byte_cnt[7]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.688      ;
; 0.571 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_wptr[1]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.691      ;
; 0.595 ; user_io:my_user_io|serial_out_rptr[4] ; user_io:my_user_io|serial_out_rptr[4]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.716      ;
; 0.598 ; user_io:my_user_io|serial_out_rptr[2] ; user_io:my_user_io|serial_out_rptr[2]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.719      ;
; 0.601 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|bit_cnt[2]            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.722      ;
; 0.603 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_wptr[2]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.723      ;
; 0.604 ; user_io:my_user_io|sbuf[6]            ; user_io:my_user_io|joystick_analog_1[7]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.725      ;
; 0.605 ; user_io:my_user_io|sbuf[0]            ; user_io:my_user_io|joystick_analog_1[9]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.727      ;
; 0.613 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|byte_cnt[4]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.734      ;
; 0.617 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|byte_cnt[3]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.738      ;
; 0.618 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|serial_out_rptr[1]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.739      ;
; 0.620 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|byte_cnt[6]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.741      ;
; 0.628 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_wptr[2]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.748      ;
; 0.633 ; user_io:my_user_io|sbuf[6]            ; user_io:my_user_io|joystick_analog_1[15] ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.755      ;
; 0.637 ; user_io:my_user_io|sbuf[6]            ; user_io:my_user_io|cmd[7]                ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.759      ;
; 0.641 ; user_io:my_user_io|sbuf[5]            ; user_io:my_user_io|joystick_analog_1[14] ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.763      ;
; 0.642 ; user_io:my_user_io|sbuf[5]            ; user_io:my_user_io|cmd[6]                ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.764      ;
; 0.654 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|byte_cnt[1]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.775      ;
; 0.657 ; user_io:my_user_io|sbuf[3]            ; user_io:my_user_io|cmd[4]                ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.779      ;
; 0.660 ; user_io:my_user_io|sbuf[3]            ; user_io:my_user_io|joystick_analog_1[12] ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.782      ;
; 0.661 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|bit_cnt[2]            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.782      ;
; 0.669 ; user_io:my_user_io|serial_out_rptr[4] ; user_io:my_user_io|serial_out_rptr[5]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.790      ;
; 0.671 ; user_io:my_user_io|serial_out_rptr[2] ; user_io:my_user_io|serial_out_rptr[3]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.792      ;
; 0.679 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|byte_cnt[5]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.800      ;
; 0.681 ; user_io:my_user_io|serial_out_rptr[3] ; user_io:my_user_io|serial_out_rptr[5]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.802      ;
; 0.685 ; user_io:my_user_io|ps2_wptr[1]        ; user_io:my_user_io|ps2_wptr[2]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.805      ;
; 0.685 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|serial_out_rptr[3]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.806      ;
; 0.688 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|byte_cnt[5]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.809      ;
; 0.691 ; user_io:my_user_io|serial_out_rptr[1] ; user_io:my_user_io|serial_out_rptr[1]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.812      ;
; 0.694 ; user_io:my_user_io|sbuf[2]            ; user_io:my_user_io|joystick_analog_1[3]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.815      ;
; 0.696 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|byte_cnt[4]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.817      ;
; 0.718 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|byte_cnt[2]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.839      ;
; 0.733 ; user_io:my_user_io|sbuf[4]            ; user_io:my_user_io|joystick_analog_1[13] ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.855      ;
; 0.735 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|bit_cnt[1]            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.856      ;
; 0.735 ; user_io:my_user_io|serial_out_rptr[2] ; user_io:my_user_io|serial_out_rptr[5]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.856      ;
; 0.736 ; user_io:my_user_io|sbuf[4]            ; user_io:my_user_io|cmd[5]                ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.858      ;
; 0.745 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|byte_cnt[7]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.866      ;
; 0.749 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|serial_out_rptr[5]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.870      ;
; 0.751 ; user_io:my_user_io|sbuf[3]            ; user_io:my_user_io|joystick_0[4]         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.041      ; 0.876      ;
; 0.753 ; user_io:my_user_io|serial_out_rptr[3] ; user_io:my_user_io|serial_out_rptr[4]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.874      ;
; 0.757 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|byte_cnt[7]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.878      ;
; 0.758 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|serial_out_rptr[2]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.879      ;
; 0.759 ; user_io:my_user_io|serial_out_rptr[1] ; user_io:my_user_io|serial_out_rptr[3]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.880      ;
; 0.764 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|byte_cnt[4]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.885      ;
; 0.771 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|byte_cnt[5]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.892      ;
; 0.778 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|byte_cnt[6]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.899      ;
; 0.795 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|byte_cnt[3]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.916      ;
; 0.796 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|byte_cnt[2]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.917      ;
; 0.803 ; user_io:my_user_io|sbuf[4]            ; user_io:my_user_io|joystick_analog_1[5]  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.924      ;
; 0.804 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~7            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.035      ; 0.923      ;
; 0.804 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~6            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.035      ; 0.923      ;
; 0.804 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~5            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.035      ; 0.923      ;
; 0.804 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~4            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.035      ; 0.923      ;
; 0.804 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~3            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.035      ; 0.923      ;
; 0.804 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~2            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.035      ; 0.923      ;
; 0.804 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~1            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.035      ; 0.923      ;
; 0.804 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~0            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.035      ; 0.923      ;
; 0.807 ; user_io:my_user_io|serial_out_rptr[2] ; user_io:my_user_io|serial_out_rptr[4]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.928      ;
; 0.809 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~23           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.035      ; 0.928      ;
; 0.809 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~22           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.035      ; 0.928      ;
; 0.809 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~21           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.035      ; 0.928      ;
; 0.809 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~20           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.035      ; 0.928      ;
; 0.809 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~19           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.035      ; 0.928      ;
; 0.809 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~18           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.035      ; 0.928      ;
; 0.809 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~17           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.035      ; 0.928      ;
; 0.809 ; user_io:my_user_io|ps2_wptr[0]        ; user_io:my_user_io|ps2_fifo~16           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.035      ; 0.928      ;
; 0.813 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|byte_cnt[7]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.934      ;
; 0.817 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|bit_cnt[1]            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.938      ;
; 0.821 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|serial_out_rptr[4]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.942      ;
; 0.822 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|byte_cnt[7]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.943      ;
; 0.823 ; user_io:my_user_io|serial_out_rptr[1] ; user_io:my_user_io|serial_out_rptr[5]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.944      ;
; 0.826 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|byte_cnt[0]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.032      ; 0.942      ;
; 0.832 ; user_io:my_user_io|serial_out_rptr[1] ; user_io:my_user_io|serial_out_rptr[2]    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.953      ;
; 0.834 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|byte_cnt[6]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.955      ;
; 0.839 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|byte_cnt[5]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.960      ;
; 0.843 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|byte_cnt[6]           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.964      ;
; 0.861 ; user_io:my_user_io|ps2_wptr[2]        ; user_io:my_user_io|ps2_fifo~23           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.035      ; 0.980      ;
+-------+---------------------------------------+------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 8.103 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -6.853       ; -0.824     ; 0.493      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'CLOCK_27[0]'                                                                                                                                                                                                                               ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                   ; Launch Clock                                                          ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.258 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.745      ; 2.059      ;
; -0.257 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.746      ; 2.059      ;
; -0.257 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.746      ; 2.059      ;
; -0.257 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.746      ; 2.059      ;
; -0.257 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.746      ; 2.059      ;
; -0.257 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.746      ; 2.059      ;
; -0.257 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.746      ; 2.059      ;
; -0.257 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.746      ; 2.059      ;
; -0.257 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.746      ; 2.059      ;
; -0.185 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.748      ; 1.989      ;
; -0.184 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.749      ; 1.989      ;
; -0.184 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.749      ; 1.989      ;
; -0.184 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.749      ; 1.989      ;
; -0.184 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.749      ; 1.989      ;
; -0.184 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.749      ; 1.989      ;
; -0.184 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.749      ; 1.989      ;
; -0.184 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.749      ; 1.989      ;
; -0.184 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.749      ; 1.989      ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                 ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                      ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 6.571 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.126     ; 2.053      ;
; 6.572 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 2.047      ;
; 6.572 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 2.050      ;
; 6.572 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 2.047      ;
; 6.579 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.124     ; 2.047      ;
; 6.581 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.136     ; 2.033      ;
; 6.581 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.133     ; 2.036      ;
; 6.581 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.133     ; 2.036      ;
; 6.582 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.139     ; 2.029      ;
; 6.582 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|udqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.133     ; 2.035      ;
; 6.583 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.187     ; 1.978      ;
; 6.583 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 1.975      ;
; 6.583 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.187     ; 1.978      ;
; 6.584 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.193     ; 1.971      ;
; 6.585 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.122     ; 2.043      ;
; 6.585 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.122     ; 2.043      ;
; 6.586 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.127     ; 2.037      ;
; 6.586 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.127     ; 2.037      ;
; 6.587 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.176     ; 1.985      ;
; 6.587 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.176     ; 1.985      ;
; 6.588 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 2.031      ;
; 6.588 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 2.031      ;
; 6.588 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 2.033      ;
; 6.588 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 2.033      ;
; 6.588 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 2.032      ;
; 6.588 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 2.032      ;
; 6.590 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 1.973      ;
; 6.590 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.184     ; 1.974      ;
; 6.590 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.183     ; 1.975      ;
; 6.590 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 1.973      ;
; 6.590 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.184     ; 1.974      ;
; 6.590 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.183     ; 1.975      ;
; 6.600 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.104     ; 2.046      ;
; 6.600 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.104     ; 2.046      ;
; 6.600 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.104     ; 2.046      ;
; 6.600 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 2.042      ;
; 6.600 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 2.044      ;
; 6.600 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 2.045      ;
; 6.600 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 2.045      ;
; 6.600 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 2.045      ;
; 6.600 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 2.044      ;
; 6.601 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.104     ; 2.045      ;
; 6.601 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 2.041      ;
; 6.601 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 2.042      ;
; 6.601 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 2.043      ;
; 6.601 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 2.044      ;
; 6.601 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.104     ; 2.045      ;
; 6.602 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.158     ; 1.988      ;
; 6.602 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.158     ; 1.988      ;
; 6.602 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.158     ; 1.988      ;
; 6.603 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.158     ; 1.987      ;
; 6.608 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 2.083      ;
; 6.608 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 2.083      ;
; 6.681 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.145     ; 1.912      ;
; 6.681 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 1.915      ;
; 6.681 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 1.915      ;
; 6.682 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.148     ; 1.908      ;
; 6.685 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 1.922      ;
; 6.685 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 1.922      ;
; 6.688 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.140     ; 1.910      ;
; 6.688 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.140     ; 1.910      ;
; 6.688 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.138     ; 1.912      ;
; 6.688 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.138     ; 1.912      ;
; 6.688 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.139     ; 1.911      ;
; 6.688 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.139     ; 1.911      ;
; 6.700 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.113     ; 1.925      ;
; 6.700 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.113     ; 1.925      ;
; 6.700 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.113     ; 1.925      ;
; 6.701 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.113     ; 1.924      ;
; 6.811 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 1.886      ;
; 6.811 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 1.886      ;
; 6.811 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 1.886      ;
; 6.811 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 1.886      ;
; 6.811 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 1.886      ;
; 6.811 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.099     ; 1.887      ;
; 6.811 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.099     ; 1.887      ;
; 6.811 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 1.886      ;
; 6.811 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.099     ; 1.887      ;
; 6.811 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 1.886      ;
; 6.811 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 1.886      ;
; 6.811 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 1.886      ;
; 6.811 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 1.886      ;
; 6.811 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 1.886      ;
; 6.811 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 1.886      ;
; 6.811 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 1.886      ;
; 6.811 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.099     ; 1.887      ;
; 6.811 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 1.886      ;
; 6.811 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 1.886      ;
; 6.818 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 1.886      ;
; 6.818 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 1.886      ;
; 6.818 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.089     ; 1.890      ;
; 6.818 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.089     ; 1.890      ;
; 6.818 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.089     ; 1.890      ;
; 6.818 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 1.886      ;
; 6.818 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 1.886      ;
; 6.818 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 1.886      ;
; 6.818 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 1.886      ;
; 6.818 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 1.885      ;
; 6.818 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 1.886      ;
; 6.818 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 1.886      ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                            ;
+--------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                                                                                                                                ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 14.527 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[1]                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.041     ; 3.040      ;
; 14.533 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.035     ; 3.040      ;
; 14.533 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.035     ; 3.040      ;
; 14.558 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[1]                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 2.960      ;
; 14.564 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 2.960      ;
; 14.564 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 2.960      ;
; 14.565 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[1]                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.040     ; 3.003      ;
; 14.571 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.034     ; 3.003      ;
; 14.571 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.034     ; 3.003      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[0]                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.847      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[1]                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.847      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[2]                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.847      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[3]                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.847      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[4]                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.847      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[5]                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.847      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[6]                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.847      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[7]                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.847      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[8]                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.847      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[9]                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.847      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[10]                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.847      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[11]                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.847      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[12]                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.847      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[13]                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.847      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[2]                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.040     ; 2.851      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|latch_delay_line:stimer_delay|data_in_reg                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[3]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.043     ; 2.848      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizep0_raw_reg[1]                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 2.843      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[3]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.043     ; 2.848      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pl_reg[2]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.043     ; 2.848      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[1]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.043     ; 2.848      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqen_reg[1]                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqst_reg[1]                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[0]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.043     ; 2.848      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[0]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.043     ; 2.848      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[0]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.043     ; 2.848      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[2]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.043     ; 2.848      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqen_reg[2]                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqst_reg[2]                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm3_raw_reg[7]                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.042     ; 2.849      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_snap_reg[7]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.047     ; 2.844      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf2_raw_reg[7]                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 2.843      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf2_snap_reg[7]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.047     ; 2.844      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf2_raw_reg[6]                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 2.843      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf2_snap_reg[6]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.047     ; 2.844      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf1_raw_reg[5]                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.042     ; 2.849      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf2_raw_reg[5]                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 2.843      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf2_snap_reg[5]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.047     ; 2.844      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_snap_reg[5]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.047     ; 2.844      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm3_raw_reg[5]                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.042     ; 2.849      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm2_snap_reg[4]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.047     ; 2.844      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm1_snap_reg[4]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.047     ; 2.844      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm3_snap_reg[4]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.047     ; 2.844      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_snap_reg[4]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.047     ; 2.844      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf2_raw_reg[4]                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 2.843      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf2_snap_reg[4]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.047     ; 2.844      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm1_raw_reg[3]                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.039     ; 2.852      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf2_raw_reg[3]                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 2.843      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf2_snap_reg[3]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.047     ; 2.844      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm3_raw_reg[2]                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.042     ; 2.849      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_snap_reg[2]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.047     ; 2.844      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf2_raw_reg[2]                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 2.843      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf2_snap_reg[2]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.047     ; 2.844      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_snap_reg[1]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.047     ; 2.844      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf2_raw_reg[1]                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 2.843      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf2_snap_reg[1]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.047     ; 2.844      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm3_raw_reg[1]                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.042     ; 2.849      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_noise_filter:pokey_noise_filter0|out_reg                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|chan0_output_reg                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|highpass0_reg                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audc1_reg[5]                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audc1_reg[7]                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audc1_reg[6]                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_noise_filter:pokey_noise_filter1|out_reg                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|chan1_output_reg                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|highpass1_reg                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audc1_reg[0]                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audc1_reg[4]                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|volume_channel_1_reg[0]                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audc1_reg[1]                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|volume_channel_1_reg[1]                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audc1_reg[2]                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|volume_channel_1_reg[2]                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audc1_reg[3]                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|volume_channel_1_reg[3]                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.854      ;
; 14.718 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[14]                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.047     ; 2.843      ;
; 14.718 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[15]                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.047     ; 2.843      ;
; 14.718 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[16]                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.846      ;
; 14.718 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[17]                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.846      ;
; 14.718 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[18]                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.846      ;
; 14.718 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[19]                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.846      ;
; 14.718 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[20]                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.846      ;
; 14.718 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[21]                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.846      ;
; 14.718 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[22]                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.846      ;
; 14.718 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[23]                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.846      ;
; 14.718 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[24]                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.846      ;
; 14.718 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[25]                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.846      ;
; 14.718 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_shift_reg[26]                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 2.846      ;
+--------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'SPI_SCK'                                                                                                            ;
+--------+------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                    ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 18.740 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 1.133      ;
; 18.740 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 1.133      ;
; 18.740 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 1.133      ;
; 18.740 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 1.133      ;
; 18.740 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 1.133      ;
; 18.740 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; -0.980     ; 1.133      ;
+--------+------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'CLOCK_27[0]'                                                                                                                                                                                                                                ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                   ; Launch Clock                                                          ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.521 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.199      ; 1.881      ;
; -0.520 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.199      ; 1.882      ;
; -0.520 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.199      ; 1.882      ;
; -0.520 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.199      ; 1.882      ;
; -0.520 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.199      ; 1.882      ;
; -0.520 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.199      ; 1.882      ;
; -0.520 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.199      ; 1.882      ;
; -0.520 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.199      ; 1.882      ;
; -0.520 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.199      ; 1.882      ;
; -0.458 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.196      ; 1.941      ;
; -0.457 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.196      ; 1.942      ;
; -0.457 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.196      ; 1.942      ;
; -0.457 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.196      ; 1.942      ;
; -0.457 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.196      ; 1.942      ;
; -0.457 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.196      ; 1.942      ;
; -0.457 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.196      ; 1.942      ;
; -0.457 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.196      ; 1.942      ;
; -0.457 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.196      ; 1.942      ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.686 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|dffe4                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.204      ; 0.980      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a63 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a62 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a61 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a60 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a59 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a58 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a57 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a56 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a31 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a29 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a28 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a27 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a26 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a25 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a24 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.118      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a55 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a54 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a53 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a52 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a51 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a50 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a49 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a48 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a47 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a46 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a45 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a44 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a43 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a42 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a41 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a40 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a39 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a38 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a37 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a36 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a35 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a34 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a33 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a32 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a23 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a22 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a21 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a20 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a19 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a18 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a17 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a16 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 0.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 1.122      ;
; 1.316 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|request_sreg                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.297      ; 1.697      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|enable_divider:enable_div|count_reg[2]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 1.682      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|enable_divider:enable_div|count_reg[3]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 1.682      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|enable_divider:enable_div|count_reg[4]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 1.682      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|enable_divider:enable_div|count_reg[5]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 1.682      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|enable_divider:enable_div|count_reg[6]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 1.682      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|enable_divider:enable_div|count_reg[7]                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 1.682      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|enable_divider:enable_div|enabled_out_reg                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 1.682      ;
; 1.506 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[0]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 1.682      ;
; 1.506 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[1]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 1.682      ;
; 1.506 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[19]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.087      ; 1.677      ;
; 1.506 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[31]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.087      ; 1.677      ;
; 1.506 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[24]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.087      ; 1.677      ;
; 1.506 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[28]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.087      ; 1.677      ;
; 1.506 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 1.682      ;
; 1.506 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 1.682      ;
; 1.506 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[4]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 1.682      ;
; 1.506 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; enable_divider:enable_179_clock_div_zpu_pokey|enabled_out_reg                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 1.682      ;
; 1.506 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[21]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.087      ; 1.677      ;
; 1.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[23]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 1.677      ;
; 1.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[29]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 1.677      ;
; 1.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[17]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 1.677      ;
; 1.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[20]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 1.677      ;
; 1.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[25]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 1.677      ;
; 1.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.102      ; 1.697      ;
; 1.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[0]                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 1.693      ;
; 1.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[1]                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 1.693      ;
; 1.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[2]                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 1.693      ;
; 1.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[3]                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 1.693      ;
; 1.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|last_ps2_clk_reg                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 1.693      ;
; 1.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|ps2_shiftreg_reg[10]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 1.691      ;
; 1.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|ps2_shiftreg_reg[9]                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 1.691      ;
; 1.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|ps2_shiftreg_reg[8]                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 1.691      ;
; 1.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|ps2_shiftreg_reg[7]                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 1.691      ;
; 1.511 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|ps2_shiftreg_reg[6]                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 1.691      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                   ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.101      ; 1.696      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.095      ; 1.690      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.095      ; 1.690      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.095      ; 1.690      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.095      ; 1.690      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.095      ; 1.690      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.095      ; 1.690      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.095      ; 1.690      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.095      ; 1.690      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.095      ; 1.690      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.095      ; 1.690      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.095      ; 1.690      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 1.684      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 1.684      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 1.684      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 1.684      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 1.684      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 1.684      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 1.684      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 1.684      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 1.684      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 1.684      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 1.684      ;
; 1.492 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 1.684      ;
; 1.493 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cke_reg                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.096      ; 1.692      ;
; 1.498 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.096      ; 1.697      ;
; 1.498 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.096      ; 1.697      ;
; 1.498 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.096      ; 1.697      ;
; 1.498 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.096      ; 1.697      ;
; 1.498 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.092      ; 1.693      ;
; 1.498 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.092      ; 1.693      ;
; 1.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.092      ; 1.694      ;
; 1.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.092      ; 1.694      ;
; 1.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.677      ;
; 1.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.096      ; 1.698      ;
; 1.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.096      ; 1.698      ;
; 1.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.096      ; 1.698      ;
; 1.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.677      ;
; 1.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.677      ;
; 1.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.677      ;
; 1.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.092      ; 1.694      ;
; 1.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.092      ; 1.694      ;
; 1.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.092      ; 1.694      ;
; 1.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.092      ; 1.694      ;
; 1.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.092      ; 1.694      ;
; 1.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.092      ; 1.694      ;
; 1.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.092      ; 1.694      ;
; 1.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.092      ; 1.694      ;
; 1.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.092      ; 1.694      ;
; 1.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.092      ; 1.694      ;
; 1.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.092      ; 1.694      ;
; 1.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.092      ; 1.694      ;
; 1.499 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.091      ; 1.693      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.694      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.694      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.694      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.694      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.694      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.695      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.694      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.694      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.694      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.694      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.694      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.694      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.694      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.694      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.694      ;
; 1.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.694      ;
; 1.506 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.695      ;
; 1.506 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.695      ;
; 1.506 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.695      ;
; 1.579 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.740      ;
; 1.579 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.740      ;
; 1.579 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 1.739      ;
; 1.579 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 1.739      ;
; 1.596 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.049      ; 1.728      ;
; 1.596 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.049      ; 1.728      ;
; 1.596 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.058      ; 1.737      ;
; 1.596 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.058      ; 1.737      ;
; 1.596 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.050      ; 1.729      ;
; 1.596 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.050      ; 1.729      ;
; 1.597 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.051      ; 1.731      ;
; 1.597 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.051      ; 1.731      ;
; 1.602 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.045      ; 1.730      ;
; 1.602 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.041      ; 1.726      ;
; 1.603 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.047      ; 1.733      ;
; 1.603 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.047      ; 1.733      ;
; 1.685 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.867      ;
; 1.685 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.867      ;
; 1.699 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.860      ;
; 1.699 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.860      ;
; 1.700 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.863      ;
; 1.700 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.863      ;
; 1.700 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.085      ; 1.862      ;
; 1.700 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.085      ; 1.862      ;
; 1.700 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.859      ;
; 1.700 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.858      ;
; 1.700 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.859      ;
; 1.700 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.085      ; 1.862      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'SPI_SCK'                                                                                                             ;
+--------+------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                    ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 19.386 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; -20.800      ; 2.309      ; 0.999      ;
; 19.386 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; -20.800      ; 2.309      ; 0.999      ;
; 19.386 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; -20.800      ; 2.309      ; 0.999      ;
; 19.386 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; -20.800      ; 2.309      ; 0.999      ;
; 19.386 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; -20.800      ; 2.309      ; 0.999      ;
; 19.386 ; user_io:my_user_io|status[0] ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; -20.800      ; 2.309      ; 0.999      ;
+--------+------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                             ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cke_reg                      ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|reply_reg                    ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ;
; 4.192 ; 4.347        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ;
; 4.192 ; 4.347        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ;
; 4.192 ; 4.347        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg                ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                 ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                 ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                 ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                 ;
; 4.197 ; 4.352        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                 ;
; 4.197 ; 4.352        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                 ;
; 4.197 ; 4.352        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                 ;
; 4.198 ; 4.353        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                 ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                     ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 4.331 ; 4.400        ; 0.069          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.357 ; 4.410        ; 0.053          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.400 ; 4.400        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.410 ; 4.410        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                         ;
+-------+--------------+----------------+-----------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type            ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                                                                                                                     ;
+-------+--------------+----------------+-----------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.558 ; 8.788        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                           ;
; 8.558 ; 8.788        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_jf41:auto_generated|ram_block1a0~porta_address_reg0                                 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_jf41:auto_generated|ram_block1a0~porta_we_reg                                       ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                          ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                  ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg       ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_address_reg0    ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_address_reg0   ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|gtia_palette:palette4|altsyncram:Mux21_rtl_0|altsyncram_tt01:auto_generated|ram_block1a0~porta_address_reg0                                                                                                       ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a0~porta_address_reg0                                                                                              ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a0~porta_we_reg                                                                                                    ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a4~porta_address_reg0                                                                                              ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a4~porta_we_reg                                                                                                    ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a0~porta_address_reg0                                                                                              ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a0~porta_we_reg                                                                                                    ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                            ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a10~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a11~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a12~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a13~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a14~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a16~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a23~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a24~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a25~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a26~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a27~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                            ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a30~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a7~porta_address_reg0                                                                                                                            ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a8~porta_address_reg0                                                                                                                            ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a9~porta_address_reg0                                                                                                                            ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                 ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                 ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                          ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                            ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                  ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_jf41:auto_generated|ram_block1a0~porta_datain_reg0                                  ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~portb_address_reg0    ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~portb_address_reg0   ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a4~porta_address_reg0                                                                                              ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a4~porta_we_reg                                                                                                    ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a17~porta_address_reg0                                                                                                                           ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a20~porta_address_reg0                                                                                                                           ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a4~porta_address_reg0                                                                                                                            ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a6~porta_address_reg0                                                                                                                            ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                           ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                 ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                           ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                             ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0     ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a1                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a10                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a11                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12~porta_datain_reg0    ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a2                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a24                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a25                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a26                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a27                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a28                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a29                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a3                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a30                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a31                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a4                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a5                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a56                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a57                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a58                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a59                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a6                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a60                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a61                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a62                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a63                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a7                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a9                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a0~porta_datain_reg0                                                                                               ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a4~porta_datain_reg0                                                                                               ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a0~porta_datain_reg0                                                                                               ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a15~porta_address_reg0                                                                                                                           ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a19~porta_address_reg0                                                                                                                           ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a21~porta_address_reg0                                                                                                                           ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a22~porta_address_reg0                                                                                                                           ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a3~porta_address_reg0                                                                                                                            ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a5~porta_address_reg0                                                                                                                            ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                            ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                            ;
+-------+--------------+----------------+-----------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                           ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                ; Clock Edge ; Target                                                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.310 ; 16.310       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.310 ; 16.310       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.314 ; 16.314       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.316 ; 16.316       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.321 ; 16.321       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.321 ; 16.321       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_27[0]'                                                                                                               ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock       ; Clock Edge ; Target                                                                         ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+
; 17.785 ; 17.969       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 17.785 ; 17.969       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 17.785 ; 17.969       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 17.785 ; 17.969       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 17.785 ; 17.969       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 17.785 ; 17.969       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 17.785 ; 17.969       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 17.785 ; 17.969       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 17.785 ; 17.969       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 17.928 ; 17.928       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 17.928 ; 17.928       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 17.929 ; 17.929       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 17.929 ; 17.929       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 17.960 ; 17.960       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 17.970 ; 17.970       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 17.971 ; 17.971       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 17.972 ; 17.972       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 17.972 ; 17.972       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 19.064 ; 19.064       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 19.064 ; 19.064       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 19.066 ; 19.066       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 19.067 ; 19.067       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 19.072 ; 19.072       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 19.072 ; 19.072       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 19.072 ; 19.072       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 19.072 ; 19.072       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 19.072 ; 19.072       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 19.072 ; 19.072       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 19.072 ; 19.072       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 19.072 ; 19.072       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 19.072 ; 19.072       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 19.077 ; 19.077       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 19.107 ; 19.107       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 19.107 ; 19.107       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 19.108 ; 19.108       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 19.108 ; 19.108       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 33.037 ; 37.037       ; 4.000          ; Port Rate        ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]                                                                    ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'SPI_SCK'                                                                        ;
+--------+--------------+----------------+------------------+---------+------------+-----------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                  ;
+--------+--------------+----------------+------------------+---------+------------+-----------------------------------------+
; 18.317 ; 18.533       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[0]   ;
; 18.317 ; 18.533       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[1]   ;
; 18.317 ; 18.533       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[2]   ;
; 18.317 ; 18.533       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[3]   ;
; 18.317 ; 18.533       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[4]   ;
; 18.317 ; 18.533       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[5]   ;
; 18.318 ; 18.534       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|SPI_MISO~en          ;
; 18.318 ; 18.534       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|SPI_MISO~reg0        ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[0]           ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[1]           ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[2]           ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[0]          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[1]          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[2]          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[3]          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[4]          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[5]          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[6]          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[7]          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[0]               ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[1]               ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~32          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~33          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~34          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~35          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~36          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~37          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~38          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~39          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~40          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~41          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~42          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~43          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~44          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~45          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~46          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~47          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~48          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~49          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~50          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~51          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~52          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~53          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~54          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~55          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~56          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~57          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~58          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~59          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~60          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~61          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~62          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~63          ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sd_dout[0]           ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|stick_idx[0]         ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|stick_idx[1]         ;
; 18.361 ; 18.545       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|stick_idx[2]         ;
; 18.362 ; 18.546       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sd_dout[3]           ;
; 18.362 ; 18.546       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sd_dout[4]           ;
; 18.362 ; 18.546       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sd_dout[6]           ;
; 18.363 ; 18.547       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[2] ;
; 18.363 ; 18.547       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_0[7] ;
; 18.363 ; 18.547       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[1] ;
; 18.363 ; 18.547       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_analog_1[7] ;
; 18.363 ; 18.547       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~10          ;
; 18.363 ; 18.547       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~11          ;
; 18.363 ; 18.547       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~12          ;
; 18.363 ; 18.547       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~13          ;
; 18.363 ; 18.547       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~14          ;
; 18.363 ; 18.547       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~15          ;
; 18.363 ; 18.547       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~16          ;
; 18.363 ; 18.547       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~17          ;
; 18.363 ; 18.547       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~18          ;
; 18.363 ; 18.547       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~19          ;
; 18.363 ; 18.547       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~20          ;
; 18.363 ; 18.547       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~21          ;
; 18.363 ; 18.547       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~22          ;
; 18.363 ; 18.547       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~23          ;
; 18.363 ; 18.547       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~8           ;
; 18.363 ; 18.547       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|ps2_fifo~9           ;
; 18.363 ; 18.547       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sd_dout[1]           ;
; 18.364 ; 18.548       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|but_sw[0]            ;
; 18.364 ; 18.548       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|but_sw[1]            ;
; 18.364 ; 18.548       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[2]               ;
; 18.364 ; 18.548       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[3]               ;
; 18.364 ; 18.548       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[4]               ;
; 18.364 ; 18.548       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[5]               ;
; 18.364 ; 18.548       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[6]               ;
; 18.364 ; 18.548       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[7]               ;
; 18.364 ; 18.548       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_0[0]        ;
; 18.364 ; 18.548       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_0[1]        ;
; 18.364 ; 18.548       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_0[2]        ;
; 18.364 ; 18.548       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_0[3]        ;
; 18.364 ; 18.548       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_0[4]        ;
; 18.364 ; 18.548       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_0[5]        ;
; 18.364 ; 18.548       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_1[0]        ;
; 18.364 ; 18.548       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_1[1]        ;
; 18.364 ; 18.548       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_1[2]        ;
; 18.364 ; 18.548       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_1[3]        ;
; 18.364 ; 18.548       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|joystick_1[4]        ;
+--------+--------------+----------------+------------------+---------+------------+-----------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                                                                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 40.631 ; 41.641       ; 1.010          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                                       ;
; 40.680 ; 41.690       ; 1.010          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                                       ;
; 41.418 ; 41.648       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ;
; 41.418 ; 41.648       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|altsyncram:altsyncram4|altsyncram_cul3:auto_generated|ram_block1a0~porta_address_reg0 ;
; 41.420 ; 41.650       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_datain_reg0                  ;
; 41.420 ; 41.650       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|altsyncram:altsyncram4|altsyncram_cul3:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 41.440 ; 41.656       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate3_state                                                                                   ;
; 41.440 ; 41.656       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate3_state                                                                   ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                                                            ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                                                ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                                                ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                                                ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_ena_state                                                                                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_ena_state                                                                                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_ena_state                                                                                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_ena_state                                                                                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_ena_state                                                                                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                                                   ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate_state                                                                                    ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_counter_state                                                                                ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                                                   ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                                                   ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_ena_state                                                                                ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reset_state                                                                                           ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|tmp_seq_ena_state                                                                                     ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_ena_state                                                                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_ena_state                                                                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_ena_state                                                                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                                         ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                         ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack     ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 44052.599 ; 44052.815    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 44052.599 ; 44052.815    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 44052.599 ; 44052.815    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 44052.599 ; 44052.815    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 44052.599 ; 44052.815    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 44052.599 ; 44052.815    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 44052.599 ; 44052.815    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 44052.599 ; 44052.815    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 44052.599 ; 44052.815    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 44052.599 ; 44052.815    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 44052.599 ; 44052.815    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 44052.599 ; 44052.815    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 44052.745 ; 44052.814    ; 0.069          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 44052.771 ; 44052.824    ; 0.053          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 44052.814 ; 44052.814    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 44052.814 ; 44052.814    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_kbd_data|clk                                                                                                           ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[0]|clk                                                                                                        ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[1]|clk                                                                                                        ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[2]|clk                                                                                                        ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[3]|clk                                                                                                        ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_parity|clk                                                                                                             ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_r_inc|clk                                                                                                              ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[0]|clk                                                                                                            ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[1]|clk                                                                                                            ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[2]|clk                                                                                                            ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[0]|clk                                                                                                         ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[1]|clk                                                                                                         ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[2]|clk                                                                                                         ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[3]|clk                                                                                                         ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[4]|clk                                                                                                         ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[5]|clk                                                                                                         ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[6]|clk                                                                                                         ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[7]|clk                                                                                                         ;
; 44052.821 ; 44052.821    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_parity|clk                                                                                                             ;
; 44052.821 ; 44052.821    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[0]|clk                                                                                                            ;
; 44052.821 ; 44052.821    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[1]|clk                                                                                                            ;
; 44052.821 ; 44052.821    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[2]|clk                                                                                                            ;
; 44052.821 ; 44052.821    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[0]|clk                                                                                                         ;
; 44052.821 ; 44052.821    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[1]|clk                                                                                                         ;
; 44052.821 ; 44052.821    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[2]|clk                                                                                                         ;
; 44052.821 ; 44052.821    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[3]|clk                                                                                                         ;
; 44052.821 ; 44052.821    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[4]|clk                                                                                                         ;
; 44052.821 ; 44052.821    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[5]|clk                                                                                                         ;
; 44052.821 ; 44052.821    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[6]|clk                                                                                                         ;
; 44052.821 ; 44052.821    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[7]|clk                                                                                                         ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_kbd_data|clk                                                                                                           ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_r_inc|clk                                                                                                              ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[0]|clk                                                                                                        ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[1]|clk                                                                                                        ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[2]|clk                                                                                                        ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[3]|clk                                                                                                        ;
; 44052.824 ; 44052.824    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 44052.824 ; 44052.824    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                      ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK     ; 2.061 ; 2.590 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK     ; 2.324 ; 2.384 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.472 ; 2.024 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.467 ; 2.019 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.470 ; 2.022 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.472 ; 2.024 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.472 ; 2.024 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.448 ; 2.006 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.458 ; 2.016 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.448 ; 2.006 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.448 ; 2.006 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.454 ; 2.006 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.454 ; 2.006 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.453 ; 2.005 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.453 ; 2.005 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.460 ; 2.012 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.460 ; 2.012 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.471 ; 2.023 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.471 ; 2.023 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                         ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK     ; 2.369  ; 1.559  ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK     ; 4.059  ; 3.567  ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; -0.969 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; -0.989 ; -1.541 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; -0.993 ; -1.545 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; -0.995 ; -1.547 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; -0.995 ; -1.547 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; -0.969 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; -0.979 ; -1.537 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; -0.970 ; -1.528 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; -0.970 ; -1.528 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; -0.977 ; -1.529 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; -0.977 ; -1.529 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; -0.976 ; -1.528 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; -0.976 ; -1.528 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; -0.983 ; -1.535 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; -0.983 ; -1.535 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; -0.994 ; -1.546 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; -0.994 ; -1.546 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                              ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK     ; 9.293  ; 9.097  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; CLOCK_27[0] ; 1.292  ; 1.163  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 1.165  ; 1.009  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 1.166  ; 1.010  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 1.167  ; 1.011  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 1.177  ; 1.021  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 1.125  ; 0.986  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 1.292  ; 1.163  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 1.277  ; 1.148  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 1.281  ; 1.152  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 1.281  ; 1.152  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 1.280  ; 1.151  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 1.166  ; 1.010  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 1.288  ; 1.159  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 1.164  ; 1.008  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 1.164  ; 1.008  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 1.156  ; 1.000  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 1.240  ; 1.152  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.288  ; 1.159  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.273  ; 1.144  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.269  ; 1.140  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.117  ; 0.978  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.117  ; 0.978  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.178  ; 1.022  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.188  ; 1.032  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.177  ; 1.021  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.177  ; 1.021  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.265  ; 1.136  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.265  ; 1.136  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.286  ; 1.157  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.286  ; 1.157  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.109  ; 0.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.279  ; 1.150  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.288  ; 1.159  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.118  ; 0.979  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 1.265  ; 1.136  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 1.177  ; 1.021  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 1.164  ; 1.008  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 1.163  ; 1.007  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 1.177  ; 1.021  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 4.495  ; 4.481  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 3.308  ; 3.172  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 3.218  ; 3.379  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 12.241 ; 12.264 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 12.041 ; 12.174 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 12.241 ; 12.264 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 12.044 ; 12.027 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 10.835 ; 10.717 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 11.558 ; 11.497 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 11.576 ; 11.639 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 10.652 ; 10.646 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 10.474 ; 10.468 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 10.652 ; 10.646 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 10.637 ; 10.596 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 10.080 ; 10.016 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 10.222 ; 10.246 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 8.186  ; 8.160  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 3.142  ; 2.957  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 12.414 ; 12.374 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 12.161 ; 12.211 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 12.414 ; 12.374 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 12.182 ; 12.113 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 11.348 ; 11.306 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 11.752 ; 11.651 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 11.551 ; 11.686 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 2.974  ; 2.762  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -1.625 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -1.743 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                      ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK     ; 7.443  ; 7.245  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; CLOCK_27[0] ; 0.718  ; 0.579  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 0.758  ; 0.602  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 0.759  ; 0.603  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 0.759  ; 0.603  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 0.718  ; 0.579  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 0.886  ; 0.757  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 0.871  ; 0.742  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 0.875  ; 0.746  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 0.875  ; 0.746  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 0.874  ; 0.745  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 0.758  ; 0.602  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 0.881  ; 0.752  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 0.748  ; 0.592  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 0.756  ; 0.600  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 0.748  ; 0.592  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 0.832  ; 0.743  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 0.703  ; 0.564  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 0.866  ; 0.737  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 0.863  ; 0.734  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 0.711  ; 0.572  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 0.711  ; 0.572  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 0.780  ; 0.624  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 0.859  ; 0.730  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 0.859  ; 0.730  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 0.880  ; 0.751  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 0.880  ; 0.751  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 0.703  ; 0.564  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 0.873  ; 0.744  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 0.882  ; 0.753  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 0.712  ; 0.573  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 0.859  ; 0.730  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 0.769  ; 0.613  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 0.757  ; 0.601  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 0.756  ; 0.600  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 0.769  ; 0.613  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 4.012  ; 3.987  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 2.871  ; 2.731  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 2.775  ; 2.940  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 2.152  ; 2.123  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 2.519  ; 2.540  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 2.519  ; 2.469  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 2.602  ; 2.509  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 2.480  ; 2.366  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 2.152  ; 2.123  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 2.459  ; 2.371  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 2.350  ; 2.346  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 2.350  ; 2.346  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 2.633  ; 2.639  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 2.576  ; 2.527  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 2.691  ; 2.629  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 2.657  ; 2.592  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 2.763  ; 2.706  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 2.714  ; 2.524  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 2.312  ; 2.215  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 2.585  ; 2.513  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 2.312  ; 2.215  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 2.563  ; 2.485  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 2.655  ; 2.609  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 2.576  ; 2.573  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 2.505  ; 2.521  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 2.553  ; 2.337  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -2.008 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -2.127 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+----------------------------------------------------------+
; Propagation Delay                                        ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 5.248 ; 5.248 ; 6.009 ; 5.982 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------+
; Minimum Propagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 4.340 ; 4.223 ; 4.966 ; 4.966 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                              ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK     ; 9.025 ; 8.998 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.933 ; 1.978 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.941 ; 1.986 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.937 ; 1.982 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.955 ; 2.000 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.955 ; 2.000 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.948 ; 2.000 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.958 ; 2.010 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.947 ; 1.999 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.947 ; 1.999 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.933 ; 1.978 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.933 ; 1.978 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.954 ; 1.999 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.954 ; 1.999 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.947 ; 1.992 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.947 ; 1.992 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.956 ; 2.001 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.956 ; 2.001 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                      ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK     ; 6.264 ; 6.264 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 0.726 ; 0.726 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 0.733 ; 0.733 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 0.730 ; 0.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 0.748 ; 0.748 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 0.748 ; 0.748 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 0.780 ; 0.780 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 0.790 ; 0.790 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 0.780 ; 0.780 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 0.780 ; 0.780 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 0.726 ; 0.726 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 0.726 ; 0.726 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 0.747 ; 0.747 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 0.747 ; 0.747 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 0.740 ; 0.740 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 0.740 ; 0.740 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 0.749 ; 0.749 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 0.749 ; 0.749 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                     ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK     ; 9.152     ; 9.152     ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.010     ; 2.010     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.018     ; 2.018     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.014     ; 2.014     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.032     ; 2.032     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.032     ; 2.032     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.032     ; 2.032     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.042     ; 2.042     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.031     ; 2.031     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.031     ; 2.031     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.010     ; 2.010     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.010     ; 2.010     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.031     ; 2.031     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.031     ; 2.031     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.024     ; 2.024     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.024     ; 2.024     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.033     ; 2.033     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.033     ; 2.033     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                             ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK     ; 6.387     ; 6.504     ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 0.757     ; 0.985     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 0.764     ; 0.992     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 0.761     ; 0.989     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 0.779     ; 1.007     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 0.779     ; 1.007     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 0.811     ; 1.055     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 0.821     ; 1.065     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 0.811     ; 1.055     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 0.811     ; 1.055     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 0.757     ; 0.985     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 0.757     ; 0.985     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 0.778     ; 1.006     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 0.778     ; 1.006     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 0.771     ; 0.999     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 0.771     ; 0.999     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 0.780     ; 1.008     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 0.780     ; 1.008     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+----------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                    ;
+------------------------------------------------------------------------+-----------+--------+----------+---------+---------------------+
; Clock                                                                  ; Setup     ; Hold   ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------------------------------------------------------------+-----------+--------+----------+---------+---------------------+
; Worst-case Slack                                                       ; -24.931   ; -1.331 ; -0.827   ; -0.817  ; 4.093               ;
;  CLOCK_27[0]                                                           ; 32.787    ; 0.187  ; -0.827   ; -0.817  ; 17.785              ;
;  SPI_SCK                                                               ; 8.258     ; 0.285  ; 14.514   ; 18.903  ; 16.636              ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.906     ; 0.186  ; 4.117    ; 1.492   ; 4.093               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -24.931   ; 0.102  ; 11.003   ; 0.686   ; 8.372               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.530    ; 8.103  ; N/A      ; N/A     ; 4.225               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; -16.485   ; 0.187  ; N/A      ; N/A     ; 44052.505           ;
;  pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A       ; N/A    ; N/A      ; N/A     ; 16.276              ;
;  reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; -0.396    ; -1.331 ; N/A      ; N/A     ; 40.596              ;
; Design-wide TNS                                                        ; -3616.04  ; -1.331 ; -7.435   ; -7.353  ; 0.0                 ;
;  CLOCK_27[0]                                                           ; 0.000     ; 0.000  ; -7.435   ; -7.353  ; 0.000               ;
;  SPI_SCK                                                               ; 0.000     ; 0.000  ; 0.000    ; 0.000   ; 0.000               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000     ; 0.000  ; 0.000    ; 0.000   ; 0.000               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -3419.723 ; 0.000  ; 0.000    ; 0.000   ; 0.000               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.530    ; 0.000  ; N/A      ; N/A     ; 0.000               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; -194.448  ; 0.000  ; N/A      ; N/A     ; 0.000               ;
;  pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A       ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; -0.396    ; -1.331 ; N/A      ; N/A     ; 0.000               ;
+------------------------------------------------------------------------+-----------+--------+----------+---------+---------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                      ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK     ; 4.018 ; 4.789 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK     ; 4.334 ; 4.789 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 3.028 ; 3.141 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 3.023 ; 3.136 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 3.026 ; 3.139 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 3.028 ; 3.141 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 3.028 ; 3.141 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.965 ; 3.082 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.975 ; 3.092 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.965 ; 3.082 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.966 ; 3.083 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 3.009 ; 3.122 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 3.009 ; 3.122 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 3.000 ; 3.113 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 3.000 ; 3.113 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 3.013 ; 3.126 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 3.013 ; 3.126 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 3.024 ; 3.137 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 3.024 ; 3.137 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                         ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK     ; 5.886  ; 5.588  ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK     ; 9.605  ; 9.380  ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; -0.969 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; -0.989 ; -1.541 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; -0.993 ; -1.545 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; -0.995 ; -1.547 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; -0.995 ; -1.547 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; -0.969 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; -0.979 ; -1.537 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; -0.970 ; -1.528 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; -0.970 ; -1.528 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; -0.977 ; -1.529 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; -0.977 ; -1.529 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; -0.976 ; -1.528 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; -0.976 ; -1.528 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; -0.983 ; -1.535 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; -0.983 ; -1.535 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; -0.994 ; -1.546 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; -0.994 ; -1.546 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                              ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK     ; 18.176 ; 17.609 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; CLOCK_27[0] ; 2.751  ; 2.413  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 2.526  ; 2.239  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 2.528  ; 2.241  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 2.528  ; 2.241  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 2.539  ; 2.252  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 2.450  ; 2.189  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 2.751  ; 2.413  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 2.735  ; 2.397  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 2.740  ; 2.402  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 2.740  ; 2.402  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 2.736  ; 2.398  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 2.527  ; 2.240  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 2.743  ; 2.405  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 2.526  ; 2.239  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 2.526  ; 2.239  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 2.517  ; 2.230  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 2.787  ; 2.520  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.743  ; 2.405  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.724  ; 2.386  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.720  ; 2.382  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.435  ; 2.174  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.435  ; 2.174  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.540  ; 2.253  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.550  ; 2.263  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.540  ; 2.253  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.539  ; 2.252  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.717  ; 2.379  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.717  ; 2.379  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.743  ; 2.405  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.743  ; 2.405  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.431  ; 2.170  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.734  ; 2.396  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.743  ; 2.405  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.440  ; 2.179  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 2.716  ; 2.378  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 2.539  ; 2.252  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 2.526  ; 2.239  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 2.526  ; 2.239  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 2.539  ; 2.252  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 8.921  ; 8.165  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 6.313  ; 5.631  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 5.728  ; 6.526  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 28.098 ; 27.588 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 27.654 ; 27.158 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 28.098 ; 27.588 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 27.595 ; 27.031 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 24.821 ; 24.466 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 26.529 ; 26.089 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 26.694 ; 26.203 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 24.458 ; 23.845 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 23.850 ; 23.367 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 24.458 ; 23.845 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 24.257 ; 23.659 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 22.940 ; 22.433 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 23.560 ; 22.782 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 18.724 ; 18.183 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 6.008  ; 5.275  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 29.151 ; 28.660 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 28.514 ; 28.018 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 29.151 ; 28.660 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 28.379 ; 27.906 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 26.631 ; 26.120 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 27.497 ; 27.114 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 27.144 ; 26.604 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 5.620  ; 4.925  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -0.556 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -0.944 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                      ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK     ; 7.443  ; 7.245  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; CLOCK_27[0] ; 0.718  ; 0.579  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 0.758  ; 0.602  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 0.759  ; 0.603  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 0.759  ; 0.603  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 0.718  ; 0.579  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 0.886  ; 0.757  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 0.871  ; 0.742  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 0.875  ; 0.746  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 0.875  ; 0.746  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 0.874  ; 0.745  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 0.758  ; 0.602  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 0.881  ; 0.752  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 0.748  ; 0.592  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 0.756  ; 0.600  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 0.748  ; 0.592  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 0.832  ; 0.743  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 0.703  ; 0.564  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 0.866  ; 0.737  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 0.863  ; 0.734  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 0.711  ; 0.572  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 0.711  ; 0.572  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 0.780  ; 0.624  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 0.859  ; 0.730  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 0.859  ; 0.730  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 0.880  ; 0.751  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 0.880  ; 0.751  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 0.703  ; 0.564  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 0.873  ; 0.744  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 0.882  ; 0.753  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 0.712  ; 0.573  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 0.859  ; 0.730  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 0.769  ; 0.613  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 0.757  ; 0.601  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 0.756  ; 0.600  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 0.769  ; 0.613  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 4.012  ; 3.987  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 2.871  ; 2.731  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 2.775  ; 2.940  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 2.152  ; 2.123  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 2.519  ; 2.540  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 2.519  ; 2.469  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 2.602  ; 2.509  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 2.480  ; 2.366  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 2.152  ; 2.123  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 2.459  ; 2.371  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 2.350  ; 2.346  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 2.350  ; 2.346  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 2.633  ; 2.639  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 2.576  ; 2.527  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 2.691  ; 2.629  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 2.657  ; 2.592  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 2.763  ; 2.706  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 2.714  ; 2.524  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 2.312  ; 2.215  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 2.585  ; 2.513  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 2.312  ; 2.215  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 2.563  ; 2.485  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 2.655  ; 2.609  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 2.576  ; 2.573  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 2.505  ; 2.521  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 2.553  ; 2.337  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -2.008 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -2.127 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+----------------------------------------------------------+
; Progagation Delay                                        ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 9.387 ; 9.147 ; 9.839 ; 9.839 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------+
; Minimum Progagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 4.340 ; 4.223 ; 4.966 ; 4.966 ;
+------------+-------------+-------+-------+-------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin          ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; VGA_VS       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_HS       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_L      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_R      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[0]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[1]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nCS    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nRAS   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nCAS   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nWE    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQMH   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQML   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CLK    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CKE    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[0]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[1]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[2]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[3]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[4]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[5]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[6]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[7]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[8]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[9]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[10]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[11]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[12]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; UART_TX      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SPI_DO       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+------------------------------------------------------------------+
; Input Transition Times                                           ;
+---------------+--------------+-----------------+-----------------+
; Pin           ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+---------------+--------------+-----------------+-----------------+
; CLOCK_27[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; UART_RX       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SS2       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SS3       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SS4       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[2]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[3]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[4]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[5]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[6]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[7]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[8]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[9]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[10]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[11]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[12]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[13]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[14]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[15]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_DO        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_DI        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CONF_DATA0    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CLOCK_27[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SCK       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+---------------+--------------+-----------------+-----------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; VGA_HS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_L      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.08 V              ; -0.00545 V          ; 0.234 V                              ; 0.291 V                              ; 5.77e-09 s                  ; 4.44e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.01e-07 V                  ; 3.08 V             ; -0.00545 V         ; 0.234 V                             ; 0.291 V                             ; 5.77e-09 s                 ; 4.44e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_nCS    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_nRAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_nCAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_nWE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQMH   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQML   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_CLK    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_CKE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.022 V                              ; 0.093 V                              ; 1.48e-09 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.022 V                             ; 0.093 V                             ; 1.48e-09 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[0]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[1]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[2]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[3]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[4]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.022 V                              ; 0.093 V                              ; 1.48e-09 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.022 V                             ; 0.093 V                             ; 1.48e-09 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[5]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[6]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[7]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[8]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[9]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[10]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[11]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[12]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.022 V                              ; 0.093 V                              ; 1.48e-09 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.022 V                             ; 0.093 V                             ; 1.48e-09 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; LED          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.08 V              ; -0.00545 V          ; 0.234 V                              ; 0.291 V                              ; 5.77e-09 s                  ; 4.44e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.01e-07 V                  ; 3.08 V             ; -0.00545 V         ; 0.234 V                             ; 0.291 V                             ; 5.77e-09 s                 ; 4.44e-09 s                 ; Yes                       ; Yes                       ;
; UART_TX      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.022 V                              ; 0.093 V                              ; 1.48e-09 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.022 V                             ; 0.093 V                             ; 1.48e-09 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.022 V                              ; 0.093 V                              ; 1.48e-09 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.022 V                             ; 0.093 V                             ; 1.48e-09 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.022 V                              ; 0.093 V                              ; 1.48e-09 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.022 V                             ; 0.093 V                             ; 1.48e-09 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.022 V                              ; 0.093 V                              ; 1.48e-09 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.022 V                             ; 0.093 V                             ; 1.48e-09 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SPI_DO       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.08 V              ; -0.00545 V          ; 0.234 V                              ; 0.291 V                              ; 5.77e-09 s                  ; 4.44e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.01e-07 V                  ; 3.08 V             ; -0.00545 V         ; 0.234 V                             ; 0.291 V                             ; 5.77e-09 s                 ; 4.44e-09 s                 ; Yes                       ; Yes                       ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; VGA_HS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; VGA_B[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_B[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_B[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_B[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_B[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_B[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_G[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; VGA_G[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_G[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_G[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_G[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_G[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_R[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_R[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_R[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_R[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_R[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_R[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; AUDIO_L      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; AUDIO_R      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.48 V              ; -0.0164 V           ; 0.353 V                              ; 0.315 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.48 V             ; -0.0164 V          ; 0.353 V                             ; 0.315 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; SDRAM_BA[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_BA[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_nCS    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_nRAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_nCAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_nWE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQMH   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQML   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_CLK    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_CKE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.5 V               ; -0.0534 V           ; 0.346 V                              ; 0.247 V                              ; 9.06e-10 s                  ; 6.55e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 2.22e-07 V                  ; 3.5 V              ; -0.0534 V          ; 0.346 V                             ; 0.247 V                             ; 9.06e-10 s                 ; 6.55e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[0]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[1]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[2]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[3]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[4]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.5 V               ; -0.0534 V           ; 0.346 V                              ; 0.247 V                              ; 9.06e-10 s                  ; 6.55e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 2.22e-07 V                  ; 3.5 V              ; -0.0534 V          ; 0.346 V                             ; 0.247 V                             ; 9.06e-10 s                 ; 6.55e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[5]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_A[6]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_A[7]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_A[8]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_A[9]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_A[10]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[11]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_A[12]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.5 V               ; -0.0534 V           ; 0.346 V                              ; 0.247 V                              ; 9.06e-10 s                  ; 6.55e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 2.22e-07 V                  ; 3.5 V              ; -0.0534 V          ; 0.346 V                             ; 0.247 V                             ; 9.06e-10 s                 ; 6.55e-10 s                 ; Yes                       ; Yes                       ;
; LED          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.48 V              ; -0.0164 V           ; 0.353 V                              ; 0.315 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.48 V             ; -0.0164 V          ; 0.353 V                             ; 0.315 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; UART_TX      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.5 V               ; -0.0534 V           ; 0.346 V                              ; 0.247 V                              ; 9.06e-10 s                  ; 6.55e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 2.22e-07 V                  ; 3.5 V              ; -0.0534 V          ; 0.346 V                             ; 0.247 V                             ; 9.06e-10 s                 ; 6.55e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.5 V               ; -0.0534 V           ; 0.346 V                              ; 0.247 V                              ; 9.06e-10 s                  ; 6.55e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 2.22e-07 V                  ; 3.5 V              ; -0.0534 V          ; 0.346 V                             ; 0.247 V                             ; 9.06e-10 s                 ; 6.55e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.5 V               ; -0.0534 V           ; 0.346 V                              ; 0.247 V                              ; 9.06e-10 s                  ; 6.55e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 2.22e-07 V                  ; 3.5 V              ; -0.0534 V          ; 0.346 V                             ; 0.247 V                             ; 9.06e-10 s                 ; 6.55e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.5 V               ; -0.0534 V           ; 0.346 V                              ; 0.247 V                              ; 9.06e-10 s                  ; 6.55e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 2.22e-07 V                  ; 3.5 V              ; -0.0534 V          ; 0.346 V                             ; 0.247 V                             ; 9.06e-10 s                 ; 6.55e-10 s                 ; Yes                       ; Yes                       ;
; SPI_DO       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.48 V              ; -0.0164 V           ; 0.353 V                              ; 0.315 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.48 V             ; -0.0164 V          ; 0.353 V                             ; 0.315 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                           ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; CLOCK_27[0]                                                           ; CLOCK_27[0]                                                           ; 85       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2473     ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 120      ; 0        ; 1        ; 0        ;
; CLOCK_27[0]                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1        ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 39       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 24814625 ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 6        ; 1        ; 0        ; 0        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2        ; 0        ; 0        ; 0        ;
; SPI_SCK                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 5416     ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0        ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0        ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 260      ; 0        ; 0        ; 0        ;
; SPI_SCK                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 100      ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 1        ; 0        ; 0        ; 0        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 2115     ; 7        ; 42       ; 1        ;
; SPI_SCK                                                               ; SPI_SCK                                                               ; 3072     ; 0        ; 229      ; 63       ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                            ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; CLOCK_27[0]                                                           ; CLOCK_27[0]                                                           ; 85       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2473     ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 120      ; 0        ; 1        ; 0        ;
; CLOCK_27[0]                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1        ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 39       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 24814625 ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 6        ; 1        ; 0        ; 0        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2        ; 0        ; 0        ; 0        ;
; SPI_SCK                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 5416     ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0        ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0        ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 260      ; 0        ; 0        ; 0        ;
; SPI_SCK                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 100      ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 1        ; 0        ; 0        ; 0        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 2115     ; 7        ; 42       ; 1        ;
; SPI_SCK                                                               ; SPI_SCK                                                               ; 3072     ; 0        ; 229      ; 63       ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                                        ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0]                                                           ; 18       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 141      ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 7888     ; 0        ; 0        ; 0        ;
; SPI_SCK                                                               ; SPI_SCK                                                               ; 0        ; 0        ; 6        ; 0        ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                                         ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0]                                                           ; 18       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 141      ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 7888     ; 0        ; 0        ; 0        ;
; SPI_SCK                                                               ; SPI_SCK                                                               ; 0        ; 0        ; 6        ; 0        ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 5     ; 5    ;
; Unconstrained Input Ports       ; 18    ; 18   ;
; Unconstrained Input Port Paths  ; 194   ; 194  ;
; Unconstrained Output Ports      ; 61    ; 61   ;
; Unconstrained Output Port Paths ; 152   ; 152  ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Sat Feb  6 21:48:01 2021
Info: Command: quartus_sta atari800core -c atari800core
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 12 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 6 of the 6 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'atari800core.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 27 -multiply_by 100 -duty_cycle 50.00 -name {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]} {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 27 -multiply_by 50 -duty_cycle 50.00 -name {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]} {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 27 -multiply_by 100 -phase -100.00 -duty_cycle 50.00 -name {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]} {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2700 -phase -0.01 -duty_cycle 50.00 -name {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]} {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]}
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 200 -multiply_by 227 -duty_cycle 50.00 -name {pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]} {pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 9 -multiply_by 4 -duty_cycle 50.00 -name {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]} {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}
Warning (332174): Ignored filter at atari800core.sdc(3): clock|altpll_component|auto_generated|pll1|clk[2] could not be matched with a pin
Warning (332049): Ignored create_generated_clock at atari800core.sdc(3): Argument -source is an empty collection
    Info (332050): create_generated_clock -name sdclk_pin -source [get_pins {clock|altpll_component|auto_generated|pll1|clk[2]}] [get_ports {SDRAM_CLK}]
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332174): Ignored filter at atari800core.sdc(5): sdclk_pin could not be matched with a clock
Warning (332049): Ignored set_input_delay at atari800core.sdc(5): Argument -clock is not an object ID
    Info (332050): set_input_delay -clock sdclk_pin -max 6.4 [get_ports SDRAM_DQ*]
Warning (332049): Ignored set_input_delay at atari800core.sdc(6): Argument -clock is not an object ID
    Info (332050): set_input_delay -clock sdclk_pin -min 3.2 [get_ports SDRAM_DQ*]
Warning (332049): Ignored set_output_delay at atari800core.sdc(7): Argument -clock is not an object ID
    Info (332050): set_output_delay -clock sdclk_pin -max 1.5 [get_ports SDRAM_*]
Warning (332049): Ignored set_output_delay at atari800core.sdc(8): Argument -clock is not an object ID
    Info (332050): set_output_delay -clock sdclk_pin -min -0.8 [get_ports SDRAM_*]
Warning (332174): Ignored filter at atari800core.sdc(9): clock|altpll_component|auto_generated|pll1|clk[0] could not be matched with a clock
Warning (332049): Ignored set_multicycle_path at atari800core.sdc(9): Argument <from> is an empty collection
    Info (332050): set_multicycle_path -from [get_clocks {sdclk_pin}] -to [get_clocks {clock|altpll_component|auto_generated|pll1|clk[0]}] -setup -end 2
Warning (332049): Ignored set_multicycle_path at atari800core.sdc(9): Argument <to> is an empty collection
Warning (332049): Ignored create_clock at atari800core.sdc(12): Incorrect assignment for clock.  Source node: CLOCK_27[0] already has a clock(s) assigned to it.  Use the -add option to assign multiple clocks to this node.  Clock was not created or updated.
    Info (332050): create_clock -name {clk_27} -period 37.037 -waveform { 0.000 18.500 } [get_ports {CLOCK_27[0]}]
Warning (332174): Ignored filter at atari800core.sdc(14): clk could not be matched with a clock
Warning (332125): Found combinational loop of 4 nodes
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[0]~6|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[0]~5|dataa"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[0]~5|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[0]~6|dataa"
Warning (332125): Found combinational loop of 4 nodes
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[0]~6|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[0]~4|datad"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[0]~4|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[0]~6|dataa"
Warning (332125): Found combinational loop of 4 nodes
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[1]~8|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[1]~7|datad"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[1]~7|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[1]~8|dataa"
Warning (332125): Found combinational loop of 4 nodes
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[1]~9|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[1]~7|datad"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[1]~7|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[1]~9|dataa"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "my_user_io|spi_sck~0|combout"
    Warning (332126): Node "my_user_io|spi_sck~0|dataa"
Warning (332060): Node: zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: user_io:my_user_io|sd_ack was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: sd_card:my_sd_card|read_state.RD_STATE_IDLE was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: user_io:my_user_io|sd_dout_strobe was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: sd_card:my_sd_card|write_state.WR_STATE_BUSY was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Warning (332009): The launch and latch times for the relationship between source clock: SPI_SCK and destination clock: pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Warning (332009): The launch and latch times for the relationship between source clock: SPI_SCK and destination clock: pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -24.931
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):   -24.931     -3419.723 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):   -16.485      -194.448 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):    -1.530        -1.530 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    -0.339        -0.339 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.906         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     8.258         0.000 SPI_SCK 
    Info (332119):    32.787         0.000 CLOCK_27[0] 
Warning (332009): The launch and latch times for the relationship between source clock: SPI_SCK and destination clock: pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Info (332146): Worst-case hold slack is -1.331
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.331        -1.331 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.344         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.453         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.454         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):     0.455         0.000 CLOCK_27[0] 
    Info (332119):     0.741         0.000 SPI_SCK 
    Info (332119):     9.616         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -0.800
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.800        -7.200 CLOCK_27[0] 
    Info (332119):     4.117         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    11.003         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    14.514         0.000 SPI_SCK 
Info (332146): Worst-case removal slack is -0.817
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.817        -7.353 CLOCK_27[0] 
    Info (332119):     1.593         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     3.268         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    18.903         0.000 SPI_SCK 
Info (332146): Worst-case minimum pulse width slack is 4.093
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.093         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.225         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.372         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    16.276         0.000 pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    16.636         0.000 SPI_SCK 
    Info (332119):    18.277         0.000 CLOCK_27[0] 
    Info (332119):    40.596         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119): 44052.505         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
Warning (332009): The launch and latch times for the relationship between source clock: SPI_SCK and destination clock: pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Warning (332060): Node: zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: user_io:my_user_io|sd_ack was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: sd_card:my_sd_card|read_state.RD_STATE_IDLE was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: user_io:my_user_io|sd_dout_strobe was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: sd_card:my_sd_card|write_state.WR_STATE_BUSY was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Warning (332009): The launch and latch times for the relationship between source clock: SPI_SCK and destination clock: pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -23.058
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):   -23.058     -3167.912 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):   -15.220      -178.913 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):    -1.227        -1.227 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    -0.396        -0.396 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.210         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     9.068         0.000 SPI_SCK 
    Info (332119):    33.089         0.000 CLOCK_27[0] 
Warning (332009): The launch and latch times for the relationship between source clock: SPI_SCK and destination clock: pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Info (332146): Worst-case hold slack is -1.160
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.160        -1.160 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.330         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.402         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.403         0.000 CLOCK_27[0] 
    Info (332119):     0.403         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):     0.675         0.000 SPI_SCK 
    Info (332119):     9.330         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -0.827
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.827        -7.435 CLOCK_27[0] 
    Info (332119):     4.551         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    11.511         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    14.873         0.000 SPI_SCK 
Info (332146): Worst-case removal slack is -0.608
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.608        -5.464 CLOCK_27[0] 
    Info (332119):     1.467         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     2.940         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    19.144         0.000 SPI_SCK 
Info (332146): Worst-case minimum pulse width slack is 4.097
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.097         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.243         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.403         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    16.279         0.000 pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    16.988         0.000 SPI_SCK 
    Info (332119):    18.273         0.000 CLOCK_27[0] 
    Info (332119):    40.596         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119): 44052.511         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
Warning (332009): The launch and latch times for the relationship between source clock: SPI_SCK and destination clock: pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Info: Analyzing Fast 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Warning (332060): Node: zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: user_io:my_user_io|sd_ack was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: sd_card:my_sd_card|read_state.RD_STATE_IDLE was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: user_io:my_user_io|sd_dout_strobe was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: sd_card:my_sd_card|write_state.WR_STATE_BUSY was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Warning (332009): The launch and latch times for the relationship between source clock: SPI_SCK and destination clock: pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -10.797
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):   -10.797     -1499.814 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -7.317       -86.005 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):     0.064         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.394         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     2.831         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    15.998         0.000 SPI_SCK 
    Info (332119):    35.237         0.000 CLOCK_27[0] 
Warning (332009): The launch and latch times for the relationship between source clock: SPI_SCK and destination clock: pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Info (332146): Worst-case hold slack is -0.876
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.876        -0.876 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.102         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.186         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.187         0.000 CLOCK_27[0] 
    Info (332119):     0.187         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):     0.285         0.000 SPI_SCK 
    Info (332119):     8.103         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -0.258
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.258        -2.314 CLOCK_27[0] 
    Info (332119):     6.571         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    14.527         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    18.740         0.000 SPI_SCK 
Info (332146): Worst-case removal slack is -0.521
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.521        -4.681 CLOCK_27[0] 
    Info (332119):     0.686         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     1.492         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    19.386         0.000 SPI_SCK 
Info (332146): Worst-case minimum pulse width slack is 4.186
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.186         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.331         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.558         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    16.300         0.000 pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.785         0.000 CLOCK_27[0] 
    Info (332119):    18.317         0.000 SPI_SCK 
    Info (332119):    40.631         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119): 44052.599         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
Warning (332009): The launch and latch times for the relationship between source clock: SPI_SCK and destination clock: pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Warning (332009): The launch and latch times for the relationship between source clock: SPI_SCK and destination clock: pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 64 warnings
    Info: Peak virtual memory: 562 megabytes
    Info: Processing ended: Sat Feb  6 21:48:11 2021
    Info: Elapsed time: 00:00:10
    Info: Total CPU time (on all processors): 00:00:14


